Most drivers use these access methods but a few do not. Update them.
In some cases the access is not permitted, so mark those with a FIXME tag
for the maintainer to check.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Pratyush Yadav <p.yadav@ti.com>
continue;
}
+#ifdef CONFIG_DM_ETH
+ priv = dev_get_priv(dev);
+#else
priv = dev->priv;
+#endif
if (priv->flags & TSEC_SGMII)
continue;
#include <syscon.h>
#include <asm/io.h>
#include <dm/device_compat.h>
+#include <dm/device-internal.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <power/pmic.h>
}
uc_pdata->type = REGULATOR_TYPE_FIXED;
- dev->priv = (void *)*p;
+ dev_set_priv(dev, (void *)*p);
return 0;
}
#include <asm/io.h>
#include <asm/pci.h>
#include <asm/lpss.h>
+#include <dm/device-internal.h>
/* Low-power Subsystem (LPSS) clock register */
enum {
plat->clock = dtplat->clock_frequency;
plat->fcr = UART_FCR_DEFVAL;
plat->bdf = pci_ofplat_get_devfn(dtplat->reg[0]);
- dev->plat = plat;
+ dev_set_plat(dev, plat);
#else
int ret;
{
const efi_guid_t guid = SBL_SERIAL_PORT_INFO_GUID;
struct sbl_serial_port_info *data;
- struct ns16550_plat *plat = dev->plat;
+ struct ns16550_plat *plat = dev_get_plat(dev);
if (!gd->arch.hob_list)
panic("hob list not found!");
}
clk->enable_count = 0;
+
/* Store back pointer to clk from udevice */
- clk->dev->uclass_priv = clk;
+ /* FIXME: This is not allowed...should be allocated by driver model */
+ dev_set_uclass_priv(clk->dev, clk);
return 0;
}
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
+#include <dm/device-internal.h>
#include <linux/clk-provider.h>
static ulong clk_fixed_rate_get_rate(struct clk *clk)
dev_read_u32_default(dev, "clock-frequency", 0);
#endif
/* Make fixed rate clock accessible from higher level struct clk */
- dev->uclass_priv = clk;
+ /* FIXME: This is not allowed */
+ dev_set_uclass_priv(dev, clk);
clk->dev = dev;
clk->enable_count = 0;
#include <asm/arch-rockchip/cru_px30.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/io.h>
+#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dt-bindings/clock/px30-cru.h>
#include <linux/bitops.h>
glb_srst_fst);
priv->glb_srst_snd_value = offsetof(struct px30_cru,
glb_srst_snd);
- sys_child->priv = priv;
+ dev_set_priv(sys_child, priv);
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk3036.h>
#include <asm/arch-rockchip/hardware.h>
+#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3036-cru.h>
#include <linux/delay.h>
cru_glb_srst_fst_value);
priv->glb_srst_snd_value = offsetof(struct rk3036_cru,
cru_glb_srst_snd_value);
- sys_child->priv = priv;
+ dev_set_priv(sys_child, priv);
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
#include <asm/arch-rockchip/cru_rk3128.h>
#include <asm/arch-rockchip/hardware.h>
#include <bitfield.h>
+#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3128-cru.h>
#include <linux/delay.h>
cru_glb_srst_fst_value);
priv->glb_srst_snd_value = offsetof(struct rk3128_cru,
cru_glb_srst_snd_value);
- sys_child->priv = priv;
+ dev_set_priv(sys_child, priv);
}
return 0;
cru_glb_srst_fst_value);
priv->glb_srst_snd_value = offsetof(struct rk3188_cru,
cru_glb_srst_snd_value);
- sys_child->priv = priv;
+ dev_set_priv(sys_child, priv);
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk322x.h>
#include <asm/arch-rockchip/hardware.h>
+#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3228-cru.h>
#include <linux/bitops.h>
cru_glb_srst_fst_value);
priv->glb_srst_snd_value = offsetof(struct rk322x_cru,
cru_glb_srst_snd_value);
- sys_child->priv = priv;
+ dev_set_priv(sys_child, priv);
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
cru_glb_srst_fst_value);
priv->glb_srst_snd_value = offsetof(struct rockchip_cru,
cru_glb_srst_snd_value);
- sys_child->priv = priv;
+ dev_set_priv(sys_child, priv);
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
#include <asm/arch/cru_rk3308.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/hardware.h>
+#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3308-cru.h>
#include <linux/bitops.h>
glb_srst_fst);
priv->glb_srst_snd_value = offsetof(struct rk3308_cru,
glb_srst_snd);
- sys_child->priv = priv;
+ dev_set_priv(sys_child, priv);
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/grf_rk3328.h>
#include <asm/io.h>
+#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3328-cru.h>
#include <linux/bitops.h>
glb_srst_fst_value);
priv->glb_srst_snd_value = offsetof(struct rk3328_cru,
glb_srst_snd_value);
- sys_child->priv = priv;
+ dev_set_priv(sys_child, priv);
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
#include <asm/arch-rockchip/cru_rk3368.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/io.h>
+#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3368-cru.h>
#include <linux/delay.h>
glb_srst_fst_val);
priv->glb_srst_snd_value = offsetof(struct rk3368_cru,
glb_srst_snd_val);
- sys_child->priv = priv;
+ dev_set_priv(sys_child, priv);
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru.h>
#include <asm/arch-rockchip/hardware.h>
+#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3399-cru.h>
#include <linux/bitops.h>
glb_srst_fst_value);
priv->glb_srst_snd_value = offsetof(struct rockchip_cru,
glb_srst_snd_value);
- sys_child->priv = priv;
+ dev_set_priv(sys_child, priv);
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rv1108.h>
#include <asm/arch-rockchip/hardware.h>
+#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rv1108-cru.h>
#include <linux/delay.h>
glb_srst_fst_val);
priv->glb_srst_snd_value = offsetof(struct rv1108_cru,
glb_srst_snd_val);
- sys_child->priv = priv;
+ dev_set_priv(sys_child, priv);
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
return log_msg_ret("child unbind", ret);
if (dev->flags & DM_FLAG_ALLOC_PDATA) {
- free(dev->plat);
- dev->plat = NULL;
+ free(dev_get_plat(dev));
+ dev_set_plat(dev, NULL);
}
if (dev->flags & DM_FLAG_ALLOC_UCLASS_PDATA) {
- free(dev->uclass_plat);
+ free(dev_get_uclass_plat(dev));
dev->uclass_plat = NULL;
}
if (dev->flags & DM_FLAG_ALLOC_PARENT_PDATA) {
- free(dev->parent_plat);
+ free(dev_get_parent_plat(dev));
dev->parent_plat = NULL;
}
ret = uclass_unbind_device(dev);
int size;
if (dev->driver->priv_auto) {
- free(dev->priv);
- dev->priv = NULL;
+ free(dev_get_priv(dev));
+ dev_set_priv(dev, NULL);
}
size = dev->uclass->uc_drv->per_device_auto;
if (size) {
- free(dev->uclass_priv);
+ free(dev_get_uclass_priv(dev));
dev->uclass_priv = NULL;
}
if (dev->parent) {
per_child_auto;
}
if (size) {
- free(dev->parent_priv);
+ free(dev_get_parent_priv(dev));
dev->parent_priv = NULL;
}
}
int sdram_mmr_init_full(struct udevice *dev)
{
- struct altera_sdram_plat *plat = dev->plat;
+ struct altera_sdram_plat *plat = dev_get_plat(dev);
struct altera_sdram_priv *priv = dev_get_priv(dev);
u32 i;
int ret;
static int altera_gen5_sdram_of_to_plat(struct udevice *dev)
{
- struct altera_gen5_sdram_plat *plat = dev->plat;
+ struct altera_gen5_sdram_plat *plat = dev_get_plat(dev);
plat->sdr = (struct socfpga_sdr *)devfdt_get_addr_index(dev, 0);
if (!plat->sdr)
{
int ret;
unsigned long sdram_size;
- struct altera_gen5_sdram_plat *plat = dev->plat;
+ struct altera_gen5_sdram_plat *plat = dev_get_plat(dev);
struct altera_gen5_sdram_priv *priv = dev_get_priv(dev);
struct socfpga_sdr_ctrl *sdr_ctrl = &plat->sdr->sdr_ctrl;
struct reset_ctl_bulk resets;
*/
int sdram_mmr_init_full(struct udevice *dev)
{
- struct altera_sdram_plat *plat = dev->plat;
+ struct altera_sdram_plat *plat = dev_get_plat(dev);
struct altera_sdram_priv *priv = dev_get_priv(dev);
u32 update_value, io48_value, ddrioctl;
u32 i;
static int altera_sdram_of_to_plat(struct udevice *dev)
{
- struct altera_sdram_plat *plat = dev->plat;
+ struct altera_sdram_plat *plat = dev_get_plat(dev);
fdt_addr_t addr;
addr = dev_read_addr_index(dev, 0);
static int gpio_dwapb_probe(struct udevice *dev)
{
struct gpio_dev_priv *priv = dev_get_uclass_priv(dev);
- struct gpio_dwapb_plat *plat = dev->plat;
+ struct gpio_dwapb_plat *plat = dev_get_plat(dev);
if (!plat) {
/* Reset on parent device only */
if (!dev)
return -1;
- uc_priv = dev->uclass_priv;
+ uc_priv = dev_get_uclass_priv(dev);
return uc_priv->gpio_base + desc->offset;
}
{
struct gpio_bank *bank = dev_get_priv(dev);
struct hikey_gpio_plat *plat = dev_get_plat(dev);
- struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
char name[18], *str;
sprintf(name, "GPIO%d_", plat->bank_index);
#include <fdtdec.h>
#include <asm/gpio.h>
#include <asm/io.h>
+#include <dm/device-internal.h>
#include <malloc.h>
enum imx_rgpio2p_direction {
static int imx_rgpio2p_bind(struct udevice *dev)
{
- struct imx_rgpio2p_plat *plat = dev->plat;
+ struct imx_rgpio2p_plat *plat = dev_get_plat(dev);
fdt_addr_t addr;
/*
plat->regs = (struct gpio_regs *)addr;
plat->bank_index = dev_seq(dev);
- dev->plat = plat;
+ dev_set_plat(dev, plat);
return 0;
}
static int lpc32xx_gpio_probe(struct udevice *dev)
{
struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
- struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
if (dev_of_offset(dev) == -1) {
/* Tell the uclass how many GPIOs we have */
*/
static int gpio_mediatek_bind(struct udevice *parent)
{
- struct mediatek_gpio_plat *plat = parent->plat;
+ struct mediatek_gpio_plat *plat = dev_get_plat(parent);
ofnode node;
int bank = 0;
int ret;
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
static int mxs_of_to_plat(struct udevice *dev)
{
- struct mxs_gpio_plat *plat = dev->plat;
+ struct mxs_gpio_plat *plat = dev_get_plat(dev);
struct fdtdec_phandle_args args;
int node = dev_of_offset(dev);
int ret;
#include <fdtdec.h>
#include <asm/gpio.h>
#include <asm/io.h>
+#include <dm/device-internal.h>
#include <linux/errno.h>
#include <malloc.h>
plat->base = base_addr;
plat->port_name = fdt_get_name(gd->fdt_blob, dev_of_offset(dev), NULL);
- dev->plat = plat;
+ dev_set_plat(dev, plat);
return 0;
}
static int gpio_exynos_probe(struct udevice *dev)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
- struct exynos_bank_info *priv = dev->priv;
- struct exynos_gpio_plat *plat = dev->plat;
+ struct exynos_bank_info *priv = dev_get_priv(dev);
+ struct exynos_gpio_plat *plat = dev_get_plat(dev);
/* Only child devices have ports */
if (!plat)
*/
static int gpio_exynos_bind(struct udevice *parent)
{
- struct exynos_gpio_plat *plat = parent->plat;
+ struct exynos_gpio_plat *plat = dev_get_plat(parent);
struct s5p_gpio_bank *bank, *base;
const void *blob = gd->fdt_blob;
int node;
#include <acpi/acpi_device.h>
#include <asm/gpio.h>
#include <dm/acpi.h>
+#include <dm/device-internal.h>
#include <dm/device_compat.h>
#include <dm/lists.h>
#include <dm/of.h>
/* Tell the uclass how many GPIOs we have */
uc_priv->gpio_count = CONFIG_SANDBOX_GPIO_COUNT;
- dev->priv = calloc(sizeof(struct gpio_state), uc_priv->gpio_count);
+ dev_set_priv(dev,
+ calloc(sizeof(struct gpio_state), uc_priv->gpio_count));
return 0;
}
static int gpio_sandbox_remove(struct udevice *dev)
{
- free(dev->priv);
+ free(dev_get_priv(dev));
return 0;
}
{
struct sunxi_gpio_soc_data *soc_data =
(struct sunxi_gpio_soc_data *)dev_get_driver_data(parent);
- struct sunxi_gpio_plat *plat = parent->plat;
+ struct sunxi_gpio_plat *plat = dev_get_plat(parent);
struct sunxi_gpio_reg *ctlr;
int bank, ret;
static uint32_t *tegra186_gpio_reg(struct udevice *dev, uint32_t reg,
uint32_t gpio)
{
- struct tegra186_gpio_plat *plat = dev->plat;
+ struct tegra186_gpio_plat *plat = dev_get_plat(dev);
uint32_t index = (reg + (gpio * TEGRA186_GPIO_PER_GPIO_STRIDE)) / 4;
return &(plat->regs[index]);
*/
static int tegra186_gpio_bind(struct udevice *parent)
{
- struct tegra186_gpio_plat *parent_plat = parent->plat;
+ struct tegra186_gpio_plat *parent_plat = dev_get_plat(parent);
struct tegra186_gpio_ctlr_data *ctlr_data =
(struct tegra186_gpio_ctlr_data *)dev_get_driver_data(parent);
uint32_t *regs;
static int tegra186_gpio_probe(struct udevice *dev)
{
- struct tegra186_gpio_plat *plat = dev->plat;
+ struct tegra186_gpio_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
/* Only child devices have ports */
static int gpio_tegra_probe(struct udevice *dev)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
- struct tegra_port_info *priv = dev->priv;
- struct tegra_gpio_plat *plat = dev->plat;
+ struct tegra_port_info *priv = dev_get_priv(dev);
+ struct tegra_gpio_plat *plat = dev_get_plat(dev);
/* Only child devices have ports */
if (!plat)
*/
static int gpio_tegra_bind(struct udevice *parent)
{
- struct tegra_gpio_plat *plat = parent->plat;
+ struct tegra_gpio_plat *plat = dev_get_plat(parent);
struct gpio_ctlr *ctlr;
int bank_count;
int bank;
static int altera_sysid_read(struct udevice *dev,
int offset, void *buf, int size)
{
- struct altera_sysid_plat *plat = dev->plat;
+ struct altera_sysid_plat *plat = dev_get_plat(dev);
struct altera_sysid_regs *const regs = plat->regs;
u32 *sysid = buf;
int cros_ec_probe(struct udevice *dev)
{
- struct ec_state *ec = dev->priv;
- struct cros_ec_dev *cdev = dev->uclass_priv;
+ struct ec_state *ec = dev_get_priv(dev);
+ struct cros_ec_dev *cdev = dev_get_uclass_priv(dev);
struct udevice *keyb_dev;
ofnode node;
int err;
else
ret = -ENODEV;
} else {
- ret = select_fs_dev(dev->plat);
+ ret = select_fs_dev(dev_get_plat(dev));
}
if (ret)
if (ofnode_valid(fs_loader_node)) {
struct device_plat *plat;
- plat = dev->plat;
+ plat = dev_get_plat(dev);
if (!ofnode_read_u32_array(fs_loader_node,
"phandlepart",
phandlepart, 2)) {
{
#if CONFIG_IS_ENABLED(DM) && CONFIG_IS_ENABLED(BLK)
int ret;
- struct device_plat *plat = dev->plat;
+ struct device_plat *plat = dev_get_plat(dev);
if (plat->phandlepart.phandle) {
ofnode node = ofnode_get_by_phandle(plat->phandlepart.phandle);
if (!priv)
return -ENOMEM;
- dev->uclass_priv = priv;
+ dev_get_uclass_priv(dev) = priv;
priv->addr = ofnode_get_addr(args.node);
return dev_read_u32(dev, "arm,vexpress,site", &priv->site);
struct arm_pl180_mmc_plat *pdata = dev_get_plat(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct mmc *mmc = &pdata->mmc;
- struct pl180_mmc_host *host = dev->priv;
+ struct pl180_mmc_host *host = dev_get_priv(dev);
struct mmc_config *cfg = &pdata->cfg;
struct clk clk;
u32 bus_width;
static int dm_mmc_getcd(struct udevice *dev)
{
- struct pl180_mmc_host *host = dev->priv;
+ struct pl180_mmc_host *host = dev_get_priv(dev);
int value = 1;
if (dm_gpio_is_valid(&host->cd_gpio))
static int arm_pl180_mmc_of_to_plat(struct udevice *dev)
{
- struct pl180_mmc_host *host = dev->priv;
+ struct pl180_mmc_host *host = dev_get_priv(dev);
fdt_addr_t addr;
addr = dev_read_addr(dev);
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
static int mxsmmc_of_to_plat(struct udevice *bus)
{
- struct mxsmmc_plat *plat = bus->plat;
+ struct mxsmmc_plat *plat = dev_get_plat(bus);
u32 prop[2];
int ret;
#include <asm/arch/clock.h>
#include <asm/arch/csrs/csrs-mio_emm.h>
#include <asm/io.h>
+#include <dm/device-internal.h>
#include <power/regulator.h>
}
slot = &host->slots[bus_id];
- dev->priv = slot;
+ dev_set_priv(dev, slot);
slot->host = host;
slot->bus_id = bus_id;
slot->dev = dev;
snprintf(name, sizeof(name), "octeontx-mmc%d", bus_id);
err = device_set_name(dev, name);
- if (!dev->uclass_priv) {
+ /* FIXME: This code should not be needed */
+ if (!dev_get_uclass_priv(dev)) {
debug("%s(%s): Allocating uclass priv\n", __func__,
dev->name);
upriv = calloc(1, sizeof(struct mmc_uclass_priv));
if (!upriv)
return -ENOMEM;
- dev->uclass_priv = upriv;
- dev->uclass->priv = upriv;
+
+ /*
+ * FIXME: This is not allowed
+ * dev_set_uclass_priv(dev, upriv);
+ * uclass_set_priv(dev->uclass, upriv);
+ */
} else {
- upriv = dev->uclass_priv;
+ upriv = dev_get_uclass_priv(dev);
}
upriv->mmc = &slot->mmc;
U_BOOT_DRIVER(octeontx_hsmmc_host) = {
.name = "octeontx_hsmmc_host",
+ /* FIXME: Why is this not UCLASS_MMC? */
.id = UCLASS_MISC,
.of_match = of_match_ptr(octeontx_hsmmc_host_ids),
.probe = octeontx_mmc_host_probe,
#include <regmap.h>
#include <syscon.h>
#include <dm/device.h>
+#include <dm/device-internal.h>
#include <dm/device_compat.h>
#include <dm/read.h>
#include <dm/devres.h>
fields = devm_kmalloc(dev, num_fields * sizeof(*fields), __GFP_ZERO);
if (!fields)
return -ENOMEM;
- dev->priv = fields;
+ dev_set_priv(dev, fields);
mux_reg_masks = devm_kmalloc(dev, num_fields * 2 * sizeof(u32),
__GFP_ZERO);
for (uclass_first_device(UCLASS_ETH_PHY, &dev); dev;
uclass_next_device(&dev)) {
if (dev->parent == eth_dev) {
- uc_priv = (struct eth_phy_device_priv *)(dev->uclass_priv);
+ uc_priv = (struct eth_phy_device_priv *)(dev_get_uclass_priv(dev));
if (!uc_priv->mdio_bus)
uc_priv->mdio_bus = mdio_bus;
* phy_dev is shared and controlled by
* other eth controller
*/
- uc_priv = (struct eth_phy_device_priv *)(phy_dev->uclass_priv);
+ uc_priv = (struct eth_phy_device_priv *)(dev_get_uclass_priv(phy_dev));
if (uc_priv->mdio_bus)
printf("Get shared mii bus on %s\n", eth_dev->name);
else
struct fm_eth *fm_eth;
struct fsl_enet_mac *mac;
+#ifndef CONFIG_DM_ETH
fm_eth = (struct fm_eth *)dev->priv;
+#else
+ fm_eth = dev_get_priv(dev);
+#endif
mac = fm_eth->mac;
/* graceful stop the transmission of frames */
u16 offset_in;
int i;
+#ifndef CONFIG_DM_ETH
fm_eth = (struct fm_eth *)dev->priv;
+#else
+ fm_eth = dev_get_priv(dev);
+#endif
pram = fm_eth->tx_pram;
txbd = fm_eth->cur_txbd;
static int fm_eth_recv(struct udevice *dev, int flags, uchar **packetp)
#endif
{
- struct fm_eth *fm_eth = (struct fm_eth *)dev->priv;
- struct fm_port_bd *rxbd = fm_eth->cur_rxbd;
+ struct fm_eth *fm_eth;
+ struct fm_port_bd *rxbd;
u32 buf_lo, buf_hi;
u16 status, len;
int ret = -1;
u8 *data;
+#ifndef CONFIG_DM_ETH
+ fm_eth = (struct fm_eth *)dev->priv;
+#else
+ fm_eth = dev_get_priv(dev);
+#endif
+ rxbd = fm_eth->cur_rxbd;
status = muram_readw(&rxbd->status);
while (!(status & RxBD_EMPTY)) {
#ifdef CONFIG_DM_ETH
static int fm_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
{
- struct fm_eth *fm_eth = (struct fm_eth *)dev->priv;
+ struct fm_eth *fm_eth = (struct fm_eth *)dev_get_priv(dev);
fm_eth->cur_rxbd = fm_eth_free_one(fm_eth, fm_eth->cur_rxbd);
static int fm_eth_probe(struct udevice *dev)
{
- struct fm_eth *fm_eth = (struct fm_eth *)dev->priv;
+ struct fm_eth *fm_eth = (struct fm_eth *)dev_get_priv(dev);
struct ofnode_phandle_args args;
void *reg;
int ret, index;
static void fec_halt(struct udevice *dev)
{
- struct fec_info_dma *info = dev->priv;
+ struct fec_info_dma *info = dev_get_priv(dev);
volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
int counter = 0xffff;
static int fec_init(struct udevice *dev)
{
- struct fec_info_dma *info = dev->priv;
+ struct fec_info_dma *info = dev_get_priv(dev);
volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
int rval, i;
uchar enetaddr[6];
static int mcdmafec_send(struct udevice *dev, void *packet, int length)
{
- struct fec_info_dma *info = dev->priv;
+ struct fec_info_dma *info = dev_get_priv(dev);
cbd_t *p_tbd, *p_used_tbd;
u16 phy_status;
static int mcdmafec_recv(struct udevice *dev, int flags, uchar **packetp)
{
- struct fec_info_dma *info = dev->priv;
+ struct fec_info_dma *info = dev_get_priv(dev);
volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
cbd_t *prbd = &info->rxbd[info->rx_idx];
*/
static int mcdmafec_probe(struct udevice *dev)
{
- struct fec_info_dma *info = dev->priv;
+ struct fec_info_dma *info = dev_get_priv(dev);
struct eth_pdata *pdata = dev_get_plat(dev);
int node = dev_of_offset(dev);
int retval;
#ifdef ET_DEBUG
static void dbg_fec_regs(struct udevice *dev)
{
- struct fec_info_s *info = dev->priv;
+ struct fec_info_s *info = dev_get_priv(dev);
volatile fec_t *fecp = (fec_t *)(info->iobase);
printf("=====\n");
int mcffec_init(struct udevice *dev)
{
- struct fec_info_s *info = dev->priv;
+ struct fec_info_s *info = dev_get_priv(dev);
volatile fec_t *fecp = (fec_t *) (info->iobase);
int rval, i;
uchar ea[6];
static int mcffec_send(struct udevice *dev, void *packet, int length)
{
- struct fec_info_s *info = dev->priv;
+ struct fec_info_s *info = dev_get_priv(dev);
volatile fec_t *fecp = (fec_t *)info->iobase;
int j, rc;
u16 phy_status;
static int mcffec_recv(struct udevice *dev, int flags, uchar **packetp)
{
- struct fec_info_s *info = dev->priv;
+ struct fec_info_s *info = dev_get_priv(dev);
volatile fec_t *fecp = (fec_t *)info->iobase;
int length = -1;
static void mcffec_halt(struct udevice *dev)
{
- struct fec_info_s *info = dev->priv;
+ struct fec_info_s *info = dev_get_priv(dev);
fec_reset(info);
fecpin_setclear(info, 0);
static int mcffec_probe(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_plat(dev);
- struct fec_info_s *info = dev->priv;
+ struct fec_info_s *info = dev_get_priv(dev);
int node = dev_of_offset(dev);
int retval, fec_idx;
const u32 *val;
/* retrieve from register structure */
dev = eth_get_dev();
+#ifdef CONFIG_DM_ETH
+ info = dev_get_priv(dev);
+#else
info = dev->priv;
+#endif
ep = (FEC_T *) info->miibase;
/* retrieve from register structure */
dev = eth_get_dev();
+#ifdef CONFIG_DM_ETH
+ info = dev_get_priv(dev);
+#else
info = dev->priv;
+#endif
fecp = (FEC_T *) info->miibase;
static int pfe_eth_send(struct udevice *dev, void *packet, int length)
{
- struct pfe_eth_dev *priv = (struct pfe_eth_dev *)dev->priv;
+ struct pfe_eth_dev *priv = (struct pfe_eth_dev *)dev_get_priv(dev);
int rc;
int i = 0;
{
struct eth_pdata *pdata = dev_get_plat(dev);
- return _sunxi_emac_eth_init(dev->priv, pdata->enetaddr);
+ return _sunxi_emac_eth_init(dev_get_priv(dev), pdata->enetaddr);
}
static int sunxi_emac_eth_send(struct udevice *dev, void *packet, int length)
static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int join)
#endif
{
- struct tsec_private *priv = (struct tsec_private *)dev->priv;
- struct tsec __iomem *regs = priv->regs;
+ struct tsec_private *priv;
+ struct tsec __iomem *regs;
u32 result, value;
u8 whichbit, whichreg;
+#ifndef CONFIG_DM_ETH
+ priv = (struct tsec_private *)dev->priv;
+#else
+ priv = dev_get_priv(dev);
+#endif
+ regs = priv->regs;
result = ether_crc(MAC_ADDR_LEN, mcast_mac);
whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
whichreg = result >> 29; /* the 3 MSB = which reg to set it in */
static int tsec_send(struct udevice *dev, void *packet, int length)
#endif
{
- struct tsec_private *priv = (struct tsec_private *)dev->priv;
- struct tsec __iomem *regs = priv->regs;
+ struct tsec_private *priv;
+ struct tsec __iomem *regs;
int result = 0;
u16 status;
int i;
+#ifndef CONFIG_DM_ETH
+ priv = (struct tsec_private *)dev->priv;
+#else
+ priv = dev_get_priv(dev);
+#endif
+ regs = priv->regs;
/* Find an empty buffer descriptor */
for (i = 0;
in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
#else
static int tsec_recv(struct udevice *dev, int flags, uchar **packetp)
{
- struct tsec_private *priv = (struct tsec_private *)dev->priv;
+ struct tsec_private *priv = (struct tsec_private *)dev_get_priv(dev);
struct tsec __iomem *regs = priv->regs;
int ret = -1;
static int tsec_free_pkt(struct udevice *dev, uchar *packet, int length)
{
- struct tsec_private *priv = (struct tsec_private *)dev->priv;
+ struct tsec_private *priv = (struct tsec_private *)dev_get_priv(dev);
u16 status;
out_be16(&priv->rxbd[priv->rx_idx].length, 0);
static void tsec_halt(struct udevice *dev)
#endif
{
- struct tsec_private *priv = (struct tsec_private *)dev->priv;
- struct tsec __iomem *regs = priv->regs;
+ struct tsec_private *priv;
+ struct tsec __iomem *regs;
+#ifndef CONFIG_DM_ETH
+ priv = (struct tsec_private *)dev->priv;
+#else
+ priv = dev_get_priv(dev);
+#endif
+ regs = priv->regs;
clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
static int tsec_init(struct udevice *dev)
#endif
{
- struct tsec_private *priv = (struct tsec_private *)dev->priv;
+ struct tsec_private *priv;
+ struct tsec __iomem *regs;
#ifdef CONFIG_DM_ETH
struct eth_pdata *pdata = dev_get_plat(dev);
#else
struct eth_device *pdata = dev;
#endif
- struct tsec __iomem *regs = priv->regs;
u32 tempval;
int ret;
+#ifndef CONFIG_DM_ETH
+ priv = (struct tsec_private *)dev->priv;
+#else
+ priv = dev_get_priv(dev);
+#endif
+ regs = priv->regs;
/* Make sure the controller is stopped */
tsec_halt(dev);
int tsec_remove(struct udevice *dev)
{
- struct tsec_private *priv = dev->priv;
+ struct tsec_private *priv = dev_get_priv(dev);
free(priv->phydev);
mdio_unregister(priv->bus);
{
u32 length, first_read, reg, attempt = 0;
void *addr, *ack;
- struct xemaclite *emaclite = dev->priv;
+ struct xemaclite *emaclite = dev_get_priv(dev);
struct emaclite_regs *regs = emaclite->regs;
struct ethernet_hdr *eth;
struct ip_udp_hdr *ip;
static int sandbox_pci_emul_post_probe(struct udevice *dev)
{
- struct sandbox_pci_emul_priv *priv = dev->uclass->priv;
+ struct sandbox_pci_emul_priv *priv = uclass_get_priv(dev->uclass);
priv->dev_count++;
sandbox_set_enable_pci_map(true);
static int sandbox_pci_emul_pre_remove(struct udevice *dev)
{
- struct sandbox_pci_emul_priv *priv = dev->uclass->priv;
+ struct sandbox_pci_emul_priv *priv = uclass_get_priv(dev->uclass);
priv->dev_count--;
sandbox_set_enable_pci_map(priv->dev_count > 0);
int pci_auto_config_devices(struct udevice *bus)
{
- struct pci_controller *hose = bus->uclass_priv;
+ struct pci_controller *hose = dev_get_uclass_priv(bus);
struct pci_child_plat *pplat;
unsigned int sub_bus;
struct udevice *dev;
debug("%s, bus=%d/%s, parent=%s\n", __func__, dev_seq(bus), bus->name,
bus->parent->name);
- hose = bus->uclass_priv;
+ hose = dev_get_uclass_priv(bus);
/*
* Set the sequence number, if device_bind() doesn't. We want control
uint offset, ulong *valuep,
enum pci_size_t size)
{
- struct pci_controller *hose = bus->uclass_priv;
+ struct pci_controller *hose = dev_get_uclass_priv(bus);
return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
}
uint offset, ulong value,
enum pci_size_t size)
{
- struct pci_controller *hose = bus->uclass_priv;
+ struct pci_controller *hose = dev_get_uclass_priv(bus);
return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
}
#else
static int qe_io_of_to_plat(struct udevice *dev)
{
- struct qe_io_plat *plat = dev->plat;
+ struct qe_io_plat *plat = dev_get_plat(dev);
fdt_addr_t addr;
addr = dev_read_addr(dev);
*/
static int par_io_of_config_node(struct udevice *dev, ofnode pio)
{
- struct qe_io_plat *plat = dev->plat;
+ struct qe_io_plat *plat = dev_get_plat(dev);
qepio83xx_t *par_io = plat->base;
const unsigned int *pio_map;
int pio_map_len;
const struct single_fdt_pin_cfg *pins,
int size)
{
- struct single_pdata *pdata = dev->plat;
+ struct single_pdata *pdata = dev_get_plat(dev);
int count = size / sizeof(struct single_fdt_pin_cfg);
phys_addr_t n, reg;
u32 val;
const struct single_fdt_bits_cfg *pins,
int size)
{
- struct single_pdata *pdata = dev->plat;
+ struct single_pdata *pdata = dev_get_plat(dev);
int count = size / sizeof(struct single_fdt_bits_cfg);
phys_addr_t n, reg;
u32 val, mask;
fdt_addr_t addr;
u32 of_reg[2];
int res;
- struct single_pdata *pdata = dev->plat;
+ struct single_pdata *pdata = dev_get_plat(dev);
pdata->width =
dev_read_u32_default(dev, "pinctrl-single,register-width", 0);
static int da9063_get_enable(struct udevice *dev)
{
- const struct da9063_priv *priv = dev->priv;
+ const struct da9063_priv *priv = dev_get_priv(dev);
const struct da9063_reg_info *info = priv->reg_info;
int ret;
static int da9063_set_enable(struct udevice *dev, bool enable)
{
- const struct da9063_priv *priv = dev->priv;
+ const struct da9063_priv *priv = dev_get_priv(dev);
const struct da9063_reg_info *info = priv->reg_info;
return pmic_clrsetbits(dev->parent, info->en_reg,
static int da9063_get_voltage(struct udevice *dev)
{
- const struct da9063_priv *priv = dev->priv;
+ const struct da9063_priv *priv = dev_get_priv(dev);
const struct da9063_reg_info *info = priv->reg_info;
int ret;
static int da9063_set_voltage(struct udevice *dev, int uV)
{
- const struct da9063_priv *priv = dev->priv;
+ const struct da9063_priv *priv = dev_get_priv(dev);
const struct da9063_reg_info *info = priv->reg_info;
uint sel;
static int ldo_get_mode(struct udevice *dev)
{
- const struct da9063_priv *priv = dev->priv;
+ const struct da9063_priv *priv = dev_get_priv(dev);
const struct da9063_reg_info *info = priv->reg_info;
int val;
static int ldo_set_mode(struct udevice *dev, int mode_id)
{
- const struct da9063_priv *priv = dev->priv;
+ const struct da9063_priv *priv = dev_get_priv(dev);
const struct da9063_reg_info *info = priv->reg_info;
const struct dm_regulator_mode *mode;
static int buck_get_mode(struct udevice *dev)
{
- const struct da9063_priv *priv = dev->priv;
+ const struct da9063_priv *priv = dev_get_priv(dev);
const struct da9063_reg_info *info = priv->reg_info;
int i;
int val;
static int buck_set_mode(struct udevice *dev, int mode_id)
{
- const struct da9063_priv *priv = dev->priv;
+ const struct da9063_priv *priv = dev_get_priv(dev);
const struct da9063_reg_info *info = priv->reg_info;
const struct dm_regulator_mode *mode;
static int buck_get_current_limit(struct udevice *dev)
{
- const struct da9063_priv *priv = dev->priv;
+ const struct da9063_priv *priv = dev_get_priv(dev);
const struct da9063_reg_info *info = priv->reg_info;
int val;
static int buck_set_current_limit(struct udevice *dev, int uA)
{
- const struct da9063_priv *priv = dev->priv;
+ const struct da9063_priv *priv = dev_get_priv(dev);
const struct da9063_reg_info *info = priv->reg_info;
int val;
static int da9063_ldo_probe(struct udevice *dev)
{
struct dm_regulator_uclass_plat *uc_pdata;
- struct da9063_priv *priv = dev->priv;
+ struct da9063_priv *priv = dev_get_priv(dev);
/* LDOs are named numerically in DT so can directly index */
if (dev->driver_data < 1 ||
static int da9063_buck_probe(struct udevice *dev)
{
struct dm_regulator_uclass_plat *uc_pdata;
- struct da9063_priv *priv = dev->priv;
+ struct da9063_priv *priv = dev_get_priv(dev);
int i;
/* Bucks have names rather than numbers so need to match with DT */
#include <syscon.h>
#include <linux/bitops.h>
#include <linux/ioport.h>
+#include <dm/device-internal.h>
#include <dm/read.h>
#ifdef CONFIG_MMC_OMAP36XX_PINS
#include <asm/arch/sys_proto.h>
}
uc_pdata->type = REGULATOR_TYPE_OTHER;
- dev->priv = (void *)*p;
+ dev_set_priv(dev, (void *)*p);
return 0;
}
/* See if we need to populate via fdt */
- if (!dev->plat) {
+ if (!dev_get_plat(dev)) {
#if CONFIG_IS_ENABLED(OF_CONTROL)
int node = dev_of_offset(dev);
const void *blob = gd->fdt_blob;
#endif
} else {
- struct dm_rproc_uclass_pdata *pdata = dev->plat;
+ struct dm_rproc_uclass_pdata *pdata = dev_get_plat(dev);
debug("'%s': using legacy data\n", dev->name);
if (pdata->name)
#include <regmap.h>
#include <reset-uclass.h>
#include <syscon.h>
+#include <dm/device-internal.h>
#include <linux/bitops.h>
#include <linux/err.h>
priv = malloc(sizeof(struct mediatek_reset_priv));
priv->regofs = regofs;
priv->nr_resets = num_regs * 32;
- rst_dev->priv = priv;
+ dev_set_priv(rst_dev, priv);
return 0;
}
#include <linux/bitops.h>
#include <linux/io.h>
#include <asm/arch-rockchip/hardware.h>
+#include <dm/device-internal.h>
#include <dm/lists.h>
/*
* Each reg has 16 bits reset signal for devices
priv = malloc(sizeof(struct rockchip_reset_priv));
priv->reset_reg_offset = reg_offset;
priv->reset_reg_num = reg_number;
- rst_dev->priv = priv;
+ dev_set_priv(rst_dev, priv);
return 0;
}
#include <reset-uclass.h>
#include <asm/io.h>
#include <dm/device_compat.h>
+#include <dm/device-internal.h>
#include <dm/lists.h>
#include <linux/bitops.h>
}
priv = malloc(sizeof(struct sifive_reset_priv));
priv->nr_reset = count;
- rst_dev->priv = priv;
+ dev_set_priv(rst_dev, priv);
return 0;
}
#include <malloc.h>
#include <reset-uclass.h>
#include <asm/io.h>
+#include <dm/device-internal.h>
#include <dm/lists.h>
#include <linux/bitops.h>
#include <linux/log2.h>
priv = malloc(sizeof(struct sunxi_reset_priv));
priv->count = count;
priv->desc = (const struct ccu_desc *)dev_get_driver_data(dev);
- rst_dev->priv = priv;
+ dev_set_priv(rst_dev, priv);
return 0;
}
static int altera_jtaguart_putc(struct udevice *dev, const char ch)
{
- struct altera_jtaguart_plat *plat = dev->plat;
+ struct altera_jtaguart_plat *plat = dev_get_plat(dev);
struct altera_jtaguart_regs *const regs = plat->regs;
u32 st = readl(®s->control);
static int altera_jtaguart_pending(struct udevice *dev, bool input)
{
- struct altera_jtaguart_plat *plat = dev->plat;
+ struct altera_jtaguart_plat *plat = dev_get_plat(dev);
struct altera_jtaguart_regs *const regs = plat->regs;
u32 st = readl(®s->control);
static int altera_jtaguart_getc(struct udevice *dev)
{
- struct altera_jtaguart_plat *plat = dev->plat;
+ struct altera_jtaguart_plat *plat = dev_get_plat(dev);
struct altera_jtaguart_regs *const regs = plat->regs;
u32 val;
static int altera_jtaguart_probe(struct udevice *dev)
{
#ifdef CONFIG_ALTERA_JTAG_UART_BYPASS
- struct altera_jtaguart_plat *plat = dev->plat;
+ struct altera_jtaguart_plat *plat = dev_get_plat(dev);
struct altera_jtaguart_regs *const regs = plat->regs;
writel(ALTERA_JTAG_AC, ®s->control); /* clear AC flag */
static int altera_uart_setbrg(struct udevice *dev, int baudrate)
{
- struct altera_uart_plat *plat = dev->plat;
+ struct altera_uart_plat *plat = dev_get_plat(dev);
struct altera_uart_regs *const regs = plat->regs;
u32 div;
static int altera_uart_putc(struct udevice *dev, const char ch)
{
- struct altera_uart_plat *plat = dev->plat;
+ struct altera_uart_plat *plat = dev_get_plat(dev);
struct altera_uart_regs *const regs = plat->regs;
if (!(readl(®s->status) & ALTERA_UART_TRDY))
static int altera_uart_pending(struct udevice *dev, bool input)
{
- struct altera_uart_plat *plat = dev->plat;
+ struct altera_uart_plat *plat = dev_get_plat(dev);
struct altera_uart_regs *const regs = plat->regs;
u32 st = readl(®s->status);
static int altera_uart_getc(struct udevice *dev)
{
- struct altera_uart_plat *plat = dev->plat;
+ struct altera_uart_plat *plat = dev_get_plat(dev);
struct altera_uart_regs *const regs = plat->regs;
if (!(readl(®s->status) & ALTERA_UART_RRDY))
static int atmel_serial_probe(struct udevice *dev)
{
- struct atmel_serial_plat *plat = dev->plat;
+ struct atmel_serial_plat *plat = dev_get_plat(dev);
struct atmel_serial_priv *priv = dev_get_priv(dev);
int ret;
#if CONFIG_IS_ENABLED(OF_CONTROL)
int ns16550_serial_probe(struct udevice *dev)
{
- struct ns16550_plat *plat = dev->plat;
+ struct ns16550_plat *plat = dev_get_plat(dev);
struct ns16550 *const com_port = dev_get_priv(dev);
struct reset_ctl_bulk reset_bulk;
fdt_addr_t addr;
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
int ns16550_serial_of_to_plat(struct udevice *dev)
{
- struct ns16550_plat *plat = dev->plat;
+ struct ns16550_plat *plat = dev_get_plat(dev);
const u32 port_type = dev_get_driver_data(dev);
fdt_addr_t addr;
struct clk clk;
static int sandbox_serial_remove(struct udevice *dev)
{
- struct sandbox_serial_plat *plat = dev->plat;
+ struct sandbox_serial_plat *plat = dev_get_plat(dev);
if (plat->colour != -1)
output_ansi_reset();
static int sandbox_serial_putc(struct udevice *dev, const char ch)
{
struct sandbox_serial_priv *priv = dev_get_priv(dev);
- struct sandbox_serial_plat *plat = dev->plat;
+ struct sandbox_serial_plat *plat = dev_get_plat(dev);
/* With of-platdata we don't real the colour correctly, so disable it */
if (!CONFIG_IS_ENABLED(OF_PLATDATA) && priv->start_of_line &&
static int sandbox_serial_of_to_plat(struct udevice *dev)
{
- struct sandbox_serial_plat *plat = dev->plat;
+ struct sandbox_serial_plat *plat = dev_get_plat(dev);
const char *colour;
int i;
static int arc_serial_setbrg(struct udevice *dev, int baudrate)
{
- struct arc_serial_plat *plat = dev->plat;
+ struct arc_serial_plat *plat = dev_get_plat(dev);
struct arc_serial_regs *const regs = plat->reg;
int arc_console_baud = gd->cpu_clk / (baudrate * 4) - 1;
static int arc_serial_putc(struct udevice *dev, const char c)
{
- struct arc_serial_plat *plat = dev->plat;
+ struct arc_serial_plat *plat = dev_get_plat(dev);
struct arc_serial_regs *const regs = plat->reg;
while (!(readb(®s->status) & UART_TXEMPTY))
static int arc_serial_pending(struct udevice *dev, bool input)
{
- struct arc_serial_plat *plat = dev->plat;
+ struct arc_serial_plat *plat = dev_get_plat(dev);
struct arc_serial_regs *const regs = plat->reg;
uint32_t status = readb(®s->status);
static int arc_serial_getc(struct udevice *dev)
{
- struct arc_serial_plat *plat = dev->plat;
+ struct arc_serial_plat *plat = dev_get_plat(dev);
struct arc_serial_regs *const regs = plat->reg;
while (!arc_serial_tstc(regs))
static int linflex_serial_probe(struct udevice *dev)
{
- struct linflex_serial_plat *plat = dev->plat;
+ struct linflex_serial_plat *plat = dev_get_plat(dev);
struct linflex_serial_priv *priv = dev_get_priv(dev);
priv->lfuart = (struct linflex_fsl *)plat->base_addr;
static bool is_lpuart32(struct udevice *dev)
{
- struct lpuart_serial_plat *plat = dev->plat;
+ struct lpuart_serial_plat *plat = dev_get_plat(dev);
return plat->flags & LPUART_FLAG_REGMAP_32BIT_REG;
}
static int lpuart_serial_getc(struct udevice *dev)
{
- struct lpuart_serial_plat *plat = dev->plat;
+ struct lpuart_serial_plat *plat = dev_get_plat(dev);
if (is_lpuart32(dev))
return _lpuart32_serial_getc(plat);
static int lpuart_serial_putc(struct udevice *dev, const char c)
{
- struct lpuart_serial_plat *plat = dev->plat;
+ struct lpuart_serial_plat *plat = dev_get_plat(dev);
if (is_lpuart32(dev))
_lpuart32_serial_putc(plat, c);
static int lpuart_serial_pending(struct udevice *dev, bool input)
{
- struct lpuart_serial_plat *plat = dev->plat;
+ struct lpuart_serial_plat *plat = dev_get_plat(dev);
struct lpuart_fsl *reg = plat->reg;
struct lpuart_fsl_reg32 *reg32 = plat->reg;
u32 stat;
static int lpuart_serial_of_to_plat(struct udevice *dev)
{
- struct lpuart_serial_plat *plat = dev->plat;
+ struct lpuart_serial_plat *plat = dev_get_plat(dev);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
fdt_addr_t addr;
static int coldfire_serial_probe(struct udevice *dev)
{
- struct coldfire_serial_plat *plat = dev->plat;
+ struct coldfire_serial_plat *plat = dev_get_plat(dev);
plat->port = dev_seq(dev);
static int coldfire_serial_putc(struct udevice *dev, const char ch)
{
- struct coldfire_serial_plat *plat = dev->plat;
+ struct coldfire_serial_plat *plat = dev_get_plat(dev);
uart_t *uart = (uart_t *)plat->base;
/* Wait for last character to go. */
static int coldfire_serial_getc(struct udevice *dev)
{
- struct coldfire_serial_plat *plat = dev->plat;
+ struct coldfire_serial_plat *plat = dev_get_plat(dev);
uart_t *uart = (uart_t *)(plat->base);
/* Wait for a character to arrive. */
int coldfire_serial_setbrg(struct udevice *dev, int baudrate)
{
- struct coldfire_serial_plat *plat = dev->plat;
+ struct coldfire_serial_plat *plat = dev_get_plat(dev);
uart_t *uart = (uart_t *)(plat->base);
mcf_serial_setbrg_common(uart, baudrate);
static int coldfire_serial_pending(struct udevice *dev, bool input)
{
- struct coldfire_serial_plat *plat = dev->plat;
+ struct coldfire_serial_plat *plat = dev_get_plat(dev);
uart_t *uart = (uart_t *)(plat->base);
if (input)
static int meson_serial_probe(struct udevice *dev)
{
- struct meson_serial_plat *plat = dev->plat;
+ struct meson_serial_plat *plat = dev_get_plat(dev);
struct meson_uart *const uart = plat->reg;
meson_serial_init(uart);
static void meson_serial_rx_error(struct udevice *dev)
{
- struct meson_serial_plat *plat = dev->plat;
+ struct meson_serial_plat *plat = dev_get_plat(dev);
struct meson_uart *const uart = plat->reg;
u32 val = readl(&uart->control);
static int meson_serial_getc(struct udevice *dev)
{
- struct meson_serial_plat *plat = dev->plat;
+ struct meson_serial_plat *plat = dev_get_plat(dev);
struct meson_uart *const uart = plat->reg;
uint32_t status = readl(&uart->status);
static int meson_serial_putc(struct udevice *dev, const char ch)
{
- struct meson_serial_plat *plat = dev->plat;
+ struct meson_serial_plat *plat = dev_get_plat(dev);
struct meson_uart *const uart = plat->reg;
if (readl(&uart->status) & AML_UART_TX_FULL)
static int meson_serial_pending(struct udevice *dev, bool input)
{
- struct meson_serial_plat *plat = dev->plat;
+ struct meson_serial_plat *plat = dev_get_plat(dev);
struct meson_uart *const uart = plat->reg;
uint32_t status = readl(&uart->status);
static int meson_serial_of_to_plat(struct udevice *dev)
{
- struct meson_serial_plat *plat = dev->plat;
+ struct meson_serial_plat *plat = dev_get_plat(dev);
fdt_addr_t addr;
addr = dev_read_addr(dev);
int mxc_serial_setbrg(struct udevice *dev, int baudrate)
{
- struct mxc_serial_plat *plat = dev->plat;
+ struct mxc_serial_plat *plat = dev_get_plat(dev);
u32 clk = imx_get_uartclk();
_mxc_serial_setbrg(plat->reg, clk, baudrate, plat->use_dte);
static int mxc_serial_probe(struct udevice *dev)
{
- struct mxc_serial_plat *plat = dev->plat;
+ struct mxc_serial_plat *plat = dev_get_plat(dev);
_mxc_serial_init(plat->reg, plat->use_dte);
static int mxc_serial_getc(struct udevice *dev)
{
- struct mxc_serial_plat *plat = dev->plat;
+ struct mxc_serial_plat *plat = dev_get_plat(dev);
struct mxc_uart *const uart = plat->reg;
if (readl(&uart->ts) & UTS_RXEMPTY)
static int mxc_serial_putc(struct udevice *dev, const char ch)
{
- struct mxc_serial_plat *plat = dev->plat;
+ struct mxc_serial_plat *plat = dev_get_plat(dev);
struct mxc_uart *const uart = plat->reg;
if (!(readl(&uart->ts) & UTS_TXEMPTY))
static int mxc_serial_pending(struct udevice *dev, bool input)
{
- struct mxc_serial_plat *plat = dev->plat;
+ struct mxc_serial_plat *plat = dev_get_plat(dev);
struct mxc_uart *const uart = plat->reg;
uint32_t sr2 = readl(&uart->sr2);
#if CONFIG_IS_ENABLED(OF_CONTROL)
static int mxc_serial_of_to_plat(struct udevice *dev)
{
- struct mxc_serial_plat *plat = dev->plat;
+ struct mxc_serial_plat *plat = dev_get_plat(dev);
fdt_addr_t addr;
addr = dev_read_addr(dev);
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
static int omap_serial_of_to_plat(struct udevice *dev)
{
- struct ns16550_plat *plat = dev->plat;
+ struct ns16550_plat *plat = dev_get_plat(dev);
fdt_addr_t addr;
struct clk clk;
int err;
#ifdef CONFIG_DM_SERIAL
static int pxa_serial_probe(struct udevice *dev)
{
- struct pxa_serial_plat *plat = dev->plat;
+ struct pxa_serial_plat *plat = dev_get_plat(dev);
pxa_setbrg_common((struct pxa_uart_regs *)plat->base, plat->port,
plat->baudrate);
static int pxa_serial_putc(struct udevice *dev, const char ch)
{
- struct pxa_serial_plat *plat = dev->plat;
+ struct pxa_serial_plat *plat = dev_get_plat(dev);
struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base;
/* Wait for last character to go. */
static int pxa_serial_getc(struct udevice *dev)
{
- struct pxa_serial_plat *plat = dev->plat;
+ struct pxa_serial_plat *plat = dev_get_plat(dev);
struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base;
/* Wait for a character to arrive. */
int pxa_serial_setbrg(struct udevice *dev, int baudrate)
{
- struct pxa_serial_plat *plat = dev->plat;
+ struct pxa_serial_plat *plat = dev_get_plat(dev);
struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base;
int port = plat->port;
static int pxa_serial_pending(struct udevice *dev, bool input)
{
- struct pxa_serial_plat *plat = dev->plat;
+ struct pxa_serial_plat *plat = dev_get_plat(dev);
struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base;
if (input)
#include <ns16550.h>
#include <serial.h>
#include <asm/arch-rockchip/clock.h>
+#include <dm/device-internal.h>
#if defined(CONFIG_ROCKCHIP_RK3188)
struct rockchip_uart_plat {
plat->plat.reg_shift = plat->dtplat.reg_shift;
plat->plat.clock = plat->dtplat.clock_frequency;
plat->plat.fcr = UART_FCR_DEFVAL;
- dev->plat = &plat->plat;
+ dev_set_plat(dev, &plat->plat);
return ns16550_serial_probe(dev);
}
#ifndef CONFIG_SPL_BUILD
int s5p_serial_setbrg(struct udevice *dev, int baudrate)
{
- struct s5p_serial_plat *plat = dev->plat;
+ struct s5p_serial_plat *plat = dev_get_plat(dev);
struct s5p_uart *const uart = plat->reg;
u32 uclk;
static int s5p_serial_probe(struct udevice *dev)
{
- struct s5p_serial_plat *plat = dev->plat;
+ struct s5p_serial_plat *plat = dev_get_plat(dev);
struct s5p_uart *const uart = plat->reg;
s5p_serial_init(uart);
static int s5p_serial_getc(struct udevice *dev)
{
- struct s5p_serial_plat *plat = dev->plat;
+ struct s5p_serial_plat *plat = dev_get_plat(dev);
struct s5p_uart *const uart = plat->reg;
if (!(readl(&uart->ufstat) & RX_FIFO_COUNT_MASK))
static int s5p_serial_putc(struct udevice *dev, const char ch)
{
- struct s5p_serial_plat *plat = dev->plat;
+ struct s5p_serial_plat *plat = dev_get_plat(dev);
struct s5p_uart *const uart = plat->reg;
if (readl(&uart->ufstat) & TX_FIFO_FULL)
static int s5p_serial_pending(struct udevice *dev, bool input)
{
- struct s5p_serial_plat *plat = dev->plat;
+ struct s5p_serial_plat *plat = dev_get_plat(dev);
struct s5p_uart *const uart = plat->reg;
uint32_t ufstat = readl(&uart->ufstat);
static int s5p_serial_of_to_plat(struct udevice *dev)
{
- struct s5p_serial_plat *plat = dev->plat;
+ struct s5p_serial_plat *plat = dev_get_plat(dev);
fdt_addr_t addr;
addr = dev_read_addr(dev);
static int cadence_spi_write_speed(struct udevice *bus, uint hz)
{
- struct cadence_spi_plat *plat = bus->plat;
+ struct cadence_spi_plat *plat = dev_get_plat(bus);
struct cadence_spi_priv *priv = dev_get_priv(bus);
cadence_qspi_apb_config_baudrate_div(priv->regbase,
static int cadence_spi_set_speed(struct udevice *bus, uint hz)
{
- struct cadence_spi_plat *plat = bus->plat;
+ struct cadence_spi_plat *plat = dev_get_plat(bus);
struct cadence_spi_priv *priv = dev_get_priv(bus);
int err;
static int cadence_spi_probe(struct udevice *bus)
{
- struct cadence_spi_plat *plat = bus->plat;
+ struct cadence_spi_plat *plat = dev_get_plat(bus);
struct cadence_spi_priv *priv = dev_get_priv(bus);
struct clk clk;
int ret;
static int cadence_spi_set_mode(struct udevice *bus, uint mode)
{
- struct cadence_spi_plat *plat = bus->plat;
+ struct cadence_spi_plat *plat = dev_get_plat(bus);
struct cadence_spi_priv *priv = dev_get_priv(bus);
/* Disable QSPI */
const struct spi_mem_op *op)
{
struct udevice *bus = spi->dev->parent;
- struct cadence_spi_plat *plat = bus->plat;
+ struct cadence_spi_plat *plat = dev_get_plat(bus);
struct cadence_spi_priv *priv = dev_get_priv(bus);
void *base = priv->regbase;
int err = 0;
static int cadence_spi_of_to_plat(struct udevice *bus)
{
- struct cadence_spi_plat *plat = bus->plat;
+ struct cadence_spi_plat *plat = dev_get_plat(bus);
ofnode subnode;
plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
static int coldfire_dspi_of_to_plat(struct udevice *bus)
{
fdt_addr_t addr;
- struct coldfire_spi_plat *plat = bus->plat;
+ struct coldfire_spi_plat *plat = dev_get_plat(bus);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
int *ctar, len;
static int davinci_spi_probe(struct udevice *bus)
{
struct davinci_spi_slave *ds = dev_get_priv(bus);
- struct davinci_spi_plat *plat = bus->plat;
+ struct davinci_spi_plat *plat = dev_get_plat(bus);
ds->regs = plat->regs;
ds->num_cs = plat->num_cs;
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
static int davinci_ofdata_to_platadata(struct udevice *bus)
{
- struct davinci_spi_plat *plat = bus->plat;
+ struct davinci_spi_plat *plat = dev_get_plat(bus);
fdt_addr_t addr;
addr = dev_read_addr(bus);
static int dw_spi_of_to_plat(struct udevice *bus)
{
- struct dw_spi_plat *plat = bus->plat;
+ struct dw_spi_plat *plat = dev_get_plat(bus);
plat->regs = dev_read_addr_ptr(bus);
static int dw_spi_set_speed(struct udevice *bus, uint speed)
{
- struct dw_spi_plat *plat = bus->plat;
+ struct dw_spi_plat *plat = dev_get_plat(bus);
struct dw_spi_priv *priv = dev_get_priv(bus);
u16 clk_div;
static int exynos_spi_of_to_plat(struct udevice *bus)
{
- struct exynos_spi_plat *plat = bus->plat;
+ struct exynos_spi_plat *plat = dev_get_plat(bus);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
static int exynos_spi_set_speed(struct udevice *bus, uint speed)
{
- struct exynos_spi_plat *plat = bus->plat;
+ struct exynos_spi_plat *plat = dev_get_plat(bus);
struct exynos_spi_priv *priv = dev_get_priv(bus);
int ret;
struct dm_spi_bus *dm_spi_bus;
uint mcr_cfg_val;
- dm_spi_bus = bus->uclass_priv;
+ dm_spi_bus = dev_get_uclass_priv(bus);
/* cpu speical pin muxing configure */
cpu_dspi_port_conf();
static int fsl_dspi_of_to_plat(struct udevice *bus)
{
fdt_addr_t addr;
- struct fsl_dspi_plat *plat = bus->plat;
+ struct fsl_dspi_plat *plat = dev_get_plat(bus);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
static int fsl_espi_of_to_plat(struct udevice *bus)
{
fdt_addr_t addr;
- struct fsl_espi_plat *plat = bus->plat;
+ struct fsl_espi_plat *plat = dev_get_plat(bus);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
static int fsl_qspi_probe(struct udevice *bus)
{
- struct dm_spi_bus *dm_bus = bus->uclass_priv;
+ struct dm_spi_bus *dm_bus = dev_get_uclass_priv(bus);
struct fsl_qspi *q = dev_get_priv(bus);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
static int mxs_of_to_plat(struct udevice *bus)
{
- struct mxs_spi_plat *plat = bus->plat;
+ struct mxs_spi_plat *plat = dev_get_plat(bus);
u32 prop[2];
int ret;
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
static int pl022_spi_of_to_plat(struct udevice *bus)
{
- struct pl022_spi_pdata *plat = bus->plat;
+ struct pl022_spi_pdata *plat = dev_get_plat(bus);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(bus);
struct clk clkdev;
static void spi_cs_activate(struct udevice *dev, uint cs)
{
struct udevice *bus = dev->parent;
- struct rockchip_spi_plat *plat = bus->plat;
+ struct rockchip_spi_plat *plat = dev_get_plat(bus);
struct rockchip_spi_priv *priv = dev_get_priv(bus);
struct rockchip_spi *regs = priv->regs;
static void spi_cs_deactivate(struct udevice *dev, uint cs)
{
struct udevice *bus = dev->parent;
- struct rockchip_spi_plat *plat = bus->plat;
+ struct rockchip_spi_plat *plat = dev_get_plat(bus);
struct rockchip_spi_priv *priv = dev_get_priv(bus);
struct rockchip_spi *regs = priv->regs;
#if CONFIG_IS_ENABLED(OF_PLATDATA)
static int conv_of_plat(struct udevice *dev)
{
- struct rockchip_spi_plat *plat = dev->plat;
+ struct rockchip_spi_plat *plat = dev_get_plat(dev);
struct dtd_rockchip_rk3288_spi *dtplat = &plat->of_plat;
struct rockchip_spi_priv *priv = dev_get_priv(dev);
int ret;
static int soft_spi_of_to_plat(struct udevice *dev)
{
- struct soft_spi_plat *plat = dev->plat;
+ struct soft_spi_plat *plat = dev_get_plat(dev);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
static int soft_spi_probe(struct udevice *dev)
{
struct spi_slave *slave = dev_get_parent_priv(dev);
- struct soft_spi_plat *plat = dev->plat;
+ struct soft_spi_plat *plat = dev_get_plat(dev);
int cs_flags, clk_flags;
int ret;
static int tegra114_spi_of_to_plat(struct udevice *bus)
{
- struct tegra_spi_plat *plat = bus->plat;
+ struct tegra_spi_plat *plat = dev_get_plat(bus);
plat->base = dev_read_addr(bus);
plat->periph_id = clock_decode_periph_id(bus);
static int tegra114_spi_set_speed(struct udevice *bus, uint speed)
{
- struct tegra_spi_plat *plat = bus->plat;
+ struct tegra_spi_plat *plat = dev_get_plat(bus);
struct tegra114_spi_priv *priv = dev_get_priv(bus);
if (speed > plat->frequency)
static int tegra20_sflash_of_to_plat(struct udevice *bus)
{
- struct tegra_spi_plat *plat = bus->plat;
+ struct tegra_spi_plat *plat = dev_get_plat(bus);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
static int tegra20_sflash_set_speed(struct udevice *bus, uint speed)
{
- struct tegra_spi_plat *plat = bus->plat;
+ struct tegra_spi_plat *plat = dev_get_plat(bus);
struct tegra20_sflash_priv *priv = dev_get_priv(bus);
if (speed > plat->frequency)
static int tegra30_spi_of_to_plat(struct udevice *bus)
{
- struct tegra_spi_plat *plat = bus->plat;
+ struct tegra_spi_plat *plat = dev_get_plat(bus);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
static int tegra30_spi_set_speed(struct udevice *bus, uint speed)
{
- struct tegra_spi_plat *plat = bus->plat;
+ struct tegra_spi_plat *plat = dev_get_plat(bus);
struct tegra30_spi_priv *priv = dev_get_priv(bus);
if (speed > plat->frequency)
static int tegra210_qspi_of_to_plat(struct udevice *bus)
{
- struct tegra_spi_plat *plat = bus->plat;
+ struct tegra_spi_plat *plat = dev_get_plat(bus);
plat->base = dev_read_addr(bus);
plat->periph_id = clock_decode_periph_id(bus);
static int tegra210_qspi_set_speed(struct udevice *bus, uint speed)
{
- struct tegra_spi_plat *plat = bus->plat;
+ struct tegra_spi_plat *plat = dev_get_plat(bus);
struct tegra210_qspi_priv *priv = dev_get_priv(bus);
if (speed > plat->frequency)
static void spi_cs_activate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct uniphier_spi_plat *plat = bus->plat;
+ struct uniphier_spi_plat *plat = dev_get_plat(bus);
struct uniphier_spi_priv *priv = dev_get_priv(bus);
ulong delay_us; /* The delay completed so far */
u32 val;
static void spi_cs_deactivate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct uniphier_spi_plat *plat = bus->plat;
+ struct uniphier_spi_plat *plat = dev_get_plat(bus);
struct uniphier_spi_priv *priv = dev_get_priv(bus);
u32 val;
static int uniphier_spi_set_speed(struct udevice *bus, uint speed)
{
- struct uniphier_spi_plat *plat = bus->plat;
+ struct uniphier_spi_plat *plat = dev_get_plat(bus);
struct uniphier_spi_priv *priv = dev_get_priv(bus);
u32 val, ckdiv;
static int uniphier_spi_of_to_plat(struct udevice *bus)
{
- struct uniphier_spi_plat *plat = bus->plat;
+ struct uniphier_spi_plat *plat = dev_get_plat(bus);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
static int zynq_qspi_of_to_plat(struct udevice *bus)
{
- struct zynq_qspi_plat *plat = bus->plat;
+ struct zynq_qspi_plat *plat = dev_get_plat(bus);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
static int zynq_qspi_set_speed(struct udevice *bus, uint speed)
{
- struct zynq_qspi_plat *plat = bus->plat;
+ struct zynq_qspi_plat *plat = dev_get_plat(bus);
struct zynq_qspi_priv *priv = dev_get_priv(bus);
struct zynq_qspi_regs *regs = priv->regs;
uint32_t confr;
static int zynq_spi_of_to_plat(struct udevice *bus)
{
- struct zynq_spi_plat *plat = bus->plat;
+ struct zynq_spi_plat *plat = dev_get_plat(bus);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
static void spi_cs_activate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct zynq_spi_plat *plat = bus->plat;
+ struct zynq_spi_plat *plat = dev_get_plat(bus);
struct zynq_spi_priv *priv = dev_get_priv(bus);
struct zynq_spi_regs *regs = priv->regs;
u32 cr;
static void spi_cs_deactivate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct zynq_spi_plat *plat = bus->plat;
+ struct zynq_spi_plat *plat = dev_get_plat(bus);
struct zynq_spi_priv *priv = dev_get_priv(bus);
struct zynq_spi_regs *regs = priv->regs;
static int zynq_spi_set_speed(struct udevice *bus, uint speed)
{
- struct zynq_spi_plat *plat = bus->plat;
+ struct zynq_spi_plat *plat = dev_get_plat(bus);
struct zynq_spi_priv *priv = dev_get_priv(bus);
struct zynq_spi_regs *regs = priv->regs;
uint32_t confr;
static int zynqmp_qspi_of_to_plat(struct udevice *bus)
{
- struct zynqmp_qspi_plat *plat = bus->plat;
+ struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
debug("%s\n", __func__);
void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval)
{
- struct zynqmp_qspi_plat *plat = bus->plat;
+ struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
struct zynqmp_qspi_regs *regs = priv->regs;
u32 tapdlybypass = 0, lpbkdlyadj = 0, datadlyadj = 0, clk_rate;
static int zynqmp_qspi_set_speed(struct udevice *bus, uint speed)
{
- struct zynqmp_qspi_plat *plat = bus->plat;
+ struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
struct zynqmp_qspi_regs *regs = priv->regs;
u32 confr;
static u64 atftmr_timer_get_count(struct udevice *dev)
{
- struct atftmr_timer_plat *plat = dev->plat;
+ struct atftmr_timer_plat *plat = dev_get_plat(dev);
struct atftmr_timer_regs *const regs = plat->regs;
u32 val;
val = readl(®s->t3_counter);
static int atftmr_timer_probe(struct udevice *dev)
{
- struct atftmr_timer_plat *plat = dev->plat;
+ struct atftmr_timer_plat *plat = dev_get_plat(dev);
struct atftmr_timer_regs *const regs = plat->regs;
u32 cr;
writel(0, ®s->t3_load);
static u64 altera_timer_get_count(struct udevice *dev)
{
- struct altera_timer_plat *plat = dev->plat;
+ struct altera_timer_plat *plat = dev_get_plat(dev);
struct altera_timer_regs *const regs = plat->regs;
u32 val;
static int altera_timer_probe(struct udevice *dev)
{
- struct altera_timer_plat *plat = dev->plat;
+ struct altera_timer_plat *plat = dev_get_plat(dev);
struct altera_timer_regs *const regs = plat->regs;
writel(0, ®s->status);
#include <dm.h>
#include <timer.h>
#include <asm/io.h>
+#include <dm/device-internal.h>
#include <linux/err.h>
/* mtime register */
static u64 andes_plmt_get_count(struct udevice *dev)
{
- return readq((void __iomem *)MTIME_REG(dev->priv));
+ return readq((void __iomem *)MTIME_REG(dev_get_priv(dev)));
}
static const struct timer_ops andes_plmt_ops = {
static int andes_plmt_probe(struct udevice *dev)
{
- dev->priv = dev_read_addr_ptr(dev);
- if (!dev->priv)
+ dev_set_priv(dev, dev_read_addr_ptr(dev));
+ if (!dev_get_priv(dev))
return -EINVAL;
return timer_timebase_fallback(dev);
static int mpc83xx_timer_probe(struct udevice *dev)
{
- struct timer_dev_priv *uc_priv = dev->uclass_priv;
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct clk clock;
int ret;
#include <dm.h>
#include <timer.h>
#include <asm/io.h>
+#include <dm/device-internal.h>
#include <linux/err.h>
/* mtime register */
static u64 sifive_clint_get_count(struct udevice *dev)
{
- return readq((void __iomem *)MTIME_REG(dev->priv));
+ return readq((void __iomem *)MTIME_REG(dev_get_priv(dev)));
}
static const struct timer_ops sifive_clint_ops = {
static int sifive_clint_probe(struct udevice *dev)
{
- dev->priv = dev_read_addr_ptr(dev);
- if (!dev->priv)
+ dev_set_priv(dev, dev_read_addr_ptr(dev));
+ if (!dev_get_priv(dev))
return -EINVAL;
return timer_timebase_fallback(dev);
unsigned long notrace timer_get_rate(struct udevice *dev)
{
- struct timer_dev_priv *uc_priv = dev->uclass_priv;
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
return uc_priv->clock_rate;
}
static int rndis_control_ack(struct udevice *net)
#endif
{
- struct ether_priv *priv = (struct ether_priv *)net->priv;
- struct eth_dev *dev = &priv->ethdev;
- int length;
- struct usb_request *resp = dev->stat_req;
+ struct ether_priv *priv;
+ struct eth_dev *dev;
+ int length;
+ struct usb_request *resp;
+
+#ifndef CONFIG_DM_ETH
+ priv = (struct ether_priv *)net->priv;
+#else
+ priv = dev_get_priv(net);
+#endif
+ dev = &priv->ethdev;
+ resp = dev->stat_req;
/* in case RNDIS calls this after disconnect */
if (!dev->status) {
{
struct udevice *bus = udev->controller_dev;
struct dm_usb_ops *ops = usb_get_ops(bus);
- struct usb_uclass_priv *uc_priv = bus->uclass->priv;
+ struct usb_uclass_priv *uc_priv = uclass_get_priv(bus->uclass);
int err;
if (!ops->control)
if (ret)
return ret;
- uc_priv = uc->priv;
+ uc_priv = uclass_get_priv(uc);
uclass_foreach_dev(bus, uc) {
ret = device_remove(bus, DM_REMOVE_NORMAL);
if (ret)
return ret;
- uc_priv = uc->priv;
+ uc_priv = uclass_get_priv(uc);
uclass_foreach_dev(bus, uc) {
/* init low_level USB */
return 0;
/* Set up the video pointer, if this is the first device */
- uc_priv = dev->uclass->priv;
+ uc_priv = uclass_get_priv(dev->uclass);
if (!uc_priv->video_ptr)
uc_priv->video_ptr = gd->video_top;
case UCLASS_ETH: {
struct efi_device_path_mac_addr *dp =
dp_fill(buf, dev->parent);
- struct eth_pdata *pdata = dev->plat;
+ struct eth_pdata *pdata = dev_get_plat(dev);
dp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
dp->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_MAC_ADDR;
return NULL;
assert(uc);
- return uc->priv;
+ return uclass_get_priv(uc);
}
void eth_set_current_to_next(void)
struct eth_pdata *pdata;
if (eth_get_dev()) {
- pdata = eth_get_dev()->plat;
+ pdata = dev_get_plat(eth_get_dev());
return pdata->enetaddr;
}
if (!current || !device_active(current))
return -EINVAL;
- priv = current->uclass_priv;
+ priv = dev_get_uclass_priv(current);
priv->state = ETH_STATE_ACTIVE;
return 0;
if (!current || !device_active(current))
return;
- priv = current->uclass_priv;
+ priv = dev_get_uclass_priv(current);
priv->state = ETH_STATE_PASSIVE;
}
/* seq is valid since the device is active */
if (eth_get_ops(dev)->write_hwaddr && !eth_mac_skip(dev_seq(dev))) {
- pdata = dev->plat;
+ pdata = dev_get_plat(dev);
if (!is_valid_ethaddr(pdata->enetaddr)) {
printf("\nError: %s address %pM illegal value\n",
dev->name, pdata->enetaddr);
retval = uclass_find_device_by_seq(UCLASS_ETH, index, &dev);
if (!retval) {
- struct eth_pdata *pdata = dev->plat;
+ struct eth_pdata *pdata = dev_get_plat(dev);
switch (op) {
case env_op_create:
case env_op_overwrite:
ret = eth_get_ops(current)->start(current);
if (ret >= 0) {
struct eth_device_priv *priv =
- current->uclass_priv;
+ dev_get_uclass_priv(current);
priv->state = ETH_STATE_ACTIVE;
return 0;
return;
eth_get_ops(current)->stop(current);
- priv = current->uclass_priv;
+ priv = dev_get_uclass_priv(current);
if (priv)
priv->state = ETH_STATE_PASSIVE;
}
static int eth_post_probe(struct udevice *dev)
{
- struct eth_device_priv *priv = dev->uclass_priv;
- struct eth_pdata *pdata = dev->plat;
+ struct eth_device_priv *priv = dev_get_uclass_priv(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
unsigned char env_enetaddr[ARP_HLEN];
char *source = "DT";
static int eth_pre_remove(struct udevice *dev)
{
- struct eth_pdata *pdata = dev->plat;
+ struct eth_pdata *pdata = dev_get_plat(dev);
eth_get_ops(dev)->stop(dev);
ut_assert(priv);
ut_asserteq(expected_base_add, priv->base_add);
- pdata = dev->plat;
+ pdata = dev_get_plat(dev);
expected_base_add += pdata->ping_add;
}
for (i = 0; i < 3; i++) {
ut_assertok(uclass_find_device(UCLASS_TEST, i, &dev));
ut_assert(dev);
- pdata = dev->plat;
+ pdata = dev_get_plat(dev);
ut_assert(pdata->ping_add == test_pdata[i].ping_add);
}
ut_assert(dev);
ut_assert(dm_testdrv_op_count[DM_TEST_OP_BIND]
== op_count[DM_TEST_OP_BIND] + 1);
- ut_assert(!dev->priv);
+ ut_assert(!dev_get_priv(dev));
/* Probe the device - it should fail allocating private data */
dms->force_fail_alloc = 1;
ut_assert(ret == -ENOMEM);
ut_assert(dm_testdrv_op_count[DM_TEST_OP_PROBE]
== op_count[DM_TEST_OP_PROBE] + 1);
- ut_assert(!dev->priv);
+ ut_assert(!dev_get_priv(dev));
/* Try again without the alloc failure */
dms->force_fail_alloc = 0;
ut_assertok(device_probe(dev));
ut_assert(dm_testdrv_op_count[DM_TEST_OP_PROBE]
== op_count[DM_TEST_OP_PROBE] + 2);
- ut_assert(dev->priv);
+ ut_assert(dev_get_priv(dev));
/* This should be device 3 in the uclass */
ut_assertok(uclass_find_device(UCLASS_TEST, 3, &test_dev));
/* Getting the child device should allocate plat / priv */
ut_assertok(testfdt_ping(dev, 10, &pingret));
- ut_assert(dev->priv);
- ut_assert(dev->plat);
+ ut_assert(dev_get_priv(dev));
+ ut_assert(dev_get_plat(dev));
expected = 10 + base;
ut_asserteq(expected, pingret);
ut_asserteq(expected, pingret);
/* Now check the ping_total */
- priv = dev->priv;
+ priv = dev_get_priv(dev);
ut_asserteq(DM_TEST_START_TOTAL + 10 + 20 + base * 2,
priv->ping_total);
base = test_pdata[i].ping_add;
debug("dev=%d, base=%d\n", i, base);
- ut_assert(!dm_check_operations(uts, dev, base, dev->priv));
+ ut_assert(!dm_check_operations(uts, dev, base, dev_get_priv(dev)));
}
return 0;
ut_assertf(!(dev->flags & DM_FLAG_ACTIVATED),
"Driver %d/%s should have deactivated", i,
dev->name);
- ut_assert(!dev->priv);
+ ut_assert(!dev_get_priv(dev));
}
return 0;
ut_assertok(uclass_get(UCLASS_TEST, &uc));
ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_INIT]);
ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_DESTROY]);
- ut_assert(uc->priv);
+ ut_assert(uclass_get_priv(uc));
ut_assertok(uclass_destroy(uc));
ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_INIT]);
&driver_info_manual, &dev));
pdata = calloc(1, sizeof(*pdata));
pdata->ping_add = key + i;
- dev->plat = pdata;
+ dev_set_plat(dev, pdata);
if (child)
child[i] = dev;
}
#include <log.h>
#include <malloc.h>
#include <asm/io.h>
+#include <dm/device-internal.h>
#include <dm/test.h>
#include <test/test.h>
#include <test/ut.h>
static int test_unbind(struct udevice *dev)
{
/* Private data should not be allocated */
- ut_assert(!dev->priv);
+ ut_assert(!dev_get_priv(dev));
dm_testdrv_op_count[DM_TEST_OP_UNBIND]++;
return 0;
dm_testdrv_op_count[DM_TEST_OP_PROBE]++;
if (!dms->force_fail_alloc)
- dev->priv = calloc(1, sizeof(struct dm_test_priv));
- if (!dev->priv)
+ dev_set_priv(dev, calloc(1, sizeof(struct dm_test_priv)));
+ if (!dev_get_priv(dev))
return -ENOMEM;
return 0;
static int testfdt_drv_ping(struct udevice *dev, int pingval, int *pingret)
{
- const struct dm_test_pdata *pdata = dev->plat;
+ const struct dm_test_pdata *pdata = dev_get_plat(dev);
struct dm_test_priv *priv = dev_get_priv(dev);
*pingret = pingval + pdata->ping_add;
ret = uclass_find_device(UCLASS_TEST_FDT, i, &dev);
ut_assert(!ret);
ut_assert(!dev_get_priv(dev));
- ut_assert(dev->plat);
+ ut_assert(dev_get_plat(dev));
}
ut_assertok(dm_check_devices(uts, num_devices));
if (&prev->uclass_node != &uc->dev_head) {
struct dm_test_uclass_perdev_priv *prev_uc_priv
= dev_get_uclass_priv(prev);
- struct dm_test_pdata *pdata = prev->plat;
+ struct dm_test_pdata *pdata = dev_get_plat(prev);
ut_assert(pdata);
ut_assert(prev_uc_priv);
static int test_init(struct uclass *uc)
{
dm_testdrv_op_count[DM_TEST_OP_INIT]++;
- ut_assert(uc->priv);
+ ut_assert(uclass_get_priv(uc));
return 0;
}