From 263ddfc3454ead3a988adef39b962479adce2b28 Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Tue, 20 Oct 2020 11:04:51 +0800 Subject: [PATCH] mmc: fsl_esdhc: set sysctl register for clock initialization The initial clock setting should be through sysctl register only, while the mmc_set_clock() will call mmc_set_ios() introduce other configurations like bus width, mode, and so on. Signed-off-by: Yangbo Lu Reviewed-by: Jaehoon Chung --- drivers/mmc/fsl_esdhc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 642784e1f3..68130ee9f4 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -715,7 +715,7 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); /* Set the initial clock speed */ - mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE); + set_sysctl(priv, mmc, 400000); /* Disable the BRR and BWR bits in IRQSTAT */ esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); -- 2.39.5