Pali Rohár [Fri, 27 Aug 2021 12:14:44 +0000 (14:14 +0200)]
arm: a37xx: pci: Implement re-issuing config requests on CRS response
According to PCIe base specification, if CRS Software Visibility is not
enabled, the Root Complex must re-issue the Configuration Request as a new
Request.
Normally this part of Root Complex is implemented in hardware but aardvark
is somehow special and does not implement it in hardware and expect that
handling of config requests are fully implemented in software.
This re-issuing functionality is required also because U-Boot does not
support CRS Software Visibility feature and therefore expects that Root
Complex re-issues requests as is specified in PCIe base specification.
Retry / re-issue config request up to the PIO_MAX_RETRIES, to prevent
infinite loop. After retry count exceed PIO_MAX_RETRIES, returns failure.
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Fri, 27 Aug 2021 12:14:43 +0000 (14:14 +0200)]
arm: a37xx: pci: Disable returning CRS response
There was mistake in commit 4cd61c43fd51 ("arm: a37xx: pci: Fix handling
PIO config error responses"). U-Boot does not support handling of CRS
return value for PCI_VENDOR_ID config read request and also does not set
CRSSVE bit.
Therefore disable returning CRS response for now.
Signed-off-by: Pali Rohár <pali@kernel.org> Fixes: 4cd61c43fd51 ("arm: a37xx: pci: Fix handling PIO config error responses") Reviewed-by: Stefan Roese <sr@denx.de>
Sven Auhagen [Tue, 24 Aug 2021 08:14:25 +0000 (10:14 +0200)]
arm: mvebu: dts: Armada8k enable mdio
Since mvpp2 is using the new mdio driver and the cp110 has been
synced with the linux upstream, the mdio has to enabled in the
device tree file.
This is missing for some device tree files and therefore the
network cards do not come online.
Signed-off-by: Sven Auhagen <sven.auhagen@voleatech.de> Reviewed-by: Stefan Roese <sr@denx.de>
- Merge some fixes to how we enable hash algorithms for FIT images in
SPL. This fixes a few cases where we should have had some options
enabled, but did not. This also removes otherwise unused options in a
few other cases.
image: Drop if/elseif hash selection in calculate_hash()
calculate_hash() would try to select the appropriate hashing function
by a if/elseif contruct. But that is exactly why hash_lookup_algo()
exists, so use it instead.
This does mean that we now have to 'select HASH' to make sure we get
the hash_lookup_algo() symbol. However, the change makes sense because
even basic FITs will have to deal with "hash" nodes.
My only concern is that the 'select SPL_HASH' might cause some
platform to grow above its SPL size allowance
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
[trini: Make FSL_CAAM be implied only on ARM && SPL] Signed-off-by: Tom Rini <trini@konsulko.com>
MD5 is being called directly in some places, but it is not available
via hash_lookup_algo("md5"). This is inconsistent with other hasing
routines. To resolve this, add an "md5" entry to hash_algos[].
The #ifdef clause looks funnier than those for other entries. This is
because both MD5 and SPL_MD5 configs exist, whereas the other hashes
do not have "SPL_" entries. The long term plan is to get rid of the
ifdefs, so those should not be expected to survive much longer.
The md5 entry does not have .hash_init/update/finish members. That's
okay because hash_progressive_lookup_algo() will catch that, and
return -EPROTONOSUPPORT, while hash_lookup_algo() will return the
correct pointer.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
[trini: Use CONFIG_IS_ENABLED not IS_ENABLED for MD5 check] Signed-off-by: Tom Rini <trini@konsulko.com>
common/spl: Drop [ST]PL_HASH_SUPPORT in favor of [ST]PL_HASH
All of these configs exist. Stick to using CONFIG_[ST]PL_HASH, and drop all
references to CONFIG_[ST]PL_HASH_SUPPORT. This means we need for
CHAIN_OF_TRUST to select SPL_HASH now.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
[trini: Add TPL case, fix CHAIN_OF_TRUST, other tweaks] Signed-off-by: Tom Rini <trini@konsulko.com>
SHA512_ALGO was used as a "either SHA512 or SHA384", although the
implementations of these two algorithms share a majority of code.
From a Kconfig interface perspective, it makes sense to present two
distinct options. This requires #ifdefing out the SHA512
implementation from sha512.c. The latter doesn't make any sense.
It's reasonable to say in Kconfig that SHA384 depends on SHA512, and
seems to be the more polite way to handle the selection.
Thus, automatically select SHA512 when SHA384 is enabled.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Originally CONFIG_FIT_SHAxxx enabled specific SHA algos for and only
for hash_calculate() in common/image-fit.c. However, since commit 14f061dcb1 ("image: Drop IMAGE_ENABLE_SHAxxx"),
the correct selector was changed to CONFIG_SHAxxx.
The extra "_FIT_" variants are neither used, nor needed. Remove them.
One defconfig disables FIT_SHA256, which is now changed to 'SHA256'.
CMD_MVEBU_BUBT needs to select select SHA256 to avoid undefined
references to "sha256_*()". bubt.c needs sha256, so this selection is
correct. It is not clear why this problem did not manifest before.
Note that SHA selection in SPL is broken for this exact reason. There
is no corresponding SPL_SHAxxx. Fixing this is is beyond the scope of
this change.
Also note that we make CONFIG_FIT now imply SHA256, to make up for
FIT_SHA256 previously being a default y option.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
[trini: Add imply SHA256 to FIT] Signed-off-by: Tom Rini <trini@konsulko.com>
Zong Li [Wed, 1 Sep 2021 07:01:39 +0000 (15:01 +0800)]
cache: add sifive composable cache driver
This driver is currently responsible for enabling all ccache ways.
Composable cache could be configure as RAM or cache, we will use it as
RAM at the beginning to put the u-boot SPL there. In u-boot proper
phrase, we will use the composable cache as cache, and try to enable the
cache ways.
Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
Code starting with the faulting instruction
===========================================
0: 9002 ebreak
...
As it is not always clear if the first 16 bits are at the start or in the
middle of a 32bit instruction it may become necessary to strip the first
u16 from the output before calling decodecode to get the correct
disassembled code.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
On the HiFive Unmatched a PCI to SATA adapter may be used to install a SATA
drive. Enable booting from it.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
When booting in EFI, lib/efi_loader/efi_memory.c calls
board_get_usable_ram_top(0) which returns by default
gd->ram_base + gd->ram_size which is the top of DDR.
In case of OPTEE boot, the top of DDR is currently reserved by OPTEE,
board_get_usable_ram_top(0) must return an address outside OPTEE
reserved memory.
gd->ram_top matches this constraint as it has already been initialized
by substracting all DT reserved-memory (included OPTEE memory area).
Tom Rini [Sat, 4 Sep 2021 19:59:00 +0000 (15:59 -0400)]
Merge tag 'efi-2021-10-rc4' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request for efi-2021-10-rc4
Documentation:
Remove invalid reference to configuration variable in UEFI doc
UEFI:
Parameter checks for the EFI_TCG2_PROTOCOL
Improve support of preseeding UEFI variables.
Correct the calculation of the size of loaded images.
Allow for UEFI images with zero VirtualSize
TCG EFI Protocol Specification defines that PCRIndex parameter
passed from caller must be 0 to 23.
TPM2_MAX_PCRS is currently used to check the range of PCRIndex,
but TPM2_MAX_PCRS is tpm2 device dependent and may have larger value.
This commit newly adds EFI_TCG2_MAX_PCR_INDEX macro, it is used to
check the range of PCRIndex parameter.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Acked-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
TCG EFI Protocol Specification requires to the input
ProtocolCapability.Size < size of the EFI_TCG2_BOOT_SERVICE_CAPABILITY
up to and including the vendor ID field.
Current implementation does different calculation, let's fix it.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Masahisa Kojima [Fri, 3 Sep 2021 01:55:50 +0000 (10:55 +0900)]
efi_loader: add missing parameter check for EFI_TCG2_PROTOCOL api
TCG EFI Protocol Specification defines the required parameter
checking and return value for each API.
This commit adds the missing parameter check and
fixes the wrong return value to comply the specification.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
efi_loader: correct determination of secure boot state
When U-Boot is started we have to use the existing variables to determine
in which secure boot state we are.
* If a platform key PK is present and DeployedMode=1, we are in deployed
mode.
* If no platform key PK is present and AuditMode=1, we are in audit mode.
* Otherwise if a platform key is present, we are in user mode.
* Otherwise if no platform key is present, we are in setup mode.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
efi_loader: don't load signature database from file
The UEFI specification requires that the signature database may only be
stored in tamper-resistant storage. So these variable may not be read
from an unsigned file.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
We should not first allocate memory and then report a rounded up value as
image size. Instead first round up according to section allocation and then
allocate the memory.
Fixes: 82786754b9d2 ("efi_loader: ImageSize must be multiple of SectionAlignment") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Michal Simek [Fri, 27 Aug 2021 10:41:38 +0000 (12:41 +0200)]
doc: Remove information about CAPSULE_FMP_HEADER
This Kconfig symbol was never added to U-Boot but it was mentioned in the
origin commit c35df7c9e43e ("qemu: arm64: Add documentation for capsule
update"). That's why remove it from documentation to be accurate.
Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
DMA is aligned to ARCH_DMA_MINALIGN(64 bytes), but as per spec, alignment
required is 4bytes only. Change DMA alignment from ARCH_DMA_MINALIGN to
GQSPI_DMA_ALIGN. Remove alignment of data length in non-exponential case.
Some minor improvements in the initialization to initialize gen_fifo
threshold and disable qspi controller while setting config register.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
spi: zynqmp_gqspi: Switch genfifo start to manual mode
Current implementation uses auto mode for starting generic FIFO.
The recommendation from IP designers is to use manual mode, hence
change to manual start mode.
In fill genfifo first write to genfio and then trigger manual start.
Also enable and check for genfifo empty interrupt status in place of
genfifo not full interrupt.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 27 Aug 2021 10:27:46 +0000 (12:27 +0200)]
doc: Remove information about CAPSULE_FMP_HEADER
This Kconfig symbol was never added to U-Boot but it was mentioned in the
origin commit c35df7c9e43e ("qemu: arm64: Add documentation for capsule
update"). That's why remove it from documentation to be accurate.
Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
BTRFS volume consists of a number of subvolumes which can be mounted separately
from each other. The top-level subvolume always exists even if no subvolumes
were created manually. A subvolume can be denoted as the default subvolume i.e.
the subvolume which is mounted by default.
The default "default subvolume" is the top-level one, but this is far from the
common practices used in the wild. For instance, openSUSE provides an OS
snapshot/rollback feature based on BTRFS. To achieve this, the actual OS root
filesystem is located into a separate subvolume which is "default" but not
"top-level". That means that the /boot/dtb/ directory is also located inside
this default subvolume instead of top-level one.
However, the existing btrfs u-boot driver always uses the top-level subvolume
as the filesystem root. This behaviour 1) is inconsistent with
mount /dev/sda1 /target
command, which mount the default subvolume 2) leads to the issues when
/boot/dtb cannot be found properly (see the reference).
This patch uses the default subvolume as the filesystem root to overcome
mentioned issues.
Reference: https://bugzilla.suse.com/show_bug.cgi?id=1185656 Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com> Fixes: f06bfcf54d0e ("fs: btrfs: Crossport open_ctree_fs_info() from btrfs-progs") Reviewed-by: Qu Wenruo <wqu@suse.com>
Pali Rohár [Sun, 22 Aug 2021 10:31:35 +0000 (12:31 +0200)]
tools: kwbimage: Remove comment about unimplemented register headers in v1 images
Support for register headers in v1 images was implemented in commit 02ba70ad6822 ("tools: kwbimage: Add support for DATA command also for v1
images"). So remove old comment.
Signed-off-by: Pali Rohár <pali@kernel.org> Fixes: 02ba70ad6822 ("tools: kwbimage: Add support for DATA command also for v1 images") Reviewed-by: Stefan Roese <sr@denx.de>
Marek Behún [Mon, 16 Aug 2021 13:19:40 +0000 (15:19 +0200)]
arm: mvebu: turris_omnia: disable MCU watchdog in board_late_init()
Disable MCU watchdog in board_late_init() instead of board_init(), so
that it is disabled after U-Boot enables SOC watchdog instead of before.
This way there is no window when the board is vulnerable.
Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
Marek Behún [Mon, 16 Aug 2021 13:19:38 +0000 (15:19 +0200)]
arm: mvebu: turris_omnia: don't guard by CONFIG_SPL_BUILD macro
We do not need to guard code in board_init() and board_late_init()
functions with the CONFIG_SPL_BUILD macro, since these functions are not
called in SPL.
Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
3125000 matches divisor 5 with 250 MHz TCLK and divisor 4 with 200 MHz TCLK. 4000000 is the rounded value for divisor 4 with 250 MHz TCLK (3906250) and
divisor 3 with 200 MHz TCLK (4166666).
5150000 is the rounded value (5208333) for divisor 3 with 250 MHz TCLK.
Testing showed that rounded value is more stable then exactly calculated.
And it is the highest possible baudrate which is stable on A38x platform.
Any other baudrate values above 2500000 are unstable, which is reason why
e.g. standard value 3000000 is not defined, and it is needed to use
non-standard value 3125000.
Tested all defined UART baudrates on Turris Omnia (A38x with 250 MHz TCLK).
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
Tom Rini [Fri, 27 Aug 2021 12:33:02 +0000 (08:33 -0400)]
Merge tag 'xilinx-for-v2021.10-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2021.10-rc3
xilinx:
- Disable CONFIG_ARCH_FIXUP_FDT_MEMORY
- Print information about cpu via soc drivers and enable DISPLAY_CPUINFO
- Wire infrastructure for DTB_RESELECT and MULTI_DTB_FIT
zynq:
- Wire single QSPI
- Use power-source instead of io-standard properties
- Enable nor on zc770-xm012
zynqmp:
- Change handling around multi_boot()
- Setup offset for u-boot.itb in spi
- Generate run time dfu_alt_info for capsule update
- Use explicit values for enums (zynqmp_firmware.h)
- Enable RTC/SHA1/BUTTON/BUTTON_GPIO command
- Disable WDT driver by default
- Bind usb/scsi via preboot because of EFI
- DT updates/fixes
- Add soc driver
- Fix SPL SPI boot mode
versal:
- Add soc driver
sdhci:
- Update tap delay programming for zynq_sdhci driver
cmd:
- Fix RTC uclass handling in date command
- Update pwm help message
- Update reset help message
watchdog:
- Fix wwdt compilation
rtc:
- Deal with seq alias in rtc uclass
- Add zynqmp RTC driver
fdt:
- Add kernel-doc for fdt_fixup_memory_banks()
Michal Simek [Tue, 24 Aug 2021 12:56:47 +0000 (14:56 +0200)]
xilinx: zynqmp: Enable stack relocation to DDR
There is no space in OCM for SPL stack because the space in OCM is occupied
by TF-A. That's why move relocate stack to DDR to 0x18000000 address
and also enable SPL_SIZE_LIMIT not to be more then 0xfffea000 which is
default address for TFA.
It is good to summarize current DDR usage in SPL flow.
0-0x80000 is used for BSS
(CONFIG_SPL_BSS_START_ADDR, CONFIG_SPL_BSS_MAX_SIZE)
0x100000 is used for DTB passing address
(CONFIG_XILINX_OF_BOARD_DTB_ADDR)
0x17fffe70 - CONFIG_SPL_STACK_R_ADDR - is used for GD
0x18000000 is used for SPL stack
(CONFIG_SPL_STACK_R_ADDR)
0x20000000-0x21000000 is used for SPL malloc area
(CONFIG_SYS_SPL_MALLOC_START, CONFIG_SYS_SPL_MALLOC_SIZE)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 11 Aug 2021 12:23:54 +0000 (14:23 +0200)]
xilinx: common: Enabling generic function for DT reselection
U-Boot support board detection at run time and based on it change DT.
This feature is implemented for SOM Kria platforms which contain two
eeproms which contain information about SOM module and CC (Carrier card).
Full U-Boot starts with minimal DT file defined by
CONFIG_DEFAULT_DEVICE_TREE which is available in multi DTB fit image.
It is using default setup of board_name variable initializaed to
DEVICE_TREE which corresponds to CONFIG_DEFAULT_DEVICE_TREE option.
When DTB_RESELECT is enabled board_detection() is called. Keep it your mind
that this code is called before relocation. board_detection() is calling
xilinx_read_eeprom() which fills board_info (xilinx_board_description)
structure which are parsed in board_name_decode().
Based on DT configuration and amount of nvmemX aliases name of the board is
composed by concatenating CONFIG_SYS_BOARD "-" <board_name> "-rev"
<board_revision> "-" <cc_name> "-rev" <cc_revision>.
If CC is not present or more are available it keeps going.
When board name is composed and returned from board_name_decode() it is
assigned to board_name variable which is used by
board_fit_config_name_match() which is called via fdtdec_setup() when it
goes over config options in multi dtb FIT image.
From practical point of view multi DTB image is key point here which has to
contain configs for detected combinations. Unfortunately as of now they
have to be full DTBs and DTBOs are not supported.
needs to be squashed together with:
fdtoverlay -o zynqmp-board-cc -i arch/arm/dts/zynqmp-board.dtb \
arch/arm/dts/zynqmp-cc.dtbo
and only one dtb is in fit:
config_X {
description = "zynqmp-board-cc";
fdt = "board-cc";
};
For creating multi DTBs fit image use mkimage -E, e.g.:
mkimage -E -f all.its all.dtb
When DTB_RESELECT is enabled xilinx_read_eeprom() is called before
relocation and it uses calloc for getting a buffer. Because this is dynamic
memory it is not relocated that's why xilinx_read_eeprom() is called again
as the part of board_init(). This second read with calloc buffer placed in
proper position board_late_init_xilinx() can setup u-boot variables as
before.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 19 Aug 2021 10:02:57 +0000 (12:02 +0200)]
xilinx: zynqmp: Generate different u-boot.itb for MULTI_DTB_FIT
When MULTI_DTB_FIT is enabled fit-dtb.blob fit image is created which
contain all DTBs listed by CONFIG_OF_LIST. And with DTB_RELESELECT there is
a need to handle it as one file with DTBs in it not as separate DTBs in
u-boot.its/itb.
That's why extend mkimage_fit_atf.sh to generate u-boot.itb correctly.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 19 Aug 2021 09:09:37 +0000 (11:09 +0200)]
Makefile: Align fit-dtb.blob and u-boot.itb by 64bits
Enabling MULTI_DTB_FIT and DTB_RESELECT can end up with multi DTBs in FIT
image placed and aligned only by 32bits (4bytes). Based on device tree
specification:
"Specifically, the memory reservation block shall be aligned to an 8-byte boundary
and the structure block to a 4-byte boundary."
is 64bit (8bytes) alignment required. That's why make sure that
fit-dtb.blob and u-boot.itb as our primary target images for Xilinx ZynqMP
are all 64bit aligned.
Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Michal Simek [Thu, 19 Aug 2021 09:07:59 +0000 (11:07 +0200)]
xilinx: zynqmp: Check that DT is 64bit aligned
DT needs to be 64bit aligned. If it is not fdt64_to_cpu will fail when try
to read information about reserved memory. The system ends in exception
without any clue what's going it. That's why detect not aligned DT and
panic to show where the issue is coming from.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 23 Jul 2021 07:59:59 +0000 (09:59 +0200)]
xilinx: Add support for generic board detection
Add support for changing DT at run time. It is done via board_detection()
which returns platform_id and platform_version which can be used via
board_name_decode() to compose board_local_name string which corresponds
with DT which is should be used.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 12 Aug 2021 10:30:36 +0000 (12:30 +0200)]
xilinx: common: Change board_info[] handling
Origin code was allocating only pointers to struct xilinx_board_description
and there was separate allocation for structure self and freeing in case of
failure.
The code is directly allocating space for all structures by one calloc to
simlify logic.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 23 Jul 2021 07:55:59 +0000 (09:55 +0200)]
xilinx: Use variable for passing board_name
Use variable which points to DEVICE_TREE by default. The reason for this
change is to enable DTB_RESELECT and MULTI_DTB_FIT where board detection
can be used for change DTB at run time. That's why there must be reference
in board_fit_config_name_match() via variable instead of hardcoding it
which is sufficient for that use case.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 12 Aug 2021 09:03:49 +0000 (11:03 +0200)]
xilinx: fru: Replace spaces with \0 in detected name
FRU spec expected \0 for unused symbols but unfortunately a lot of boards
are using spaces instead of \0. That's why after saving it to desc->name
name is checked again and all spaces are converted to \0. This will ensure
that names can be used for string manipulations like concatenation.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 11 Aug 2021 10:01:25 +0000 (12:01 +0200)]
cmd: boot: Update reset usage message
The commit 573a3811edc8 ("sysreset: psci: support system reset in a generic
way with PSCI") has added support for warm reset via PSCI but this hasn't
been reflected in usage message and user has to look at the code how to run
it. That's why update usage text to make this clear.
Here is full help with updated usage:
ZynqMP> help reset
reset - Perform RESET of the CPU
Usage:
reset - cold boot without level specifier
reset -w - warm reset if implemented
Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Michal Simek [Thu, 1 Jul 2021 09:44:51 +0000 (11:44 +0200)]
cmd: pwm: Remove additional pwm description
The first name is taken from command name that's why shouldn't be listed in
help. And commands shouldn't be listed with <> which means value but value
itself is command name.
Also add description for commands to make it clear what it does.
T Karthik Reddy [Tue, 10 Aug 2021 12:50:19 +0000 (06:50 -0600)]
soc: xilinx: versal: Add soc_xilinx_versal driver
soc_xilinx_versal driver allows identification of family & revision
of versal SoC. This driver is selected by CONFIG_SOC_XILINX_VERSAL.
Probe this driver using platdata U_BOOT_DEVICE structure which is
defined at mach-versal/cpu.c.
Add this config to xilinx_versal_virt_defconfig &
xilinx_versal_mini_ospi_defconfig file to select this driver.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
T Karthik Reddy [Tue, 10 Aug 2021 12:50:18 +0000 (06:50 -0600)]
soc: xilinx: zynqmp: Add soc_xilinx_zynqmp driver
soc_xilinx_zynqmp driver allows identification of family & revision
of zynqmp SoC. This driver is selected by CONFIG_SOC_XILINX_ZYNQMP.
Add this config to xilinx_zynqmp_virt_defconfig file.
Probe this driver using platdata U_BOOT_DEVICE structure which is
specified in mach-zynqmp/cpu.c.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 10 Aug 2021 07:21:54 +0000 (09:21 +0200)]
fdt_support: Add kernel-doc for fdt_fixup_memory_banks()
Add kernel-doc description for fdt_fixup_memory_banks() because it is
implemented in one specific way and this information should be available
for others to decide if their SoC conforms to it.
If you don't want U-Boot to update your memory DT layout please disable
CONFIG_ARCH_FIXUP_FDT_MEMORY.
Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Michal Simek [Fri, 6 Aug 2021 12:09:32 +0000 (14:09 +0200)]
xilinx: Disable ARCH_FIXUP_FDT_MEMORY
Based on DT spec you can have one memory node which multiple ranges or
multiple nodes.
fdt_fixup_memory_banks() is not implemented in a correct way when multiple
memory nodes are present because all ranges are put it to the first memory
node found. And next memory nodes are kept in DT which ends up in the same
range specification in the same DT.
Here is what it is happening.
Origin DT.
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
xilinx: Add jedec compatible string for QSPI (Zynq/ZynqMP)
Add missing "jedec, spi-nor" compatible string for QSPI flash node.
Spi-nor framework uses this compatibility string to probe &
initialize flash. With missing compatibility string we are observing
below error:
Zynq> sf probe 0 0 0
jedec_spi_nor spi_flash@0:0: unrecognized JEDEC id bytes:
00, 00, 00 Failed to initialize SPI flash at 0:0 (error -2)
Signed-off-by: Raju Kumar Pothuraju <raju.kumar-pothuraju@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 29 Jul 2021 12:22:05 +0000 (14:22 +0200)]
xilinx: zynqmp: Initialize usb and scsi via preboot
Based on thread
https://lists.denx.de/pipermail/u-boot/2021-June/451828.html
especially
"Overall we have a deficiency in the UEFI implementation in that we
cannot deal with block devices added or removed after initialization."
there is a need to deal with removable media as usb/scsi/sata.
That's why bridge this gap in EFI implementation by resetting usb and
scsi resets to get all disks before efi_init_obj_list() is called.
In our standard boot flow, where we use distro boot, order is fixed as
"jtag mmc0 mmc1 qspi0 nand0 usb0 usb1 scsi0 pxe dhcp" with prioritizing
boot device added by commit 2882b39d564b ("arm64: zynqmp: Setup the first
boot_target at run time").
When device has ESP partition all devices should be detected because then
efi_disk_register() in efi_init_obj_list() is called only once.
The first such a device is sd/emmc(mmc0/mmc1) and then disks on usb/sata
are not handled at all.
The commit 6bb577dbb30f ("arm64: zynqmp: Disable
EFI_CAPSULE_ON_DISK_EARLY") also pointed out on this issue but detection of
removable media wasn't solved that's why do it now via preboot command.
I have tested cases without usb and scsi and there is no problem with
calling resets without devices itself.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 6 Aug 2021 07:18:17 +0000 (09:18 +0200)]
arm64: zynqmp: Disable WDT_CDNS driver by default
Do not enable watchdog driver in default zynqmp configuration. The reason
is that not all distributions are handling watchdog properly and then
expires and system resets. If someone needs watchdog in their design please
enable it by hand.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
T Karthik Reddy [Tue, 3 Aug 2021 05:20:45 +0000 (23:20 -0600)]
mmc: zynq_sdhci: Wait till sd card detect state is stable
As per SD spec when SD host controller is reset, it takes 1000msec
to detect the card state. In case, if we enable the sd bus voltage &
card detect state is not stable, then host controller will disable
the sd bus voltage.
In case of warm/subsystem reboot, due to unstable card detect state
host controller is disabling the sd bus voltage to sd card causing
sd card timeout error. So we wait for a maximum of 1000msec to get
the card detect state stable before we enable the sd bus voltage.
This current fix is workaround for now, this needs to be analysed
further. Zynqmp platform should behave the same as Versal, but we
did not encounter this issue as of now. So we are fixing it for
Versal only.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
mmc: zynq_sdhci: Move setting tapdelay code to driver
Move tapdelay function calls to zynq_sdhci.c and make them static
inline. zynqmp_tap_delay.h has function prototypes for the functions
defined in tap_delays.c, which will not be needed anymore.
mmc: zynq_sdhci: Add xilinx_pm_request() method to set tapdelays
Currently xilinx sdhci driver is using zynqmp_mmio_write() to set
tapdelay values and DLL resets. Continue to use this for SPL and mini
U-Boot where U-Boot will be executed at EL3 level.
Use firmware call xilinx_pm_request() using appropriate arguments to
set input/output tapdelays and also for DLL resets in regular flow(EL2).
Host driver should explicitly request DLL reset before ITAP (assert DLL)
and after OTAP (release DLL) to avoid issues in some cases. Also handle
error return where possible.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
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