Raymond Mao [Thu, 3 Oct 2024 21:50:38 +0000 (14:50 -0700)]
asn1_decoder: add build options for ASN1 decoder
When building with MbedTLS, we are using MbedTLS to decode ASN1 data
for x509, pkcs7 and mscode.
Introduce _LEGACY and _MBEDTLS kconfigs for ASN1 decoder legacy and
MbedTLS implementations respectively.
Signed-off-by: Raymond Mao <raymond.mao@linaro.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Raymond Mao [Thu, 3 Oct 2024 21:50:36 +0000 (14:50 -0700)]
mbedtls: add RSA helper layer on MbedTLS
Add RSA helper layer on top on MbedTLS PK and RSA library.
Introduce _LEGACY and _MBEDTLS kconfigs for RSA helper legacy and
MbedTLS implementations respectively.
Signed-off-by: Raymond Mao <raymond.mao@linaro.org> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Raymond Mao [Thu, 3 Oct 2024 21:50:35 +0000 (14:50 -0700)]
lib/crypto: Adapt mscode_parser to MbedTLS
Previous patch has introduced MbedTLS porting layer for mscode parser,
here to adjust the header and makefiles accordingly.
Adding _LEGACY Kconfig for legacy mscode implementation.
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Raymond Mao [Thu, 3 Oct 2024 21:50:32 +0000 (14:50 -0700)]
mbedtls: add PKCS7 parser porting layer
Add porting layer for PKCS7 parser on top of MbedTLS PKCS7 library.
Introduce _LEGACY and _MBEDTLS kconfigs for PKCS7 parser legacy and
MbedTLS implementations respectively.
Signed-off-by: Raymond Mao <raymond.mao@linaro.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Raymond Mao [Thu, 3 Oct 2024 21:50:30 +0000 (14:50 -0700)]
mbedtls: add X509 cert parser porting layer
Add porting layer for X509 cert parser on top of MbedTLS X509
library.
Introduce _LEGACY and _MBEDTLS kconfigs for X509 cert parser legacy
and MbedTLS implementations respectively.
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Raymond Mao [Thu, 3 Oct 2024 21:50:28 +0000 (14:50 -0700)]
mbedtls: add public key porting layer
Add porting layer for public key on top of MbedTLS X509 library.
Introduce _LEGACY and _MBEDTLS kconfigs for public key legacy and
MbedTLS implementations respectively.
Signed-off-by: Raymond Mao <raymond.mao@linaro.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Raymond Mao [Thu, 3 Oct 2024 21:50:24 +0000 (14:50 -0700)]
mbedtls/external: update MbedTLS PKCS7 test suites
Update the PKCS7 test suites for multiple certs.
The PR for this patch is at:
https://github.com/Mbed-TLS/mbedtls/pull/9001
For enabling EFI loader PKCS7 features with MbedTLS build,
we need this patch on top of MbedTLS v3.6.0 before it is merged into
the next MbedTLS LTS release.
Signed-off-by: Raymond Mao <raymond.mao@linaro.org> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Raymond Mao [Thu, 3 Oct 2024 21:50:23 +0000 (14:50 -0700)]
mbedtls/external: support decoding multiple signer's cert
Support decoding multiple signer's cert in the signed data within
a PKCS7 message.
The PR for this patch is at:
https://github.com/Mbed-TLS/mbedtls/pull/9001
For enabling EFI loader PKCS7 features with MbedTLS build,
we need this patch on top of MbedTLS v3.6.0 before it is merged into
the next MbedTLS LTS release.
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Raymond Mao [Thu, 3 Oct 2024 21:50:22 +0000 (14:50 -0700)]
mbedtls/external: support PKCS9 Authenticate Attributes
Populate PKCS9 Authenticate Attributes from signer info if it exists
in a PKCS7 message.
Add OIDs for describing objects using for Authenticate Attributes.
The PR for this patch is at:
https://github.com/Mbed-TLS/mbedtls/pull/9001
For enabling EFI loader PKCS7 features with MbedTLS build,
we need this patch on top of MbedTLS v3.6.0 before it is merged into
the next MbedTLS LTS release.
Signed-off-by: Raymond Mao <raymond.mao@linaro.org> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Raymond Mao [Thu, 3 Oct 2024 21:50:21 +0000 (14:50 -0700)]
mbedtls/external: support Microsoft Authentication Code
Populate Microsoft Authentication Code from the content data
into PKCS7 decoding context if it exists in a PKCS7 message.
Add OIDs for describing objects using for Microsoft Authentication
Code.
The PR for this patch is at:
https://github.com/Mbed-TLS/mbedtls/pull/9001
For enabling EFI loader PKCS7 features with MbedTLS build,
we need this patch on top of MbedTLS v3.6.0 before it is merged into
the next MbedTLS LTS release.
Signed-off-by: Raymond Mao <raymond.mao@linaro.org> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Raymond Mao [Thu, 3 Oct 2024 21:50:20 +0000 (14:50 -0700)]
mbedtls: Enable smaller implementation for SHA256/512
Smaller implementation for SHA256 and SHA512 helps to reduce the
ROM footprint though it has a certain impact on performance.
As a trade-off, enable it as a default config when MbedTLS is
enabled can reduce the target size significantly with acceptable
performance loss.
Signed-off-by: Raymond Mao <raymond.mao@linaro.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Raymond Mao [Thu, 3 Oct 2024 21:50:18 +0000 (14:50 -0700)]
sha1: Remove sha1 non-watchdog API
We don't need an API specially for non-watchdog since sha1_csum_wd
supports it by disabling CONFIG_HW_WATCHDOG and CONFIG_WATCHDOG.
Set 0x10000 as default chunk size for SHA1.
Signed-off-by: Raymond Mao <raymond.mao@linaro.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Raymond Mao [Thu, 3 Oct 2024 21:50:17 +0000 (14:50 -0700)]
md5: Remove md5 non-watchdog API
We don't need an API specially for non-watchdog since md5_wd supports
it by disabling CONFIG_HW_WATCHDOG and CONFIG_WATCHDOG.
Set 0x10000 as default chunk size for MD5.
Signed-off-by: Raymond Mao <raymond.mao@linaro.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Michal Simek <michal.simek@amd.com>
Raymond Mao [Thu, 3 Oct 2024 21:50:16 +0000 (14:50 -0700)]
lib: Adapt digest header files to MbedTLS
Adapt digest header files to support both original libs and MbedTLS
by switching on/off MBEDTLS_LIB_CRYPTO.
Introduce <alg>_LEGACY kconfig for legacy hash implementations.
sha256.o should depend on SHA256 kconfig only but not SUPPORT_EMMC_RPMB,
SHA256 should be selected when SUPPORT_EMMC_RPMB is enabled instead.
`IS_ENABLED` or `CONFIG_IS_ENABLED` is not applicable here, since
including <linux/kconfig.h> causes undefined reference on schedule()
with sandbox build, as <linux/kconfig.h> includes <generated/autoconf.h>
which enables `CONFIG_HW_WATCHDOG` and `CONFIG_WATCHDOG` but no schedule()
are defined in sandbox build,
Thus we use `#if defined(CONFIG_MBEDTLS_LIB_CRYPTO)` instead.
Signed-off-by: Raymond Mao <raymond.mao@linaro.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Raymond Mao [Thu, 3 Oct 2024 21:50:15 +0000 (14:50 -0700)]
mbedtls: add mbedtls into the build system
Port mbedtls with adapted libc header files.
Add mbedtls default config header file.
Optimize mbedtls default config by disabling unused features to
reduce the target size.
Add mbedtls kbuild makefile.
Add Kconfig skeleton and config submenu entry for selecting
crypto libraries between mbedtls and legacy ones.
Add the mbedtls include directories into the build system.
Port u-boot hash functions as MbedTLS crypto alternatives and set
it as default.
Subsequent patches will separate those Kconfigs into pairs of
_LEGACY and _MBEDTLS for controlling the implementations of legacy
crypto libraries and MbedTLS ones respectively.
The motivation of moving and adapting *INT* macros from kernel.h
to limits.h is to fulfill the MbedTLS building requirement.
The conditional compilation statements in MbedTLS expects the
*INT* macros as constant expressions, thus expressions like
`((int)(~0U >> 1))` will not work.
Prerequisite
------------
This patch series requires mbedtls git repo to be added as a
subtree to the main U-Boot repo via:
Raymond Mao [Thu, 3 Oct 2024 21:50:14 +0000 (14:50 -0700)]
CI: Exclude MbedTLS subtree for CONFIG checks
Since MbedTLS is an external repo with its own coding style,
exclude it from Azure and gitlab CI CONFIG checks.
Signed-off-by: Raymond Mao <raymond.mao@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Daniel Palmer [Sun, 29 Sep 2024 09:27:39 +0000 (18:27 +0900)]
cmd: Make bootvx independent of bootelf
There are lots of usecases for running baremetal ELF
binaries via bootelf but if you enable bootelf you
get bootvx as well and you probably don't want or need
it.
mkimage: ecdsa: add signature/key nodes to dtb if missing
If the signature/key node(s) are not yet present in the U-Boot device
tree, ecdsa_add_verify_data simply fails if it can't find the nodes.
This behaviour differs from rsa_add_verify_data, wich does add the missing
nodes and proceeds in that case.
This change is mainly copy&paste from rsa_add_verify_data to add the
same behaviour to ecdsa_add_verify_data.
Jonas Karlman [Sun, 4 Aug 2024 15:09:52 +0000 (15:09 +0000)]
serial: ns16550: Try get serial clock rate from DT before CLK
Initializing a clock driver to read a known static clock rate can take
some time at U-Boot proper pre-reloc phase.
Change to first try and read clock rate from DT to speed up boot time,
fall back to getting the clock rate from clock driver.
This help reduce boot time by around:
- ~35ms on a Radxa ROCK Pi 4 (RK3399)
- ~15ms on a Radxa ZERO 3W (RK3566)
Time that is wasted getting a static rate known at compile time.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Simon Glass <sjg@chromium.org>
Chris Webb [Wed, 31 Jul 2024 10:01:31 +0000 (11:01 +0100)]
pinctrl: mediatek: Bind gpio while binding pinctrl
Mediatek pinctrl drivers call mtk_gpiochip_register() to bind the child
gpio controller as part of mtk_pinctrl_common_probe(). This breaks
gpiohog support because the gpio controller is bound too late for
DM_FLAG_PROBE_AFTER_BIND (set while binding hogs) to work.
Move the mtk_gpiochip_register() to mtk_pinctrl_common_bind() and call
this as the .bind method of each of the mediatek pinctrl drivers.
Marek Vasut [Sat, 5 Oct 2024 17:45:02 +0000 (19:45 +0200)]
clk: renesas: rcar-gen3: Fix SSCG caching replacement with MDSEL/PE caching
The SSCG is active with MDSEL[12] is not set. Previous commit 99c7e031196d ("clk: renesas: rcar-gen3: Replace SSCG caching
with MDSEL/PE caching") inverted the conditional assignment
of priv->sscg = !(cpg_mode & BIT(12)) during conversion from
(priv->sscg ? 16 : 0) to priv->cpg_mode & BIT(core->offset) ? 16 : 0;
Invert the assignment back to the correct state.
This fixes R8A77980, R8A77990, R8A77995 and R8A774C0.
Fixes: 99c7e031196d ("clk: renesas: rcar-gen3: Replace SSCG caching with MDSEL/PE caching") Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Tom Rini [Sat, 5 Oct 2024 17:18:38 +0000 (11:18 -0600)]
Merge branch 'u-boot-nand-20241005' of https://gitlab.denx.de/u-boot/custodians/u-boot-nand-flash into next
These are a number of assorted upstream Linux fixes to the
BRCMNAND driver.
This patch set lowers the hamming distance between the Linux
and U-Boot drivers a bit as well, while we deviate quite
a bit it is still possible to bring fixes over thanks to
exercises like this.
The patches pass the pipeline CI:
https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/pipelines/22535
William Zhang [Mon, 16 Sep 2024 09:58:49 +0000 (11:58 +0200)]
mtd: rawnand: brcmnand: Add support for getting ecc setting from strap
Backport from the upstream Linux kernel
commit c2cf7e25eb2a3c915a420fb8ceed8912add7f36c
"mtd: rawnand: brcmnand: Add support for getting ecc setting from strap"
Note: the upstream kernel introduces a new
bool brcmnand_get_sector_size_1k() function because the int
version in U-Boot has been removed in Linux. I kept the old
int-returning version that is already in U-Boot as we depend
on that in other code.
BCMBCA broadband SoC based board design does not specify ecc setting in
dts but rather use the SoC NAND strap info to obtain the ecc strength
and spare area size setting. Add brcm,nand-ecc-use-strap dts propety for
this purpose and update driver to support this option. However these two
options can not be used at the same time.
Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: David Regan <dregan@broadcom.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20240301173308.226004-1-william.zhang@broadcom.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: William Zhang <william.zhang@broadcom.com> Tested-by: William Zhang <william.zhang@broadcom.com>
Augmented to also support the "write-protect" boolean property.
The write protection feature is controlled by the module parameter wp_on
with default set to enabled. But not all the board use this feature
especially in BCMBCA broadband board. And module parameter is not
sufficient as different board can have different option. Add a device
tree property and allow this feature to be configured through the board
dts on per board basis.
Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Reviewed-by: Kamal Dasu <kamal.dasu@broadcom.com> Reviewed-by: David Regan <dregan@broadcom.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20240223034758.13753-14-william.zhang@broadcom.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: William Zhang <william.zhang@broadcom.com>
mtd: rawnand: brcmnand: Add read data bus interface
This is a port of the read data bus interface from the Linux
brcmnand driver, commit 546e425991205f59281e160a0d0daed47b7ca9b3
"mtd: rawnand: brcmnand: Add BCMBCA read data bus interface"
This is needed for the BCMBCA RAW NAND driver.
Signed-off-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: William Zhang <william.zhang@broadcom.com>
brcmnand controller can only access the flash spare area up to certain
bytes based on the ECC level. It can be less than the actual flash spare
area size. For example, for many NAND chip supporting ECC BCH-8, it has
226 bytes spare area. But controller can only uses 218 bytes. So brcmand
driver overrides the mtd oobsize with the controller's accessible spare
area size. When the nand base driver utilizes the nand_device object, it
resets the oobsize back to the actual flash spare aprea size from
nand_memory_organization structure and controller may not able to access
all the oob area as mtd advises.
This change fixes the issue by overriding the oobsize in the
nand_memory_organization structure to the controller's accessible spare
area size.
Fixes: a7ab085d7c16 ("mtd: rawnand: Initialize the nand_device object") Signed-off-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20230706182909.79151-6-william.zhang@broadcom.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: William Zhang <william.zhang@broadcom.com>
When the oob buffer length is not in multiple of words, the oob write
function does out-of-bounds read on the oob source buffer at the last
iteration. Fix that by always checking length limit on the oob buffer
read and fill with 0xff when reaching the end of the buffer to the oob
registers.
If system is busy during the command status polling function, the driver
may not get the chance to poll the status register till the end of time
out and return the premature status. Do a final check after time out
happens to ensure reading the correct status.
v7.2 controller has different ECC level field size and shift in the acc
control register than its predecessor and successor controller. It needs
to be set specifically.
- Add DA9063 watchdog support for the imx6q-lxr2 board.
- Add support for DH electronics i.MX8M Plus DHCOM PicoITX
- Add DH i.MX8MP DHCOM SoM on DRC02 carrier board
- Several fsl_esdhc_imx improvements.
- Pas no-mmc-hs400 to mmc2 on imx8mm-cl-iot-gate.
Tom Rini [Fri, 4 Oct 2024 15:01:44 +0000 (09:01 -0600)]
Merge branch 'qcom-next' of https://source.denx.de/u-boot/custodians/u-boot-snapdragon into next
* Initial UFS PHY driver
* Support for SM8150 (clock and pinctrl)
* Allow writing configuration to PMIC GPIOs again
* Support for configuring "special" pins (e.g. UFS reset or sdhc pins)
* Support for "clk dump" command to decode various clocks.
Peter Robinson [Fri, 4 Oct 2024 10:40:44 +0000 (11:40 +0100)]
Update directories for new name of TF-A directories
The TF-A URL was updated, as a result the name of the
directory changed as part of the new git URL and not
all the referenced directories were updated.
Fixes: 0ec0207fe07 ("Update the ARM trusted firmware git URL") Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Jonas Karlman [Fri, 4 Oct 2024 06:21:34 +0000 (06:21 +0000)]
rockchip: Provid SPL control over otp presence
The series "rockchip: Add efuse and otp support to more SoCs" [1],
merged in v2023.04, refactored and extended the Rockchip efuse and otp
driver to support reading eFUSE/OTP for all supported Rockchip SoCs.
Due to use of different licenses the drivers were never combined into a
single driver, however anything non SoC specific should be applied to
both drivers.
The commit fe38b88453d2 ("rockchip: Provided SPL control over efuse
presence") changed Makefile options for only one of the two drivers,
apply same change to keep these two drivers in sync.
Caleb Connolly [Mon, 19 Aug 2024 19:34:17 +0000 (21:34 +0200)]
clk/qcom: implement clk dump
Add support for dumping a few of the clocks used on Qualcomm platforms.
Naming the Global PLL's, Root Clock Generators, and gate clocks.
This helps a lot with platform bringup and feature enablement by making
it easy to sanity check that the clocks are programmed correctly.
== Usage ==
Enable CONFIG_CMD_CLK and "#define LOG_DEBUG" at the top of
qcom-<soc>.c.
The "clk dump" command should print the states of all the gates, GPLLs
and RCGs for your SoC.
== Glossary ==
RCG: Root Clock Generator
* Takes in some fairly arbitrary high freq clock (configurable clock
source and options for taking just even pulses and other things)
* Output frequency = input_freq * (m/n) * (1/d) where m/n are arbitrary
8 or 16-bit values (depending on the RCG), and d is a number (with
support for .5 offsets).
GPLL: Global Phase Locked Loop
* Crystal as input
* integer multiplier + exponent part (2^-40)
Gate: Simple on/off clock
* Put between RCGs and the peripherals they power
* Required to allow for correct power sequencing
If you do the maths manually using the equations from "clk dump", the
numbers should roughly line up by they're likely to be out by a handful
of MHz. They output is formatted so that it can be pasted directly into
the python interpreter.
The bug in writing was caused by a long-standing error in the SPMI
driver which has since been fixed - c2de620d64d4 ("spmi: msm: fix
version 5 support"). We can safely enable writing GPIO configuration
now.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Julius Lehmann [Wed, 11 Sep 2024 17:13:10 +0000 (19:13 +0200)]
pinctrl: qcom: add driver for SM8150 SoC
Add pinctrl and GPIO driver for SM8150. Driver code is based on the
similar U-Boot drivers. All constants are taken from the corresponding
Linux driver. This drivers differs from the similar U-Boot drivers,
because SM8150 SoC have different function IDs for the same functions
on different pins.
Co-authored-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Julius Lehmann <lehmanju@devpi.de> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Julius Lehmann [Wed, 11 Sep 2024 17:13:09 +0000 (19:13 +0200)]
clk: qcom: add driver for SM8150 SoC
Add clock, reset and power domain driver for SM8150. Driver code is
based on the similar U-Boot drivers. All constants are taken from the
corresponding Linux driver.
This driver supports clock rate setting only debug UART,
RGMII/Ethernet modules and USB controller.
Co-authored-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Julius Lehmann <lehmanju@devpi.de> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Vitor Soares [Tue, 1 Oct 2024 16:01:52 +0000 (17:01 +0100)]
arm: imx: imx8m: soc: Fix VPU fdt disable fixup
With the introduction of downstream Linux 6.6, the iMX8MP VPU block
control node in DTS was renamed "blk-ctl@38330000" and will not match
the ones found in `node_path_imx8mp` resulting in the node not being
disabled on the VPU-less variants.
Add an extra node_path entry for imx8mp VPU block control that match
with downstream Linux.
Signed-off-by: Vitor Soares <vitor.soares@toradex.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Tue, 1 Oct 2024 13:07:57 +0000 (21:07 +0800)]
mmc: fsl_esdhc_imx: Reset tuning logic
When supporting partition reset for SoC such as i.MX95 , the Linux
Kernel may have configured the tuning, while after force reset by
wdog or else, uboot CMD0 will never pass unless config RSTT to reset
tuning logic.
Since RSTA and RSTT are independent, so need both to be reseted in the
controller.
Acked-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Tue, 1 Oct 2024 13:07:55 +0000 (21:07 +0800)]
mmc: fsl_esdhc_imx: Fix host_caps issue for non-DM driver
The plat->cfg is wrongly memset to 0, so the host_caps value configured
in fsl_esdhc_initialize is reset. Remove the unnecessary memset since
plat is allocated via calloc.
Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Tue, 1 Oct 2024 13:07:54 +0000 (21:07 +0800)]
mmc: fsl_esdhc_imx: Send 80 clocks before IDLE command
According to SD and MMC spec, 74 clocks must be sent to device after
power stable. This is need in reinit ops for DM MMC or init ops for
non-DM MMC after power cycle.
So set the INTIA to send 80 clocks in esdhc_init_common and move
its calling from probe to reinit.
However, on 8MQ EVK and 8QXP MEK with some brands of SD cards, sending
80 clocks may not work well.
The root cause is related with power up time. According to spec, after
power stable, host shall supply at least 74 SD clocks to the SD card with
the maximum of 1ms. However, the power ram up time is related with the
characteristic of SD card. At the moment of sending 74 SD clocks, the
power probably not ram up to the operating level on the problematic
cards. Then cause the cards not ready.
This patch changes to send SD clock with 1ms duration to replace 80
SD clocks (0.2ms at 400Khz clock).
This way meets the spec requirement as well, and adds the margin for
power ram up time to be compatible with the problematic SD cards.
This is also aligned with implementation which has FORCE clock
always on.
Reviewed-and-tested-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Tue, 1 Oct 2024 13:07:53 +0000 (21:07 +0800)]
mmc: fsl_esdhc_imx: Enable AHB/IPG clk with clk bulk API
With partition reset supported for i.MX8QM/QXP/95 and etc, when linux
mmc runtime suspended, the mmc clks are gated off. While at same time
system controller reset Cortex-A cores because of various reasons(
WDOG timeout and etc), with SPL run again, only enable PER clk is not
enough, also need to enable AHB/IPG clk, here use clk bulk API to enable
all the clocks.
Ye Li [Sun, 29 Sep 2024 01:32:26 +0000 (09:32 +0800)]
gpio: adp5585: Add SPL config for ADP5585 driver
So we can disable to build ADP5585 in SPL to save size
Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Alice Guo <alice.guo@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
Marek Vasut [Wed, 25 Sep 2024 16:07:17 +0000 (18:07 +0200)]
arm64: dts: imx8mp: Add DH i.MX8MP DHCOM SoM on DRC02 carrier board
Add support for DH electronics i.MX8MP DHCOM SoM on DRC02 carrier board.
This system is populated with two ethernet ports, two CANs, RS485 and RS232,
USB, capacitive buttons and an OLED display.
Matching Linux kernel patch has been posted:
https://lore.kernel.org/imx/20240925160343.84388-2-marex@denx.de/
Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
Marek Vasut [Sat, 28 Sep 2024 23:52:35 +0000 (01:52 +0200)]
arm64: dts: imx8mp: Add support for DH electronics i.MX8M Plus DHCOM PicoITX
Add support for DH electronics i.MX8M Plus DHCOM SoM on PicoITX carrier board.
This system is populated with serial console, EQoS ethernet, eMMC, SD, SPI NOR,
LEDs and USB 3.0 host used in USB 2.0 mode on PicoITX.
Matching Linux kernel patch has been posted:
https://lore.kernel.org/imx/20240928234949.357893-2-marex@denx.de/
Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
Simon Glass [Fri, 20 Sep 2024 07:24:37 +0000 (09:24 +0200)]
mmc: Add more debugging for SPL
When MMC booting fails it is sometimes hard to figure out what went
wrong as there is no error code. It isn't even clear which MMC device
was chosen, since SPL can have its own numbering.
Simon Glass [Fri, 20 Sep 2024 07:24:29 +0000 (09:24 +0200)]
tiny-printf: Correct return values
The sprintf() etc. functions are supposed to return the length of the
string written, but do not. Fix this by checking the amount of buffer
space used.
Before
commit da3447d09fa0 ("android: Fix ramdisk loading for bootimage v3+"),
the ramdisk was loaded from img_data.ramdisk_ptr, ignoring offset
provided via mkbootimg.
commit da3447d09fa0 ("android: Fix ramdisk loading for bootimage v3+")
rightfully fixes this by switching to use img_data.ramdisk_addr instead.
However, it does not copy the ramdisk content to img_data.ramdisk_addr
in case we use boot image v2.
Because of this, we can no longer boot Android on Khadas vim3 board:
[ 3.940361] RAMDISK: Couldn't find valid RAM disk image starting at 0.
Tom Rini [Thu, 3 Oct 2024 15:30:37 +0000 (09:30 -0600)]
Merge patch series "arm: Initial support for Analog Devices SC5xx boards"
Oliver Gaskell <Oliver.Gaskell@analog.com> says:
ADSP-SC5xx is a series of ARM-based DSPs.
This comprises the armv7 based SC57x, SC58x and SC594 series, and the
armv8 based SC598.
This patch series includes configurations, init code, and minimal DTs
to enable Analog Devices' evaluation boards for these SoCs to boot
through SPL and into U-Boot Proper, as well as devicetree schemas for
the added DTs.
This patch series depends on ("arm: Add Analog Devices SC5xx Machine
Type") (https://lists.denx.de/pipermail/u-boot/2024-April/552043.html)
Oliver Gaskell [Thu, 12 Sep 2024 15:51:01 +0000 (16:51 +0100)]
arm: SC573-EZKIT initial support
Adds support for Analog Devices' SC573-EZKIT board. Includes:
- SoC specific configs in mach-sc5xx/Kconfig
- Memory Map for SPL
- Necessary board-specific init functions
- Board-specific Kconfig and environment in board/adi/
- Memory configuration
Oliver Gaskell [Thu, 12 Sep 2024 15:51:00 +0000 (16:51 +0100)]
arm: SC589-MINI initial support
Adds support for Analog Devices' SC589-MINI board. Includes:
- Board specific configs in mach-sc5xx/Kconfig
- Board-specific Kconfig and environment in board/adi/
Signed-off-by: Oliver Gaskell <Oliver.Gaskell@analog.com>
projects / u-boot.git / log
;st=author){kind=link}
