vexpress: disable cci ace slave ports when booting in non-sec/hyp mode
Commit f225d39d3093 ("vexpress: Check TC2 firmware support before defaulting
to nonsec booting") added support to check if the firmware on TC2 is
configured appropriately before booting in nonsec/hyp mode.
However when booting in non-secure/hyp mode, CCI control must be done in
secure firmware and can't be done in non-secure/hyp mode. In order to
ensure that, this patch disables the cci slave port inteface so that it
is not accessed at all.
Cc: Jon Medhurst <tixy@linaro.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Jon Medhurst <tixy@linaro.org> Tested-by: Jon Medhurst <tixy@linaro.org>
Chris Packham [Fri, 23 Sep 2016 03:59:43 +0000 (15:59 +1200)]
common/console.c: ensure GD_FLG_SILENT is set or cleared
When CONFIG_SILENT_CONSOLE is defined and the default environment has
silent=1 it is not possible for a user to make the console un-silent if
the environment is not available when console_init_f() is called (for
example because the environment is in SPI).
Add a new helper function console_update_silent() and call it from both
console_init_f() and console_init_r().
Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
ARM: OMAP5+: Override switch_to_hypervisor function
Override the switch_to_hypervisor function to switch cpu to hypervisor
mode using the available ROM code hook early in the boot phase before
the boot loader checks for HYP mode.
Based on the work done by Jonathan Bergsagel jbergsagel@ti.com.
Cc: beagleboard-x15@googlegroups.com Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
ARM: Introduce function to switch to hypervisor mode
On some of the SoCs one cannot enable hypervisor mode directly from the
u-boot because the ROM code puts the chip to supervisor mode after it
jumps to boot loader. Hence introduce a weak function which can be
overridden based on the SoC type and switch to hypervisor mode in a
custom way.
Cc: beagleboard-x15@googlegroups.com Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
omap: Set appropriate cache configuration for LPAE and non-LAPE cases
Cache configuration methods is different for LPAE and non-LPAE cases.
Hence the bits and the interpretaion is different for two cases.
In case of non-LPAE mode short descriptor format is used and we need
to set Cache and Buffer bits.
In the case of LPAE the cache configuration happens via MAIR0 lookup.
Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
omap: Remove hardcoding of mmu section shift to 20
As of now the mmu section shift is hardcoded to 20 but with LPAE
coming into picture this can be different. Hence replacing 20 with
MMU_SECTION_SHIFT macro.
Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Tweaks (no functional changes) to include/search.h, including:
* use standard multiple inclusion check
* fix spelling mistakes
* have comments match actual names in function prototypes
* remove obsolete reference to "do_apply"
* replace "hashing table" with "hash table"
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
When enabled sec firmware framework, but lack of definition of
the marco SEC_FIRMWARE_FIT_IMAGE, SEC_FIRMEWARE_FIT_CNF_NAME
and SEC_FIRMWARE_TARGET_EL, there will be some build errors,
so give a default definition.
ARM: Respect CONFIG_SPL_STACK define in lowlevel_init.S
The SPL and U-Boot proper may use different initial stack
locations, which are configured via CONFIG_SPL_STACK and
CONFIG_SYS_INIT_SP_ADDR defines. The lowlevel_init.S
code needs to handle this in the same way as crt0.S
Without this fix, setting the U-Boot stack location to some
place, which is not safely accessible by the SPL (such as
the DRAM), causes a very early SPL deadlock.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Andreas Fenkart [Mon, 29 Aug 2016 21:17:00 +0000 (23:17 +0200)]
Suspected Spam: Do not open attachements![PATCH 4/6] tools/env: flash_write_buf: enforce offset to be start of environment
This allows to take advantage of the environment being block aligned.
This is not a new constraint. Writes always start at the begin of the
environment, since the header with CRC/length as there.
Every environment modification requires updating the header
Signed-off-by: Andreas Fenkart <andreas.fenkart@digitalstrom.com>
Andreas Fenkart [Mon, 29 Aug 2016 21:16:59 +0000 (23:16 +0200)]
tools/env: lookup dev_type directly from flash_read_buf/flash_write_buf
flash_write_buf already looks up size/offset/#sector from struct
envdev_s. It can look up mtd_type as well. Same applies to
flash_read_buf. Makes the interface simpler
Signed-off-by: Andreas Fenkart <andreas.fenkart@digitalstrom.com>
Andreas Fenkart [Mon, 29 Aug 2016 21:16:58 +0000 (23:16 +0200)]
tools/env: pass bad block offset by value
the offset is not modified by linux ioctl call
see mtd_ioctl{drivers/mtd/mtdchar.c}
Makes the interface less ambiguous, since the caller can
now exclude a modification of blockstart
Signed-off-by: Andreas Fenkart <andreas.fenkart@digitalstrom.com>
Clemens Gruber [Mon, 29 Aug 2016 15:10:36 +0000 (17:10 +0200)]
gunzip: cache-align write buffer memory
When using gzwrite to eMMC on an i.MX6Q board, the following warning
occurs repeatedly:
CACHE: Misaligned operation at range [4fd63318, 4fe63318]
This patch cache-aligns the memory allocation for the gzwrite writebuf,
therefore avoiding the misaligned dcache flush and the warning from
check_cache_range.
Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com> Reviewed-by: Eric Nelson <eric@nelint.com> Reviewed-by: Stefan Agner <stefan.agner@toradex.com>
Simon Glass [Mon, 3 Oct 2016 00:01:11 +0000 (18:01 -0600)]
README: Fix CONFIG_SYS_NAND_MAX_DEVICE typo
This should be CONFIG_SYS_MAX_NAND_DEVICE. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Scott Wood <oss@buserror.net> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <york.sun@nxp.com>
Simon Glass [Mon, 3 Oct 2016 00:01:08 +0000 (18:01 -0600)]
atmel: Drop README.at91-soc
This issue covered by this doc appears to be fixed, so let's remove the
README.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <york.sun@nxp.com> Acked-by: Andreas Bießmann <andreas@biessmann.org>
Simon Glass [Mon, 3 Oct 2016 00:01:05 +0000 (18:01 -0600)]
README: i2c: Drop unused i2c CONFIG options
CONFIG_SYS_NUM_I2C_ADAPTERS and CONFIG_SYS_I2C_MULTI_NOPROBES are not used
in U-Boot, so drop them.
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <york.sun@nxp.com>
Simon Glass [Sun, 25 Sep 2016 00:20:17 +0000 (18:20 -0600)]
spl: Make spl_boot_list a local variable
There is no need for this to be in the BSS region. By moving it we can delay
use of BSS in SPL. This is useful for machines where the BSS region is not
in writeable space. On 64-bit x86, SPL runs from SPI flash and it is easier
to eliminate BSS use than link SPL to run with BSS at a particular
cache-as-RAM (CAR) address.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
Simon Glass [Sun, 25 Sep 2016 00:20:13 +0000 (18:20 -0600)]
spl: Pass spl_image as a parameter to load_image() methods
Rather than having a global variable, pass the spl_image as a parameter.
This avoids BSS use, and makes it clearer what the function is actually
doing.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
Simon Glass [Sun, 25 Sep 2016 00:20:11 +0000 (18:20 -0600)]
spl: Convert spl_net_load_image() to use linker list
Add a linker list declaration for this method and remove the explicit
switch() code. We need two variants - one for BOOT_DEVICE_CPGMAC and one for
BOOT_DEVICE_USBETH.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
Simon Glass [Sun, 25 Sep 2016 00:20:10 +0000 (18:20 -0600)]
spi: Move freescale-specific code into a private header
At present there are two SPI functions only used by freescale which are
defined in the spi_flash.h header. One function name matches an existing
generic SPL function.
Move these into a private header to avoid confusion.
Arcturus looks like it does not actually support SPI, so drop the SPI code
from that board.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
Simon Glass [Sun, 25 Sep 2016 00:19:59 +0000 (18:19 -0600)]
spl: Convert spl_ram_load_image() to use linker list
Add a linker list declaration for this method and remove the explicit
switch() code.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Include updating the DFU case] Signed-off-by: Tom Rini <trini@konsulko.com>
Simon Glass [Sun, 25 Sep 2016 00:19:51 +0000 (18:19 -0600)]
spl: Move spl_board_load_image() into a generic header
At present this is only used on ARM and sandbox, but it is just as
applicable to other architectures. Move the function prototype into the
generic SPL header.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
Andrew F. Davis [Tue, 30 Aug 2016 19:06:28 +0000 (14:06 -0500)]
ti_armv7_common: Disable Falcon Mode on HS devices
Authentication of images in Falcon Mode is not supported. Do not enable
SPL_OS_BOOT when TI_SECURE_DEVICE is enabled. This prevents attempting
to directly load kernel images which will fail, for security reasons,
on HS devices, the board is locked if a non-authenticatable image load
is attempted, so we disable attempting Falcon Mode.
Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Andrew F. Davis [Tue, 30 Aug 2016 19:06:25 +0000 (14:06 -0500)]
ti: omap-common: Allow AM33xx devices to be built securely
Like OMAP54xx and AM43xx family SoCs, AM33xx based SoCs have high
security enabled models. Allow AM33xx devices to be built with
HS Device Type Support.
Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Andrew F. Davis [Tue, 30 Aug 2016 19:06:24 +0000 (14:06 -0500)]
board: am33xx-hs: Allow post-processing of FIT image on AM33xx
When CONFIG_FIT_IMAGE_POST_PROCESS or CONFIG_SPL_FIT_IMAGE_POST_PROCESS
is enabled board_fit_image_post_process will be called, add this
function to am33xx boards when CONFIG_TI_SECURE_DEVICE is set to
verify the loaded image.
Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Andrew F. Davis [Tue, 30 Aug 2016 19:06:23 +0000 (14:06 -0500)]
am33xx: config.mk: Fix option used to enable SPI SPL image type
The option SPL_SPI_SUPPORT is used to enable support in SPL for loading
images from SPI flash, it should not be used to determine the build type
of the SPL image itself. The ability to read images from SPI flash does
not imply the SPL will be booted from SPI flash.
Andrew F. Davis [Tue, 30 Aug 2016 19:06:21 +0000 (14:06 -0500)]
am33xx: config.mk: Add support for additional secure boot image types
Depending on the boot media, different images are needed
for secure devices. The build generates u-boot*_HS_* files
as appropriate for the different boot modes.
For AM33xx devices additional image types are needed for
various SPL boot modes as the ROM checks for the name of
the boot mode in the file it loads.
Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Andrew F. Davis [Tue, 30 Aug 2016 19:06:20 +0000 (14:06 -0500)]
Kconfig: Separate AM33XX SOC config from target board config
The config option AM33XX is used in several boards and should be
defined as a stand-alone option for this SOC. We break this out
from target boards that use this SoC and common headers then enable
AM33XX on in all the boards that used these targets to eliminate any
functional change with this patch.
This is similar to what has already been done in 9de852642cae ("arm: Kconfig: Add support for AM43xx SoC specific Kconfig")
and is done for the same reasons.
Signed-off-by: Andrew F. Davis <afd@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Daniel Allred [Fri, 2 Sep 2016 05:40:24 +0000 (00:40 -0500)]
ARM: omap5: add fdt secure dram reservation fixup
Adds a secure dram reservation fixup for secure
devices, when a region in the emif has been set aside
for secure world use. The size is defined by the
CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE config option.
Signed-off-by: Daniel Allred <d-allred@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Daniel Allred [Fri, 2 Sep 2016 05:40:23 +0000 (00:40 -0500)]
ti_omap5_common: mark region of DRAM protected on HS parts
If the ending portion of the DRAM is reserved for secure
world use, then u-boot cannot use this memory for its relocation
purposes. To prevent issues, we mark this memory as PRAM and this
prevents it from being used by u-boot at all.
Daniel Allred [Fri, 2 Sep 2016 05:40:22 +0000 (00:40 -0500)]
ARM: DRA7: Add secure emif setup calls
After EMIF DRAM is configured, but before it is used,
calls are made on secure devices to reserve any configured
memory region needed by the secure world and then to lock the
EMIF firewall configuration. If any other firewall
configuration needs to be applied, it must happen before the
lock call.
Daniel Allred [Fri, 2 Sep 2016 05:40:21 +0000 (00:40 -0500)]
arm: omap5: secure API for EMIF memory reservations
Create a few public APIs which rely on secure world ROM/HAL
APIs for their implementation. These are intended to be used
to reserve a portion of the EMIF memory and configure hardware
firewalls around that region to prevent public code from
manipulating or interfering with that memory.
Signed-off-by: Daniel Allred <d-allred@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Daniel Allred [Fri, 2 Sep 2016 05:40:20 +0000 (00:40 -0500)]
ti: omap5: Add Kconfig options for secure EMIF reservations
Adds start address and size config options for setting aside
a portion of the EMIF memory space for usage by security software
(like a secure OS/TEE). There are two sizes, a total size and a
protected size. The region is divided into protected (secure) and
unprotected (public) regions, that are contiguous and start at the
start address given. If the start address is zero, the intention
is that the region will be automatically placed at the end of the
available external DRAM space.
Jacob Chen [Mon, 19 Sep 2016 10:46:28 +0000 (18:46 +0800)]
rockchip: add boot-mode support for rk3288, rk3036
rockchip platform have a protocol to pass the the kernel reboot mode to bootloader
by some special registers when system reboot. In bootloader we should read it and take action.
We can only setup boot_mode in board_late_init becasue "setenv" need env setuped.
So add CONFIG_BOARD_LATE_INIT to common header and use a entry "rk_board_late_init"
to replace "board_late_init" in board file.
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Fri, 23 Sep 2016 07:57:22 +0000 (15:57 +0800)]
dts: evb-rk3399: add init voltage node for vdd-center
Add a regulator-init-microvolt for vdd_center regulator
so that we can get a init value for driver probe.
Not like pmic regulator, the PWM regulator do not have a
known default output value, so we would like to init the
regulator when driver probe.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Fri, 23 Sep 2016 07:57:18 +0000 (15:57 +0800)]
rockchip: rkpwm: fix the register sequence
Reference to kernel source code, rockchip pwm has three
type, we are using v2 for rk3288 and rk3399, so let's
update the register to sync with pwm_data_v2 in kernel.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Fri, 23 Sep 2016 07:57:17 +0000 (15:57 +0800)]
rockchip: rk3399: update PPLL and pmu_pclk frequency
Update PPLL to 676MHz and PMU_PCLK to 48MHz, because:
1. 48MHz can make sure the pwm can get exact 50% duty ratio, but 99MHz
can not,
2. We think 48MHz is fast enough for pmu pclk and it is lower power cost
than 99MHz,
3. PPLL 676 MHz and PMU_PCLK 48MHz are the clock rate we are using
internally for kernel,it suppose not to change the bus clock like pmu_pclk
in kernel, so we want to change it in uboot.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
Sandy Patterson [Mon, 29 Aug 2016 11:31:17 +0000 (07:31 -0400)]
Enable ROCKCHIP_SPL_BACK_TO_BROM for rock2 board
Rock2 has been tested with back to brom feature. The tricky part is that
with this feature the default environment is inside u-boot, and it's
defined for every rk3288 board independetly. So I just changed it for
rock2 here if ROCKCHIP_SPL_BACK_TO_BROM.
Solve by moving environment after u-boot before 1M boundary
Signed-off-by: Sandy Patterson <apatterson@sightlogix.com> Acked-by: Simon Glass <sjg@chromium.org>
Sandy Patterson [Wed, 10 Aug 2016 14:21:47 +0000 (10:21 -0400)]
rockchip: Fix SPL console output when ROCKCHIP_SPL_BACK_TO_BROM is enabled
Move back_to_bootrom() call later in SPL init so that the console is
initialized and printouts happen.
Currently when ROCKCHIP_SPL_BACK_TO_BROM is enabled there is no console
output from the SPL init stages.
I wasn't sure exactly where this should happen, so if we are set to do
run spl_board_init, then go back to bootrom there after
preloader_console_init(). Otherwise fall back to old behavior of doing
it in board_init_f.
The all current Rockchip SoCs supporting 4GB of ram have problems
accessing the memory region 0xfe000000~0xff000000. Actually, some IP
controller can't address to, so let's limit the available range.
This patch fixes a bug which found in miniarm-rk3288-4GB board. The
U-Boot was relocated to 0xfef72000, and .bss variants was also
relocated, such as do_fat_read_at_block. Once eMMC controller transfer
data to do_fat_read_at_block via DMA, DMAC can't access more than
0xfe000000. So that DMAC didn't work sane.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
projects / u-boot.git / log
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