From: Bo Gan <ganboing@gmail.com>
Date: Wed, 6 Mar 2024 03:00:11 +0000 (-0800)
Subject: riscv: dts: jh7110: Enable PLL node in SPL
X-Git-Url: http://git.dujemihanovic.xyz/%22http:/www.sics.se/static/git-favicon.png?a=commitdiff_plain;h=e6b7aeef3df206b9f2a47e715d643b735d18ae73;p=u-boot.git

riscv: dts: jh7110: Enable PLL node in SPL

Previously PLL node was missing from SPL dts. This caused BUS_ROOT
to stay on OSC clock (24Mhz). As a result, all peripherals have to
run at a much lower frequency, and loading from sdcard/emmc is slow.
Thus, enabling PLL node in dts to fix this.

Signed-off-by: Bo Gan <ganboing@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---

diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi
index 2f560e7296..c09d5c9170 100644
--- a/arch/riscv/dts/jh7110-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-u-boot.dtsi
@@ -93,6 +93,10 @@
 	bootph-pre-ram;
 };
 
+&pllclk {
+	bootph-pre-ram;
+};
+
 &S7_0 {
 	status = "okay";
 };