From: Caleb Connolly Date: Mon, 26 Feb 2024 17:26:17 +0000 (+0000) Subject: pinctrl: qcom: stub support for special GPIOs X-Git-Url: http://git.dujemihanovic.xyz/%22http:/www.sics.se/static/git-favicon.png?a=commitdiff_plain;h=a245aece2acfbbaf01f41c595f9bfb02a9aedb70;p=u-boot.git pinctrl: qcom: stub support for special GPIOs Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usual naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue. Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop. Reviewed-by: Neil Armstrong Reviewed-by: Sumit Garg Tested-by: Sumit Garg #qcs404 Signed-off-by: Caleb Connolly --- diff --git a/arch/arm/mach-snapdragon/include/mach/gpio.h b/arch/arm/mach-snapdragon/include/mach/gpio.h index 8dac62f870..53c6ae0649 100644 --- a/arch/arm/mach-snapdragon/include/mach/gpio.h +++ b/arch/arm/mach-snapdragon/include/mach/gpio.h @@ -13,6 +13,8 @@ struct msm_pin_data { int pin_count; const unsigned int *pin_offsets; + /* Index of first special pin, these are ignored for now */ + unsigned int special_pins_start; }; static inline u32 qcom_pin_offset(const unsigned int *offs, unsigned int selector) @@ -25,4 +27,9 @@ static inline u32 qcom_pin_offset(const unsigned int *offs, unsigned int selecto return out; } +static inline bool qcom_is_special_pin(const struct msm_pin_data *pindata, unsigned int pin) +{ + return pindata->special_pins_start && pin >= pindata->special_pins_start; +} + #endif /* _QCOM_GPIO_H_ */ diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c index 80cd28bb23..5e57b0cbde 100644 --- a/drivers/gpio/msm_gpio.c +++ b/drivers/gpio/msm_gpio.c @@ -39,6 +39,10 @@ static int msm_gpio_direction_input(struct udevice *dev, unsigned int gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev); + /* Always NOP for special pins, assume they're in the correct state */ + if (qcom_is_special_pin(priv->pin_data, gpio)) + return 0; + /* Disable OE bit */ clrsetbits_le32(priv->base + GPIO_CONFIG_REG(dev, gpio), GPIO_OE_MASK, GPIO_OE_DISABLE); @@ -50,6 +54,10 @@ static int msm_gpio_set_value(struct udevice *dev, unsigned int gpio, int value) { struct msm_gpio_bank *priv = dev_get_priv(dev); + /* Always NOP for special pins, assume they're in the correct state */ + if (qcom_is_special_pin(priv->pin_data, gpio)) + return 0; + value = !!value; /* set value */ writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_REG(dev, gpio)); @@ -62,6 +70,10 @@ static int msm_gpio_direction_output(struct udevice *dev, unsigned int gpio, { struct msm_gpio_bank *priv = dev_get_priv(dev); + /* Always NOP for special pins, assume they're in the correct state */ + if (qcom_is_special_pin(priv->pin_data, gpio)) + return 0; + value = !!value; /* set value */ writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_REG(dev, gpio)); @@ -76,6 +88,10 @@ static int msm_gpio_get_value(struct udevice *dev, unsigned int gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev); + /* Always NOP for special pins, assume they're in the correct state */ + if (qcom_is_special_pin(priv->pin_data, gpio)) + return 0; + return !!(readl(priv->base + GPIO_IN_OUT_REG(dev, gpio)) >> GPIO_IN); } @@ -83,6 +99,10 @@ static int msm_gpio_get_function(struct udevice *dev, unsigned int gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev); + /* Always NOP for special pins, assume they're in the correct state */ + if (qcom_is_special_pin(priv->pin_data, gpio)) + return 0; + if (readl(priv->base + GPIO_CONFIG_REG(dev, gpio)) & GPIO_OE_ENABLE) return GPIOF_OUTPUT; diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c index 8149ffd83c..c860b748e9 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8016.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c @@ -55,7 +55,10 @@ static unsigned int apq8016_get_function_mux(unsigned int selector) } static const struct msm_pinctrl_data apq8016_data = { - .pin_data = { .pin_count = 133, }, + .pin_data = { + .pin_count = 133, + .special_pins_start = 122, + }, .functions_count = ARRAY_SIZE(msm_pinctrl_functions), .get_function_name = apq8016_get_function_name, .get_function_mux = apq8016_get_function_mux, diff --git a/drivers/pinctrl/qcom/pinctrl-apq8096.c b/drivers/pinctrl/qcom/pinctrl-apq8096.c index d64ab1ff7b..75d1d0956a 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8096.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8096.c @@ -50,7 +50,10 @@ static unsigned int apq8096_get_function_mux(unsigned int selector) } static const struct msm_pinctrl_data apq8096_data = { - .pin_data = { .pin_count = 157, }, + .pin_data = { + .pin_count = 157, + .special_pins_start = 150, + }, .functions_count = ARRAY_SIZE(msm_pinctrl_functions), .get_function_name = apq8096_get_function_name, .get_function_mux = apq8096_get_function_mux, diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c index 2d99f99e1e..74c04ab87c 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c @@ -46,7 +46,10 @@ static unsigned int ipq4019_get_function_mux(unsigned int selector) } static const struct msm_pinctrl_data ipq4019_data = { - .pin_data = { .pin_count = 100, }, + .pin_data = { + .pin_count = 100, + .special_pins_start = 100, /* There are no special pins */ + }, .functions_count = ARRAY_SIZE(msm_pinctrl_functions), .get_function_name = ipq4019_get_function_name, .get_function_mux = ipq4019_get_function_mux, diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c b/drivers/pinctrl/qcom/pinctrl-qcom.c index dc3d8c4d90..ee0624df29 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcom.c +++ b/drivers/pinctrl/qcom/pinctrl-qcom.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include "pinctrl-qcom.h" @@ -83,6 +84,10 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector, { struct msm_pinctrl_priv *priv = dev_get_priv(dev); + /* Always NOP for special pins, assume they're in the correct state */ + if (qcom_is_special_pin(&priv->data->pin_data, pin_selector)) + return 0; + clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector), TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE, priv->data->get_function_mux(func_selector) << 2); @@ -94,6 +99,10 @@ static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector, { struct msm_pinctrl_priv *priv = dev_get_priv(dev); + /* Always NOP for special pins */ + if (qcom_is_special_pin(&priv->data->pin_data, pin_selector)) + return 0; + switch (param) { case PIN_CONFIG_DRIVE_STRENGTH: argument = (argument / 2) - 1; @@ -136,6 +145,9 @@ int msm_pinctrl_bind(struct udevice *dev) const char *name; int ret; + if (!data->pin_data.special_pins_start) + dev_warn(dev, "Special pins start index not defined!\n"); + drv = lists_driver_lookup_name("pinctrl_qcom"); if (!drv) return -ENOENT; diff --git a/drivers/pinctrl/qcom/pinctrl-qcs404.c b/drivers/pinctrl/qcom/pinctrl-qcs404.c index ac00afa2a1..b54c8d80b8 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcs404.c +++ b/drivers/pinctrl/qcom/pinctrl-qcs404.c @@ -61,8 +61,11 @@ static unsigned int qcs404_get_function_mux(unsigned int selector) return msm_pinctrl_functions[selector].val; } -static struct msm_pinctrl_data qcs404_data = { - .pin_data = { .pin_count = 126, }, +static const struct msm_pinctrl_data qcs404_data = { + .pin_data = { + .pin_count = 126, + .special_pins_start = 120, + }, .functions_count = ARRAY_SIZE(msm_pinctrl_functions), .get_function_name = qcs404_get_function_name, .get_function_mux = qcs404_get_function_mux, diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c index 9f0f4085ce..76bd8c4ef4 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm845.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c @@ -75,10 +75,11 @@ static unsigned int sdm845_get_function_mux(unsigned int selector) return msm_pinctrl_functions[selector].val; } -static struct msm_pinctrl_data sdm845_data = { +static const struct msm_pinctrl_data sdm845_data = { .pin_data = { .pin_offsets = sdm845_pin_offsets, - .pin_count = ARRAY_SIZE(sdm845_pin_offsets), + .pin_count = 154, + .special_pins_start = 150, }, .functions_count = ARRAY_SIZE(msm_pinctrl_functions), .get_function_name = sdm845_get_function_name,