From: Saksham Jain <saksham.jain@nxp.com>
Date: Wed, 23 Mar 2016 10:54:39 +0000 (+0530)
Subject: armv8: ls2080: Add config for endianess of CCSR GUR
X-Git-Tag: v2025.01-rc5-pxa1908~9757^2~10
X-Git-Url: http://git.dujemihanovic.xyz/%22http:/www.sics.se/static/git-favicon.png?a=commitdiff_plain;h=809d343a1a778e68d519c04e01118bd8eb990eff;p=u-boot.git

armv8: ls2080: Add config for endianess of CCSR GUR

The GUR (DCFG) registers in CCSR space are in little endian format.
Define a config CONFIG_SYS_FSL_CCSR_GUR_LE in
arch/arm/include/asm/arch-fsl-layerscape/config.h

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
---

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index cc25811fc1..ceefe431fd 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -82,6 +82,9 @@
 /* Secure Boot */
 #define CONFIG_ESBC_HDR_LS
 
+/* DCFG - GUR */
+#define CONFIG_SYS_FSL_CCSR_GUR_LE
+
 /* Cache Coherent Interconnect */
 #define CCI_MN_BASE			0x04000000
 #define CCI_MN_RNF_NODEID_LIST		0x180