rockchip: sdram: Move all DT decoding to ofdata_to_platdata()

It is more correct to avoid touching the device tree in the probe() method.
Update the driver to work this way. Note that only SPL needs to fiddle with
the SDRAM registers, so decoding the platform data fully is not necessary in
U-Boot proper.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/include/asm/arch-rockchip/sdram.h b/arch/arm/include/asm/arch-rockchip/sdram.h
index c9e3001720ed86849346023e6f2e006aceb55372..e08e28f4f0c5c9e9e81c3f77db85972162512e46 100644 (file)
--- a/arch/arm/include/asm/arch-rockchip/sdram.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram.h
@@ -87,12 +87,4 @@ struct rk3288_base_params {
        u32 odt;
 };
 
-struct rk3288_sdram_params {
-       struct rk3288_sdram_channel ch[2];
-       struct rk3288_sdram_pctl_timing pctl_timing;
-       struct rk3288_sdram_phy_timing phy_timing;
-       struct rk3288_base_params base;
-       int num_channels;
-};
-
 #endif

diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
index 55ac73e9d25111eb96345e07d66cd7af9f80e9ed..940ee58a642ccd9dd1b59c87ae6c8257c6eb291a 100644 (file)
--- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
@@ -41,6 +41,16 @@ struct dram_info {
        struct rk3288_grf *grf;
        struct rk3288_sgrf *sgrf;
        struct rk3288_pmu *pmu;
+       bool is_veyron;
+};
+
+struct rk3288_sdram_params {
+       struct rk3288_sdram_channel ch[2];
+       struct rk3288_sdram_pctl_timing pctl_timing;
+       struct rk3288_sdram_phy_timing phy_timing;
+       struct rk3288_base_params base;
+       int num_channels;
+       struct regmap *map;
 };
 
 #ifdef CONFIG_SPL_BUILD
@@ -703,7 +713,7 @@ static int sdram_init(struct dram_info *dram,
 
        return 0;
 }
-#endif
+#endif /* CONFIG_SPL_BUILD */
 
 size_t sdram_size_mb(struct rk3288_pmu *pmu)
 {
@@ -779,18 +789,35 @@ static int veyron_init(struct dram_info *priv)
 static int setup_sdram(struct udevice *dev)
 {
        struct dram_info *priv = dev_get_priv(dev);
-       struct rk3288_sdram_params params;
+       struct rk3288_sdram_params *params = dev_get_platdata(dev);
+
+# ifdef CONFIG_ROCKCHIP_FAST_SPL
+       if (priv->is_veyron) {
+               int ret;
+
+               ret = veyron_init(priv);
+               if (ret)
+                       return ret;
+       }
+# endif
+
+       return sdram_init(priv, params);
+}
+
+static int rk3288_dmc_ofdata_to_platdata(struct udevice *dev)
+{
+       struct rk3288_sdram_params *params = dev_get_platdata(dev);
        const void *blob = gd->fdt_blob;
        int node = dev->of_offset;
        int i, ret;
 
-       params.num_channels = fdtdec_get_int(blob, node,
-                                            "rockchip,num-channels", 1);
-       for (i = 0; i < params.num_channels; i++) {
+       params->num_channels = fdtdec_get_int(blob, node,
+                                             "rockchip,num-channels", 1);
+       for (i = 0; i < params->num_channels; i++) {
                ret = fdtdec_get_byte_array(blob, node,
                                            "rockchip,sdram-channel",
-                                           (u8 *)&params.ch[i],
-                                           sizeof(params.ch[i]));
+                                           (u8 *)&params->ch[i],
+                                           sizeof(params->ch[i]));
                if (ret) {
                        debug("%s: Cannot read rockchip,sdram-channel\n",
                              __func__);
@@ -798,41 +825,44 @@ static int setup_sdram(struct udevice *dev)
                }
        }
        ret = fdtdec_get_int_array(blob, node, "rockchip,pctl-timing",
-                                  (u32 *)&params.pctl_timing,
-                                  sizeof(params.pctl_timing) / sizeof(u32));
+                                  (u32 *)&params->pctl_timing,
+                                  sizeof(params->pctl_timing) / sizeof(u32));
        if (ret) {
                debug("%s: Cannot read rockchip,pctl-timing\n", __func__);
                return -EINVAL;
        }
        ret = fdtdec_get_int_array(blob, node, "rockchip,phy-timing",
-                                  (u32 *)&params.phy_timing,
-                                  sizeof(params.phy_timing) / sizeof(u32));
+                                  (u32 *)&params->phy_timing,
+                                  sizeof(params->phy_timing) / sizeof(u32));
        if (ret) {
                debug("%s: Cannot read rockchip,phy-timing\n", __func__);
                return -EINVAL;
        }
        ret = fdtdec_get_int_array(blob, node, "rockchip,sdram-params",
-                                  (u32 *)&params.base,
-                                  sizeof(params.base) / sizeof(u32));
+                                  (u32 *)&params->base,
+                                  sizeof(params->base) / sizeof(u32));
        if (ret) {
                debug("%s: Cannot read rockchip,sdram-params\n", __func__);
                return -EINVAL;
        }
+#ifdef CONFIG_ROCKCHIP_FAST_SPL
+       struct dram_info *priv = dev_get_priv(dev);
 
-# ifdef CONFIG_ROCKCHIP_FAST_SPL
-       if (!fdt_node_check_compatible(blob, 0, "google,veyron")) {
-               ret = veyron_init(priv);
-               if (ret)
-                       return ret;
-       }
-# endif
+       priv->is_veyron = !fdt_node_check_compatible(blob, 0, "google,veyron");
+#endif
+       ret = regmap_init_mem(dev, &params->map);
+       if (ret)
+               return ret;
 
-       return sdram_init(priv, &params);
+       return 0;
 }
-#endif
+#endif /* CONFIG_SPL_BUILD */
 
 static int rk3288_dmc_probe(struct udevice *dev)
 {
+#ifdef CONFIG_SPL_BUILD
+       struct rk3288_sdram_params *plat = dev_get_platdata(dev);
+#endif
        struct dram_info *priv = dev_get_priv(dev);
        struct regmap *map;
        int ret;
@@ -849,14 +879,12 @@ static int rk3288_dmc_probe(struct udevice *dev)
        priv->sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
        priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
 
-       ret = regmap_init_mem(dev, &map);
-       if (ret)
-               return ret;
-       priv->chan[0].pctl = regmap_get_range(map, 0);
-       priv->chan[0].publ = regmap_get_range(map, 1);
-       priv->chan[1].pctl = regmap_get_range(map, 2);
-       priv->chan[1].publ = regmap_get_range(map, 3);
-
+#ifdef CONFIG_SPL_BUILD
+       priv->chan[0].pctl = regmap_get_range(plat->map, 0);
+       priv->chan[0].publ = regmap_get_range(plat->map, 1);
+       priv->chan[1].pctl = regmap_get_range(plat->map, 2);
+       priv->chan[1].publ = regmap_get_range(plat->map, 3);
+#endif
        ret = uclass_get_device(UCLASS_CLK, 0, &dev_clk);
        if (ret)
                return ret;
@@ -902,6 +930,12 @@ U_BOOT_DRIVER(dmc_rk3288) = {
        .id = UCLASS_RAM,
        .of_match = rk3288_dmc_ids,
        .ops = &rk3288_dmc_ops,
+#ifdef CONFIG_SPL_BUILD
+       .ofdata_to_platdata = rk3288_dmc_ofdata_to_platdata,
+#endif
        .probe = rk3288_dmc_probe,
        .priv_auto_alloc_size = sizeof(struct dram_info),
+#ifdef CONFIG_SPL_BUILD
+       .platdata_auto_alloc_size = sizeof(struct rk3288_sdram_params),
+#endif
 };