#include <reset-uclass.h>
#include <regmap.h>
#include <linux/bitops.h>
+#include <linux/delay.h>
-#define REG_COUNT 8
#define BITS_PER_REG 32
-#define LEVEL_OFFSET 0x7c
+
+struct meson_reset_drvdata {
+ unsigned int reg_count;
+ unsigned int level_offset;
+};
struct meson_reset_priv {
struct regmap *regmap;
+ struct meson_reset_drvdata *drvdata;
};
static int meson_reset_request(struct reset_ctl *reset_ctl)
{
- if (reset_ctl->id > (REG_COUNT * BITS_PER_REG))
+ struct meson_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+ struct meson_reset_drvdata *data = priv->drvdata;
+
+ if (reset_ctl->id > (data->reg_count * BITS_PER_REG))
return -EINVAL;
return 0;
static int meson_reset_level(struct reset_ctl *reset_ctl, bool assert)
{
struct meson_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+ struct meson_reset_drvdata *data = priv->drvdata;
uint bank = reset_ctl->id / BITS_PER_REG;
uint offset = reset_ctl->id % BITS_PER_REG;
- uint reg_offset = LEVEL_OFFSET + (bank << 2);
+ uint reg_offset = data->level_offset + (bank << 2);
uint val;
regmap_read(priv->regmap, reg_offset, &val);
.rst_deassert = meson_reset_deassert,
};
+static const struct meson_reset_drvdata meson_gxbb_data = {
+ .reg_count = 8,
+ .level_offset = 0x7c,
+};
+
+static const struct meson_reset_drvdata meson_a1_data = {
+ .reg_count = 3,
+ .level_offset = 0x40,
+};
+
static const struct udevice_id meson_reset_ids[] = {
- { .compatible = "amlogic,meson-gxbb-reset" },
- { .compatible = "amlogic,meson-axg-reset" },
+ {
+ .compatible = "amlogic,meson-gxbb-reset",
+ .data = (ulong)&meson_gxbb_data,
+ },
+ {
+ .compatible = "amlogic,meson-axg-reset",
+ .data = (ulong)&meson_gxbb_data,
+ },
+ {
+ .compatible = "amlogic,meson-a1-reset",
+ .data = (ulong)&meson_a1_data,
+ },
{ }
};
static int meson_reset_probe(struct udevice *dev)
{
struct meson_reset_priv *priv = dev_get_priv(dev);
+ priv->drvdata = (struct meson_reset_drvdata *)dev_get_driver_data(dev);
return regmap_init_mem(dev_ofnode(dev), &priv->regmap);
}