aspeed: Device Tree configuration for Reset Driver

Add Reset Driver configuration to ast2500 SoC Device Tree and bindings
for various reset signals

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts
index dc13952fb85ea2678e0e01ea52a11818acd94f91..723941ac0beea72f8416833852c721a7b4161031 100644 (file)
--- a/arch/arm/dts/ast2500-evb.dts
+++ b/arch/arm/dts/ast2500-evb.dts
@@ -21,3 +21,18 @@
 &sdrammc {
        clock-frequency = <400000000>;
 };
+
+&wdt1 {
+       u-boot,dm-pre-reloc;
+       status = "okay";
+};
+
+&wdt2 {
+       u-boot,dm-pre-reloc;
+       status = "okay";
+};
+
+&wdt3 {
+       u-boot,dm-pre-reloc;
+       status = "okay";
+};

diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index c95a7ba835a0bbb17ea53891c2d2d3a9cd67c07c..faeeec1be4d2539143576af80275616df51c8e58 100644 (file)
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -1,4 +1,5 @@
 #include <dt-bindings/clock/ast2500-scu.h>
+#include <dt-bindings/reset/ast2500-reset.h>
 
 #include "ast2500.dtsi"
 
@@ -11,12 +12,21 @@
                #reset-cells = <1>;
        };
 
+       rst: reset-controller {
+               u-boot,dm-pre-reloc;
+               compatible = "aspeed,ast2500-reset";
+               aspeed,wdt = <&wdt1>;
+               #reset-cells = <1>;
+       };
+
        sdrammc: sdrammc@1e6e0000 {
                u-boot,dm-pre-reloc;
                compatible = "aspeed,ast2500-sdrammc";
                reg = <0x1e6e0000 0x174
                        0x1e6e0200 0x1d4 >;
+               #reset-cells = <1>;
                clocks = <&scu PLL_MPLL>;
+               resets = <&rst AST_RESET_SDRAM>;
        };
 
        ahb {

diff --git a/include/dt-bindings/reset/ast2500-reset.h b/include/dt-bindings/reset/ast2500-reset.h
new file mode 100644 (file)
index 0000000..eb5e1db
--- /dev/null
+++ b/include/dt-bindings/reset/ast2500-reset.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2017 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ABI_MACH_ASPEED_AST2500_RESET_H_
+#define _ABI_MACH_ASPEED_AST2500_RESET_H_
+
+/*
+ * The values are intentionally layed out as flags in
+ * WDT reset parameter.
+ */
+
+#define AST_RESET_SOC                  0
+#define AST_RESET_CHIP                 1
+#define AST_RESET_CPU                  (1 << 1)
+#define AST_RESET_ARM                  (1 << 2)
+#define AST_RESET_COPROC               (1 << 3)
+#define AST_RESET_SDRAM                        (1 << 4)
+#define AST_RESET_AHB                  (1 << 5)
+#define AST_RESET_I2C                  (1 << 6)
+#define AST_RESET_MAC1                 (1 << 7)
+#define AST_RESET_MAC2                 (1 << 8)
+#define AST_RESET_GCRT                 (1 << 9)
+#define AST_RESET_USB20                        (1 << 10)
+#define AST_RESET_USB11_HOST           (1 << 11)
+#define AST_RESET_USB11_HID            (1 << 12)
+#define AST_RESET_VIDEO                        (1 << 13)
+#define AST_RESET_HAC                  (1 << 14)
+#define AST_RESET_LPC                  (1 << 15)
+#define AST_RESET_SDIO                 (1 << 16)
+#define AST_RESET_MIC                  (1 << 17)
+#define AST_RESET_CRT2D                        (1 << 18)
+#define AST_RESET_PWM                  (1 << 19)
+#define AST_RESET_PECI                 (1 << 20)
+#define AST_RESET_JTAG                 (1 << 21)
+#define AST_RESET_ADC                  (1 << 22)
+#define AST_RESET_GPIO                 (1 << 23)
+#define AST_RESET_MCTP                 (1 << 24)
+#define AST_RESET_XDMA                 (1 << 25)
+#define AST_RESET_SPI                  (1 << 26)
+#define AST_RESET_MISC                 (1 << 27)
+
+#endif  /* _ABI_MACH_ASPEED_AST2500_RESET_H_ */