clk: clk-imx8qxp: Add LPUART IPG entries

Since commit cc7df0b9e8bc ("serial: lpuart: Enable IPG clock")
the colibri-imx8qxp board no longer boots.

The reason is that the imx8qxp clock driver does not handle the
LPUART IPG clocks inside get_rate(), set_rate() and enable() functions.

Fix the boot regression by adding the LPUART IPG entries.

Fixes: cc7df0b9e8bc ("serial: lpuart: Enable IPG clock")
Reported-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Hiago De Franco <hiago.franco@toradex.com> # Toradex Colibri iMX8X
Acked-by: Sean Anderson <seanga2@gmail.com>

diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
index 8bf7e32548133eaf4d8420c4f11f73f1b3b68446..d900d4cd528642f1508050bb7d0deb27a3a82987 100644 (file)
--- a/drivers/clk/imx/clk-imx8qxp.c
+++ b/drivers/clk/imx/clk-imx8qxp.c
@@ -88,20 +88,23 @@ ulong imx8_clk_get_rate(struct clk *clk)
                resource = SC_R_SDHC_1;
                pm_clk = SC_PM_CLK_PER;
                break;
-       case IMX8QXP_UART0_IPG_CLK:
        case IMX8QXP_UART0_CLK:
+       case IMX8QXP_UART0_IPG_CLK:
                resource = SC_R_UART_0;
                pm_clk = SC_PM_CLK_PER;
                break;
        case IMX8QXP_UART1_CLK:
+       case IMX8QXP_UART1_IPG_CLK:
                resource = SC_R_UART_1;
                pm_clk = SC_PM_CLK_PER;
                break;
        case IMX8QXP_UART2_CLK:
+       case IMX8QXP_UART2_IPG_CLK:
                resource = SC_R_UART_2;
                pm_clk = SC_PM_CLK_PER;
                break;
        case IMX8QXP_UART3_CLK:
+       case IMX8QXP_UART3_IPG_CLK:
                resource = SC_R_UART_3;
                pm_clk = SC_PM_CLK_PER;
                break;
@@ -170,18 +173,22 @@ ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate)
                pm_clk = SC_PM_CLK_PER;
                break;
        case IMX8QXP_UART0_CLK:
+       case IMX8QXP_UART0_IPG_CLK:
                resource = SC_R_UART_0;
                pm_clk = SC_PM_CLK_PER;
                break;
        case IMX8QXP_UART1_CLK:
+       case IMX8QXP_UART1_IPG_CLK:
                resource = SC_R_UART_1;
                pm_clk = SC_PM_CLK_PER;
                break;
        case IMX8QXP_UART2_CLK:
+       case IMX8QXP_UART2_IPG_CLK:
                resource = SC_R_UART_2;
                pm_clk = SC_PM_CLK_PER;
                break;
        case IMX8QXP_UART3_CLK:
+       case IMX8QXP_UART3_IPG_CLK:
                resource = SC_R_UART_3;
                pm_clk = SC_PM_CLK_PER;
                break;
@@ -263,18 +270,22 @@ int __imx8_clk_enable(struct clk *clk, bool enable)
                pm_clk = SC_PM_CLK_PER;
                break;
        case IMX8QXP_UART0_CLK:
+       case IMX8QXP_UART0_IPG_CLK:
                resource = SC_R_UART_0;
                pm_clk = SC_PM_CLK_PER;
                break;
        case IMX8QXP_UART1_CLK:
+       case IMX8QXP_UART1_IPG_CLK:
                resource = SC_R_UART_1;
                pm_clk = SC_PM_CLK_PER;
                break;
        case IMX8QXP_UART2_CLK:
+       case IMX8QXP_UART2_IPG_CLK:
                resource = SC_R_UART_2;
                pm_clk = SC_PM_CLK_PER;
                break;
        case IMX8QXP_UART3_CLK:
+       case IMX8QXP_UART3_IPG_CLK:
                resource = SC_R_UART_3;
                pm_clk = SC_PM_CLK_PER;
                break;