};
/* Information about a GPIO bank */
-struct hikey_gpio_platdata {
+struct hikey_gpio_plat {
int bank_index;
ulong base; /* address of registers in physical memory */
};
#include <asm/arch/sci/types.h>
-struct imx8_power_domain_platdata {
+struct imx8_power_domain_plat {
sc_rsrc_t resource_id;
};
#ifndef _ASM_ARCH_IMX8M_POWER_DOMAIN_H
#define _ASM_ARCH_IMX8M_POWER_DOMAIN_H
-struct imx8m_power_domain_platdata {
+struct imx8m_power_domain_plat {
int resource_id;
int has_pd;
struct power_domain pd;
u32 gpio_pdir;
};
-struct vybrid_gpio_platdata {
+struct vybrid_gpio_plat {
unsigned int chip;
u32 base;
const char *port_name;
#if CONFIG_IS_ENABLED(DM_GPIO)
/* Information about a GPIO bank */
-struct omap_gpio_platdata {
+struct omap_gpio_plat {
int bank_index;
ulong base; /* address of registers in physical memory */
const char *port_name;
#ifdef CONFIG_DM_I2C
/* Information about a GPIO bank */
-struct omap_i2c_platdata {
+struct omap_i2c_plat {
ulong base; /* address of registers in physical memory */
int speed;
int ip_rev;
enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
-struct ti_musb_platdata {
+struct ti_musb_plat {
void *base;
void *ctrl_mod_base;
struct musb_hdrc_platform_data plat;
}
/* Platform data for the GPIOs */
-static const struct at91_port_platdata at91sam9260_plat[] = {
+static const struct at91_port_plat at91sam9260_plat[] = {
{ ATMEL_BASE_PIOA, "PA" },
{ ATMEL_BASE_PIOB, "PB" },
{ ATMEL_BASE_PIOC, "PC" },
#endif
/* Platform data for the GPIOs */
-static const struct at91_port_platdata at91sam9260_plat[] = {
+static const struct at91_port_plat at91sam9260_plat[] = {
{ ATMEL_BASE_PIOA, "PA" },
{ ATMEL_BASE_PIOB, "PB" },
{ ATMEL_BASE_PIOC, "PC" },
#define _ATMEL_SERIAL_H
/* Information about a serial port */
-struct atmel_serial_platdata {
+struct atmel_serial_plat {
uint32_t base_addr;
};
}
/* Platform data for each GPIO port */
-struct at91_port_platdata {
+struct at91_port_plat {
uint32_t base_addr;
const char *bank_name;
};
};
/**
- * struct bcm2835_gpio_platdata - GPIO platform description
+ * struct bcm2835_gpio_plat - GPIO platform description
*
* @base: Base address of GPIO controller
*/
-struct bcm2835_gpio_platdata {
+struct bcm2835_gpio_plat {
unsigned long base;
};
}
#if !CONFIG_IS_ENABLED(OF_CONTROL)
-static const struct ns16550_platdata lpc32xx_uart[] = {
+static const struct ns16550_plat lpc32xx_uart[] = {
{ .base = UART3_BASE, .reg_shift = 2,
.clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
{ .base = UART4_BASE, .reg_shift = 2,
};
#if defined(CONFIG_LPC32XX_HSUART)
-static const struct lpc32xx_hsuart_platdata lpc32xx_hsuart[] = {
+static const struct lpc32xx_hsuart_plat lpc32xx_hsuart[] = {
{ HS_UART1_BASE, },
{ HS_UART2_BASE, },
{ HS_UART7_BASE, },
};
/* platform data for the driver model */
-struct nx_display_platdata {
+struct nx_display_plat {
int module;
struct dp_sync_info sync;
struct dp_ctrl_info ctrl;
#if defined CONFIG_SPL_BUILD || \
(!defined(CONFIG_DM) && !defined(CONFIG_OF_CONTROL))
-int nx_display_probe(struct nx_display_platdata *plat);
+int nx_display_probe(struct nx_display_plat *plat);
#endif
#endif
}
#if !CONFIG_IS_ENABLED(OF_CONTROL)
-static const struct ns16550_platdata am33xx_serial[] = {
+static const struct ns16550_plat am33xx_serial[] = {
{ .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2,
.clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
# ifdef CONFIG_SYS_NS16550_COM2
};
#ifdef CONFIG_DM_I2C
-static const struct omap_i2c_platdata am33xx_i2c[] = {
+static const struct omap_i2c_plat am33xx_i2c[] = {
{ I2C_BASE1, 100000, OMAP_I2C_REV_V2},
{ I2C_BASE2, 100000, OMAP_I2C_REV_V2},
{ I2C_BASE3, 100000, OMAP_I2C_REV_V2},
#endif
#if CONFIG_IS_ENABLED(DM_GPIO)
-static const struct omap_gpio_platdata am33xx_gpio[] = {
+static const struct omap_gpio_plat am33xx_gpio[] = {
{ 0, AM33XX_GPIO0_BASE },
{ 1, AM33XX_GPIO1_BASE },
{ 2, AM33XX_GPIO2_BASE },
};
#if CONFIG_IS_ENABLED(DM_USB) && !CONFIG_IS_ENABLED(OF_CONTROL)
-static struct ti_musb_platdata usb0 = {
+static struct ti_musb_plat usb0 = {
.base = (void *)USB0_OTG_BASE,
.ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl0,
.plat = {
},
};
-static struct ti_musb_platdata usb1 = {
+static struct ti_musb_plat usb1 = {
.base = (void *)USB1_OTG_BASE,
.ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl1,
.plat = {
#if CONFIG_IS_ENABLED(DM_GPIO)
#if !CONFIG_IS_ENABLED(OF_CONTROL)
/* Manually initialize GPIO banks when OF_CONTROL doesn't */
-static const struct omap_gpio_platdata omap34xx_gpio[] = {
+static const struct omap_gpio_plat omap34xx_gpio[] = {
{ 0, OMAP34XX_GPIO1_BASE },
{ 1, OMAP34XX_GPIO2_BASE },
{ 2, OMAP34XX_GPIO3_BASE },
};
#if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int px30_syscon_bind_of_platdata(struct udevice *dev)
+static int px30_syscon_bind_of_plat(struct udevice *dev)
{
dev->driver_data = dev->driver->of_match->data;
debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
.name = "rockchip_px30_pmu",
.id = UCLASS_SYSCON,
.of_match = px30_syscon_ids,
- .bind = px30_syscon_bind_of_platdata,
+ .bind = px30_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_px30_pmugrf) = {
.name = "rockchip_px30_pmugrf",
.id = UCLASS_SYSCON,
.of_match = px30_syscon_ids + 1,
- .bind = px30_syscon_bind_of_platdata,
+ .bind = px30_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_px30_grf) = {
.name = "rockchip_px30_grf",
.id = UCLASS_SYSCON,
.of_match = px30_syscon_ids + 2,
- .bind = px30_syscon_bind_of_platdata,
+ .bind = px30_syscon_bind_of_plat,
};
#endif
};
#if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int rk3188_syscon_bind_of_platdata(struct udevice *dev)
+static int rk3188_syscon_bind_of_plat(struct udevice *dev)
{
dev->driver_data = dev->driver->of_match->data;
debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
.name = "rockchip_rk3188_noc",
.id = UCLASS_SYSCON,
.of_match = rk3188_syscon_ids,
- .bind = rk3188_syscon_bind_of_platdata,
+ .bind = rk3188_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3188_grf) = {
.name = "rockchip_rk3188_grf",
.id = UCLASS_SYSCON,
.of_match = rk3188_syscon_ids + 1,
- .bind = rk3188_syscon_bind_of_platdata,
+ .bind = rk3188_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3188_pmu) = {
.name = "rockchip_rk3188_pmu",
.id = UCLASS_SYSCON,
.of_match = rk3188_syscon_ids + 2,
- .bind = rk3188_syscon_bind_of_platdata,
+ .bind = rk3188_syscon_bind_of_plat,
};
#endif
};
#if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int rk3288_syscon_bind_of_platdata(struct udevice *dev)
+static int rk3288_syscon_bind_of_plat(struct udevice *dev)
{
dev->driver_data = dev->driver->of_match->data;
debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
.name = "rockchip_rk3288_noc",
.id = UCLASS_SYSCON,
.of_match = rk3288_syscon_ids,
- .bind = rk3288_syscon_bind_of_platdata,
+ .bind = rk3288_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3288_grf) = {
.name = "rockchip_rk3288_grf",
.id = UCLASS_SYSCON,
.of_match = rk3288_syscon_ids + 1,
- .bind = rk3288_syscon_bind_of_platdata,
+ .bind = rk3288_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3288_sgrf) = {
.name = "rockchip_rk3288_sgrf",
.id = UCLASS_SYSCON,
.of_match = rk3288_syscon_ids + 2,
- .bind = rk3288_syscon_bind_of_platdata,
+ .bind = rk3288_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3288_pmu) = {
.name = "rockchip_rk3288_pmu",
.id = UCLASS_SYSCON,
.of_match = rk3288_syscon_ids + 3,
- .bind = rk3288_syscon_bind_of_platdata,
+ .bind = rk3288_syscon_bind_of_plat,
};
#endif
};
#if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int rk3368_syscon_bind_of_platdata(struct udevice *dev)
+static int rk3368_syscon_bind_of_plat(struct udevice *dev)
{
dev->driver_data = dev->driver->of_match->data;
debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
.name = "rockchip_rk3368_grf",
.id = UCLASS_SYSCON,
.of_match = rk3368_syscon_ids,
- .bind = rk3368_syscon_bind_of_platdata,
+ .bind = rk3368_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3368_pmugrf) = {
.name = "rockchip_rk3368_pmugrf",
.id = UCLASS_SYSCON,
.of_match = rk3368_syscon_ids + 1,
- .bind = rk3368_syscon_bind_of_platdata,
+ .bind = rk3368_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3368_msch) = {
.name = "rockchip_rk3368_msch",
.id = UCLASS_SYSCON,
.of_match = rk3368_syscon_ids + 2,
- .bind = rk3368_syscon_bind_of_platdata,
+ .bind = rk3368_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3368_sgrf) = {
.name = "rockchip_rk3368_sgrf",
.id = UCLASS_SYSCON,
.of_match = rk3368_syscon_ids + 3,
- .bind = rk3368_syscon_bind_of_platdata,
+ .bind = rk3368_syscon_bind_of_plat,
};
#endif
};
#if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int rk3399_syscon_bind_of_platdata(struct udevice *dev)
+static int rk3399_syscon_bind_of_plat(struct udevice *dev)
{
dev->driver_data = dev->driver->of_match->data;
debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
.name = "rockchip_rk3399_grf",
.id = UCLASS_SYSCON,
.of_match = rk3399_syscon_ids,
- .bind = rk3399_syscon_bind_of_platdata,
+ .bind = rk3399_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3399_pmugrf) = {
.name = "rockchip_rk3399_pmugrf",
.id = UCLASS_SYSCON,
.of_match = rk3399_syscon_ids + 1,
- .bind = rk3399_syscon_bind_of_platdata,
+ .bind = rk3399_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3399_pmusgrf) = {
.name = "rockchip_rk3399_pmusgrf",
.id = UCLASS_SYSCON,
.of_match = rk3399_syscon_ids + 2,
- .bind = rk3399_syscon_bind_of_platdata,
+ .bind = rk3399_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3399_cic) = {
.name = "rockchip_rk3399_cic",
.id = UCLASS_SYSCON,
.of_match = rk3399_syscon_ids + 3,
- .bind = rk3399_syscon_bind_of_platdata,
+ .bind = rk3399_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3399_pmu) = {
.name = "rockchip_rk3399_pmu",
.id = UCLASS_SYSCON,
.of_match = rk3399_syscon_ids + 4,
- .bind = rk3399_syscon_bind_of_platdata,
+ .bind = rk3399_syscon_bind_of_plat,
};
#endif
}
/* BSEC MISC driver *******************************************************/
-struct stm32mp_bsec_platdata {
+struct stm32mp_bsec_plat {
u32 base;
};
static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp)
{
- struct stm32mp_bsec_platdata *plat;
+ struct stm32mp_bsec_plat *plat;
u32 tmp_data = 0;
int ret;
static int stm32mp_bsec_read_shadow(struct udevice *dev, u32 *val, u32 otp)
{
- struct stm32mp_bsec_platdata *plat;
+ struct stm32mp_bsec_plat *plat;
if (IS_ENABLED(CONFIG_TFABOOT))
return stm32_smc(STM32_SMC_BSEC,
static int stm32mp_bsec_read_lock(struct udevice *dev, u32 *val, u32 otp)
{
- struct stm32mp_bsec_platdata *plat = dev_get_plat(dev);
+ struct stm32mp_bsec_plat *plat = dev_get_plat(dev);
/* return OTP permanent write lock status */
*val = bsec_read_lock(plat->base + BSEC_WRLOCK_OFF, otp);
static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp)
{
- struct stm32mp_bsec_platdata *plat;
+ struct stm32mp_bsec_plat *plat;
if (IS_ENABLED(CONFIG_TFABOOT))
return stm32_smc_exec(STM32_SMC_BSEC,
static int stm32mp_bsec_write_shadow(struct udevice *dev, u32 val, u32 otp)
{
- struct stm32mp_bsec_platdata *plat;
+ struct stm32mp_bsec_plat *plat;
if (IS_ENABLED(CONFIG_TFABOOT))
return stm32_smc_exec(STM32_SMC_BSEC,
static int stm32mp_bsec_of_to_plat(struct udevice *dev)
{
- struct stm32mp_bsec_platdata *plat = dev_get_plat(dev);
+ struct stm32mp_bsec_plat *plat = dev_get_plat(dev);
plat->base = (u32)dev_read_addr_ptr(dev);
static int stm32mp_bsec_probe(struct udevice *dev)
{
int otp;
- struct stm32mp_bsec_platdata *plat;
+ struct stm32mp_bsec_plat *plat;
/*
* update unlocked shadow for OTP cleared by the rom code
.id = UCLASS_MISC,
.of_match = stm32mp_bsec_ids,
.of_to_plat = stm32mp_bsec_of_to_plat,
- .plat_auto = sizeof(struct stm32mp_bsec_platdata),
+ .plat_auto = sizeof(struct stm32mp_bsec_plat),
.ops = &stm32mp_bsec_ops,
.probe = stm32mp_bsec_probe,
};
bool bsec_dbgswenable(void)
{
struct udevice *dev;
- struct stm32mp_bsec_platdata *plat;
+ struct stm32mp_bsec_plat *plat;
int ret;
ret = uclass_get_device_by_driver(UCLASS_MISC,
}
#if !CONFIG_IS_ENABLED(OF_CONTROL)
-static struct ns16550_platdata ns16550_com1_pdata = {
+static struct ns16550_plat ns16550_com1_pdata = {
.base = CONFIG_SYS_NS16550_COM1,
.reg_shift = 2,
.clock = CONFIG_SYS_NS16550_CLK,
};
/* Details about a GPIO bank */
-struct sifive_gpio_platdata {
+struct sifive_gpio_plat {
void *base; /* address of registers in physical memory */
};
};
/* Details about a GPIO bank */
-struct sifive_gpio_platdata {
+struct sifive_gpio_plat {
void *base; /* address of registers in physical memory */
};
};
/**
- * struct apl_hostbridge_platdata - platform data for hostbridge
+ * struct apl_hostbridge_plat - platform data for hostbridge
*
* @dtplat: Platform data for of-platdata
* @early_pads: Early pad data to set up, each (pad, cfg0, cfg1)
* @pciex_region_size: BAR length in bytes
* @bdf: Bus/device/function of hostbridge
*/
-struct apl_hostbridge_platdata {
+struct apl_hostbridge_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_intel_apl_hostbridge dtplat;
#endif
static int apl_hostbridge_early_init_pinctrl(struct udevice *dev)
{
- struct apl_hostbridge_platdata *plat = dev_get_plat(dev);
+ struct apl_hostbridge_plat *plat = dev_get_plat(dev);
struct udevice *pinctrl;
int ret;
static int apl_hostbridge_early_init(struct udevice *dev)
{
- struct apl_hostbridge_platdata *plat = dev_get_plat(dev);
+ struct apl_hostbridge_plat *plat = dev_get_plat(dev);
u32 region_size;
ulong base;
u32 reg;
static int apl_hostbridge_of_to_plat(struct udevice *dev)
{
- struct apl_hostbridge_platdata *plat = dev_get_plat(dev);
+ struct apl_hostbridge_plat *plat = dev_get_plat(dev);
struct udevice *pinctrl;
int ret;
.of_to_plat = apl_hostbridge_of_to_plat,
.probe = apl_hostbridge_probe,
.remove = apl_hostbridge_remove,
- .plat_auto = sizeof(struct apl_hostbridge_platdata),
+ .plat_auto = sizeof(struct apl_hostbridge_plat),
ACPI_OPS_PTR(&apl_hostbridge_acpi_ops)
.flags = DM_FLAG_OS_PREPARE,
};
CF9_GLB_RST = 1 << 20,
};
-struct apl_pmc_platdata {
+struct apl_pmc_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_intel_apl_pmc dtplat;
#endif
return 0;
}
-int apl_pmc_ofdata_to_uc_platdata(struct udevice *dev)
+int apl_pmc_ofdata_to_uc_plat(struct udevice *dev)
{
struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
- struct apl_pmc_platdata *plat = dev_get_plat(dev);
+ struct apl_pmc_plat *plat = dev_get_plat(dev);
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
u32 base[6];
if (ret)
return log_msg_ret("Bad gpe0-dw", ret);
- return pmc_ofdata_to_uc_platdata(dev);
+ return pmc_ofdata_to_uc_plat(dev);
#else
struct dtd_intel_apl_pmc *dtplat = &plat->dtplat;
static int enable_pmcbar(struct udevice *dev)
{
struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
- struct apl_pmc_platdata *priv = dev_get_plat(dev);
+ struct apl_pmc_plat *priv = dev_get_plat(dev);
pci_dev_t pmc = priv->bdf;
/*
.name = "intel_apl_pmc",
.id = UCLASS_ACPI_PMC,
.of_match = apl_pmc_ids,
- .of_to_plat = apl_pmc_ofdata_to_uc_platdata,
+ .of_to_plat = apl_pmc_ofdata_to_uc_plat,
.probe = apl_pmc_probe,
.ops = &apl_pmc_ops,
- .plat_auto = sizeof(struct apl_pmc_platdata),
+ .plat_auto = sizeof(struct apl_pmc_plat),
};
{
if (CONFIG_IS_ENABLED(OF_PLATDATA) &&
!CONFIG_IS_ENABLED(OF_PLATDATA_PARENT)) {
- struct dm_spi_slave_platdata *plat;
+ struct dm_spi_slave_plat *plat;
struct udevice *spi;
int ret;
* This driver uses its own compatible string but almost everything else from
* the standard ns16550 driver. This allows us to provide an of-platdata
* implementation, since the platdata produced by of-platdata does not match
- * struct ns16550_platdata.
+ * struct ns16550_plat.
*
* When running with of-platdata (generally TPL), the platdata is converted to
* something that ns16550 expects. When running withoutof-platdata (SPL, U-Boot
static int apl_ns16550_probe(struct udevice *dev)
{
- struct ns16550_platdata *plat = dev_get_plat(dev);
+ struct ns16550_plat *plat = dev_get_plat(dev);
if (!CONFIG_IS_ENABLED(PCI))
apl_uart_init(plat->bdf, plat->base);
{
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_intel_apl_ns16550 *dtplat = dev_get_plat(dev);
- struct ns16550_platdata *plat;
+ struct ns16550_plat *plat;
/*
* Convert our plat to the ns16550's plat, so we can just use
.name = "intel_apl_ns16550",
.id = UCLASS_SERIAL,
.of_match = apl_ns16550_serial_ids,
- .plat_auto = sizeof(struct ns16550_platdata),
+ .plat_auto = sizeof(struct ns16550_plat),
.priv_auto = sizeof(struct NS16550),
.ops = &ns16550_serial_ops,
.of_to_plat = apl_ns16550_of_to_plat,
#include <asm/arch/pch.h>
#include <linux/delay.h>
-struct sata_platdata {
+struct sata_plat {
int port_map;
uint port0_gen3_tx;
uint port1_gen3_tx;
static void broadwell_sata_init(struct udevice *dev)
{
- struct sata_platdata *plat = dev_get_plat(dev);
+ struct sata_plat *plat = dev_get_plat(dev);
u32 reg32;
u8 *abar;
u16 reg16;
static int broadwell_sata_enable(struct udevice *dev)
{
- struct sata_platdata *plat = dev_get_plat(dev);
+ struct sata_plat *plat = dev_get_plat(dev);
struct gpio_desc desc;
u16 map;
int ret;
static int broadwell_sata_of_to_plat(struct udevice *dev)
{
- struct sata_platdata *plat = dev_get_plat(dev);
+ struct sata_plat *plat = dev_get_plat(dev);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
.of_match = broadwell_ahci_ids,
.of_to_plat = broadwell_sata_of_to_plat,
.probe = broadwell_sata_probe,
- .plat_auto = sizeof(struct sata_platdata),
+ .plat_auto = sizeof(struct sata_plat),
};
int cpu_x86_bind(struct udevice *dev)
{
- struct cpu_platdata *plat = dev_get_parent_plat(dev);
+ struct cpu_plat *plat = dev_get_parent_plat(dev);
struct cpuid_result res;
plat->cpu_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
#include <spl.h>
#include <asm/itss.h>
-struct itss_platdata {
+struct itss_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
/* Put this first since driver model will copy the data here */
struct dtd_intel_itss dtplat;
int ret;
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- struct itss_platdata *plat = dev_get_plat(dev);
+ struct itss_plat *plat = dev_get_plat(dev);
struct dtd_intel_itss *dtplat = &plat->dtplat;
/*
.ops = &itss_ops,
.bind = itss_bind,
.of_to_plat = itss_of_to_plat,
- .plat_auto = sizeof(struct itss_platdata),
+ .plat_auto = sizeof(struct itss_plat),
.priv_auto = sizeof(struct itss_priv),
};
#define PCH_P2SB_E0 0xe0
#define HIDE_BIT BIT(0)
-struct p2sb_platdata {
+struct p2sb_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_intel_p2sb dtplat;
#endif
*/
static int p2sb_early_init(struct udevice *dev)
{
- struct p2sb_platdata *plat = dev_get_plat(dev);
+ struct p2sb_plat *plat = dev_get_plat(dev);
pci_dev_t pdev = plat->bdf;
/*
int p2sb_of_to_plat(struct udevice *dev)
{
struct p2sb_uc_priv *upriv = dev_get_uclass_priv(dev);
- struct p2sb_platdata *plat = dev_get_plat(dev);
+ struct p2sb_plat *plat = dev_get_plat(dev);
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
int ret;
static int p2sb_child_post_bind(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- struct p2sb_child_platdata *pplat = dev_get_parent_plat(dev);
+ struct p2sb_child_plat *pplat = dev_get_parent_plat(dev);
int ret;
u32 pid;
.remove = p2sb_remove,
.ops = &p2sb_ops,
.of_to_plat = p2sb_of_to_plat,
- .plat_auto = sizeof(struct p2sb_platdata),
- .per_child_plat_auto = sizeof(struct p2sb_child_platdata),
+ .plat_auto = sizeof(struct p2sb_plat),
+ .per_child_plat_auto = sizeof(struct p2sb_child_plat),
.child_post_bind = p2sb_child_post_bind,
.flags = DM_FLAG_OS_PREPARE,
};
for (uclass_find_first_device(UCLASS_CPU, &dev);
dev;
uclass_find_next_device(&dev)) {
- struct cpu_platdata *plat = dev_get_parent_plat(dev);
+ struct cpu_plat *plat = dev_get_parent_plat(dev);
if (plat->cpu_id == apic_id) {
*devp = dev;
static int mp_init_cpu(struct udevice *cpu, void *unused)
{
- struct cpu_platdata *plat = dev_get_parent_plat(cpu);
+ struct cpu_plat *plat = dev_get_parent_plat(cpu);
plat->ucode_version = microcode_read_rev();
plat->device_id = gd->arch.x86_device;
int cpu_num;
int cpu_online;
struct udevice *dev, *pdev;
- struct cpu_platdata *plat;
+ struct cpu_plat *plat;
char *cpu;
/* first we need to find '/cpus' */
{
const efi_guid_t guid = SBL_SERIAL_PORT_INFO_GUID;
struct sbl_serial_port_info *data;
- struct ns16550_platdata *plat = dev->plat;
+ struct ns16550_plat *plat = dev->plat;
if (!gd->arch.hob_list)
panic("hob list not found!");
.id = UCLASS_SERIAL,
.of_match = slimbootloader_serial_ids,
.of_to_plat = slimbootloader_serial_of_to_plat,
- .plat_auto = sizeof(struct ns16550_platdata),
+ .plat_auto = sizeof(struct ns16550_plat),
.priv_auto = sizeof(struct NS16550),
.probe = ns16550_serial_probe,
.ops = &ns16550_serial_ops,
#define GPIO_PER_BANK 32
#define GPIO_BANKS 3
-struct broadwell_bank_platdata {
+struct broadwell_bank_plat {
uint16_t base_addr;
const char *bank_name;
int bank;
#include <asm-generic/gpio.h>
-struct ich6_bank_platdata {
+struct ich6_bank_plat {
uint16_t base_addr;
const char *bank_name;
int offset;
for (uclass_find_first_device(UCLASS_CPU, &dev);
dev;
uclass_find_next_device(&dev)) {
- struct cpu_platdata *plat = dev_get_parent_plat(dev);
+ struct cpu_plat *plat = dev_get_parent_plat(dev);
int length;
length = acpi_create_madt_lapic(
static int fsp_video_probe(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct vesa_mode_info *vesa = &mode_info.vesa;
int ret;
static int fsp_video_bind(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
/* Set the maximum supported resolution */
plat->size = 2560 * 1600 * 4;
for (uclass_find_first_device(UCLASS_CPU, &dev);
dev;
uclass_find_next_device(&dev)) {
- struct cpu_platdata *plat = dev_get_parent_plat(dev);
+ struct cpu_plat *plat = dev_get_parent_plat(dev);
u8 cpuflag = MPC_CPU_EN;
if (!device_active(dev))
for (uclass_find_first_device(UCLASS_CPU, &dev);
dev;
uclass_find_next_device(&dev)) {
- struct cpu_platdata *plat = dev_get_parent_plat(dev);
+ struct cpu_plat *plat = dev_get_parent_plat(dev);
if (!device_active(dev))
continue;
DECLARE_GLOBAL_DATA_PTR;
-static const struct pl01x_serial_platdata serial_platdata = {
+static const struct pl01x_serial_plat serial_plat = {
.base = 0x16000000,
#ifdef CONFIG_ARCH_CINTEGRATOR
.type = TYPE_PL011,
U_BOOT_DEVICE(integrator_serials) = {
.name = "serial_pl01x",
- .plat = &serial_platdata,
+ .plat = &serial_plat,
};
void peripheral_power_enable (void);
#include <dm/platform_data/serial_pl01x.h>
#include <asm/armv8/mmu.h>
-static const struct pl01x_serial_platdata serial_platdata = {
+static const struct pl01x_serial_plat serial_plat = {
.base = UART0_BASE,
.type = TYPE_PL011,
.clock = CONFIG_PL011_CLOCK,
U_BOOT_DEVICE(total_compute_serials) = {
.name = "serial_pl01x",
- .plat = &serial_platdata,
+ .plat = &serial_plat,
};
static struct mm_region total_compute_mem_map[] = {
DECLARE_GLOBAL_DATA_PTR;
-static const struct pl01x_serial_platdata serial_platdata = {
+static const struct pl01x_serial_plat serial_plat = {
.base = V2M_UART0,
.type = TYPE_PL011,
.clock = CONFIG_PL011_CLOCK,
U_BOOT_DEVICE(vexpress_serials) = {
.name = "serial_pl01x",
- .plat = &serial_platdata,
+ .plat = &serial_plat,
};
static struct mm_region vexpress64_mem_map[] = {
uclass_find_first_device(UCLASS_VIDEO, &dev);
if (dev) {
- struct atmel_lcd_platdata *plat = dev_get_plat(dev);
+ struct atmel_lcd_plat *plat = dev_get_plat(dev);
plat->timing_index = 1;
}
{
}
-static struct atmel_serial_platdata at91sam9260_serial_plat = {
+static struct atmel_serial_plat at91sam9260_serial_plat = {
.base_addr = ATMEL_BASE_DBGU,
};
{
}
-static struct atmel_serial_platdata at91sam9260_serial_plat = {
+static struct atmel_serial_plat at91sam9260_serial_plat = {
.base_addr = ATMEL_BASE_DBGU,
};
#if !CONFIG_IS_ENABLED(OF_CONTROL)
#include <dm/platform_data/serial_pl01x.h>
-static const struct pl01x_serial_platdata serial0 = {
+static const struct pl01x_serial_plat serial0 = {
.base = CONFIG_SYS_SERIAL0,
.type = TYPE_PL011,
.clock = 0,
.plat = &serial0,
};
-static const struct pl01x_serial_platdata serial1 = {
+static const struct pl01x_serial_plat serial1 = {
.base = CONFIG_SYS_SERIAL1,
.type = TYPE_PL011,
.clock = 0,
return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS);
}
-static struct mxc_serial_platdata cm_fx6_mxc_serial_plat = {
+static struct mxc_serial_plat cm_fx6_mxc_serial_plat = {
.reg = (struct mxc_uart *)UART4_BASE,
};
#endif
#ifdef CONFIG_SPL_BUILD
-static const struct ns16550_platdata serial_pdata = {
+static const struct ns16550_plat serial_pdata = {
.base = DAVINCI_UART2_BASE,
.reg_shift = 2,
.clock = 228000000,
.plat = &serial_pdata,
};
-static const struct davinci_mmc_plat mmc_platdata = {
+static const struct davinci_mmc_plat mmc_plat = {
.reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
.cfg = {
.f_min = 200000,
};
U_BOOT_DEVICE(omapl138_mmc) = {
.name = "ti_da830_mmc",
- .plat = &mmc_platdata,
+ .plat = &mmc_plat,
};
void spl_board_init(void)
DECLARE_GLOBAL_DATA_PTR;
-static struct pl01x_serial_platdata serial0 = {
+static struct pl01x_serial_plat serial0 = {
#if CONFIG_CONS_INDEX == 0
.base = CONFIG_SYS_SERIAL0,
#elif CONFIG_CONS_INDEX == 1
.plat = &serial0,
};
-static struct pl01x_serial_platdata serial1 = {
+static struct pl01x_serial_plat serial1 = {
.base = CONFIG_SYS_SERIAL1,
.type = TYPE_PL011,
};
}
#endif /* CONFIG_OF_BOARD_SETUP */
-static struct mxc_serial_platdata ventana_mxc_serial_plat = {
+static struct mxc_serial_plat ventana_mxc_serial_plat = {
.reg = (struct mxc_uart *)UART2_BASE,
};
#include <asm/armv8/mmu.h>
/*TODO drop this table in favour of device tree */
-static const struct hikey_gpio_platdata hi6220_gpio[] = {
+static const struct hikey_gpio_plat hi6220_gpio[] = {
{ 0, HI6220_GPIO_BASE(0)},
{ 1, HI6220_GPIO_BASE(1)},
{ 2, HI6220_GPIO_BASE(2)},
#if !CONFIG_IS_ENABLED(OF_CONTROL)
-static const struct pl01x_serial_platdata serial_platdata = {
+static const struct pl01x_serial_plat serial_plat = {
#if CONFIG_CONS_INDEX == 1
.base = HI6220_UART0_BASE,
#elif CONFIG_CONS_INDEX == 4
U_BOOT_DEVICE(hikey_seriala) = {
.name = "serial_pl01x",
- .plat = &serial_platdata,
+ .plat = &serial_plat,
};
#endif
#if !CONFIG_IS_ENABLED(OF_CONTROL)
#include <dm/platform_data/serial_pl01x.h>
-static const struct pl01x_serial_platdata serial_platdata = {
+static const struct pl01x_serial_plat serial_plat = {
.base = HI3660_UART6_BASE,
.type = TYPE_PL011,
.clock = 19200000
U_BOOT_DEVICE(hikey960_serial0) = {
.name = "serial_pl01x",
- .plat = &serial_platdata,
+ .plat = &serial_plat,
};
#endif
struct mm_region *mem_map = poplar_mem_map;
#if !CONFIG_IS_ENABLED(OF_CONTROL)
-static const struct pl01x_serial_platdata serial_platdata = {
+static const struct pl01x_serial_plat serial_plat = {
.base = REG_BASE_UART0,
.type = TYPE_PL010,
.clock = 75000000,
U_BOOT_DEVICE(poplar_serial) = {
.name = "serial_pl01x",
- .plat = &serial_platdata,
+ .plat = &serial_plat,
};
#endif
#include <fdt_support.h>
#include "igep00x0.h"
-static const struct ns16550_platdata igep_serial = {
+static const struct ns16550_plat igep_serial = {
.base = OMAP34XX_UART3,
.reg_shift = 2,
.clock = V_NS16550_CLK,
.nand_string = "MMC"
};
-static const struct ns16550_platdata serial_omap_platdata = {
+static const struct ns16550_plat serial_omap_plat = {
.base = OMAP34XX_UART3,
.reg_shift = 2,
.clock = V_NS16550_CLK,
U_BOOT_DEVICE(sniper_serial) = {
.name = "ns16550_serial",
- .plat = &serial_omap_platdata
+ .plat = &serial_omap_plat
};
static struct musb_hdrc_config musb_config = {
twl4030_power_mmc_init(1);
}
-static const struct omap_i2c_platdata rx51_i2c[] = {
+static const struct omap_i2c_plat rx51_i2c[] = {
{ I2C_BASE1, 2200000, OMAP_I2C_REV_V1 },
{ I2C_BASE2, 100000, OMAP_I2C_REV_V1 },
{ I2C_BASE3, 400000, OMAP_I2C_REV_V1 },
}
}
-static struct atmel_serial_platdata at91sam9260_serial_plat = {
+static struct atmel_serial_plat at91sam9260_serial_plat = {
.base_addr = ATMEL_BASE_DBGU,
};
(struct gpio_regs *) GPIOA_BASE_ADDR;
#ifndef CONFIG_OF_CONTROL
-static const struct pl01x_serial_platdata serial_platdata = {
+static const struct pl01x_serial_plat serial_plat = {
.base = 0x80406000,
.type = TYPE_PL011,
.clock = 2700 * 1000,
U_BOOT_DEVICE(stv09911_serials) = {
.name = "serial_pl01x",
- .plat = &serial_platdata,
+ .plat = &serial_plat,
};
#endif
return 0;
}
-static struct coldfire_serial_platdata mcf5307_serial_plat = {
+static struct coldfire_serial_plat mcf5307_serial_plat = {
.base = CONFIG_SYS_UART_BASE,
.port = 0,
.baudrate = CONFIG_BAUDRATE,
#endif
#if !CONFIG_IS_ENABLED(OF_CONTROL)
-static const struct omap_hsmmc_plat am335x_mmc0_platdata = {
+static const struct omap_hsmmc_plat am335x_mmc0_plat = {
.base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE,
.cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT,
.cfg.f_min = 400000,
U_BOOT_DEVICE(am335x_mmc0) = {
.name = "omap_hsmmc",
- .plat = &am335x_mmc0_platdata,
+ .plat = &am335x_mmc0_plat,
};
-static const struct omap_hsmmc_plat am335x_mmc1_platdata = {
+static const struct omap_hsmmc_plat am335x_mmc1_plat = {
.base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE,
.cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT,
.cfg.f_min = 400000,
U_BOOT_DEVICE(am335x_mmc1) = {
.name = "omap_hsmmc",
- .plat = &am335x_mmc1_platdata,
+ .plat = &am335x_mmc1_plat,
};
#endif
0
};
-static const struct ns16550_platdata devkit8000_serial = {
+static const struct ns16550_plat devkit8000_serial = {
.base = OMAP34XX_UART3,
.reg_shift = 2,
.clock = V_NS16550_CLK,
#endif /* CONFIG_SPL_BUILD */
-static struct mxc_serial_platdata mxc_serial_plat = {
+static struct mxc_serial_plat mxc_serial_plat = {
.reg = (struct mxc_uart *)UART1_BASE,
.use_dte = true,
};
}
#endif
-static struct mxc_serial_platdata mxc_serial_plat = {
+static struct mxc_serial_plat mxc_serial_plat = {
.reg = (struct mxc_uart *)UART1_BASE,
.use_dte = 1,
};
#endif /* CONFIG_SPL_BUILD */
-static struct mxc_serial_platdata mxc_serial_plat = {
+static struct mxc_serial_plat mxc_serial_plat = {
.reg = (struct mxc_uart *)UART1_BASE,
.use_dte = true,
};
return 0;
}
#else /* !CONFIG_IS_ENABLED(DM_MMC) */
-static const struct pxa_mmc_plat mmc_platdata = {
+static const struct pxa_mmc_plat mmc_plat = {
.base = (struct pxa_mmc_regs *)MMC0_BASE,
};
U_BOOT_DEVICE(pxa_mmcs) = {
.name = "pxa_mmc",
- .plat = &mmc_platdata,
+ .plat = &mmc_plat,
};
#endif /* !CONFIG_IS_ENABLED(DM_MMC) */
#endif
-static const struct pxa_serial_platdata serial_platdata = {
+static const struct pxa_serial_plat serial_plat = {
.base = (struct pxa_uart_regs *)FFUART_BASE,
.port = FFUART_INDEX,
.baudrate = CONFIG_BAUDRATE,
U_BOOT_DEVICE(pxa_serials) = {
.name = "serial_pxa",
- .plat = &serial_platdata,
+ .plat = &serial_plat,
};
for (uclass_first_device(UCLASS_CPU, &dev);
dev;
uclass_next_device(&dev)) {
- struct cpu_platdata *plat = dev_get_parent_plat(dev);
+ struct cpu_plat *plat = dev_get_parent_plat(dev);
struct cpu_info info;
bool first = true;
int ret, i;
for (device_find_first_child(bus, &dev);
dev;
device_find_next_child(&dev)) {
- struct pci_child_platdata *pplat;
+ struct pci_child_plat *pplat;
pplat = dev_get_parent_plat(dev);
if (short_listing) {
return CMD_RET_SUCCESS;
}
-static int curr_dev_and_platdata(struct udevice **devp,
- struct dm_regulator_uclass_plat **uc_pdata,
- bool allow_type_fixed)
+static int curr_dev_and_plat(struct udevice **devp,
+ struct dm_regulator_uclass_plat **uc_pdata,
+ bool allow_type_fixed)
{
*devp = NULL;
*uc_pdata = NULL;
int ret;
int i;
- ret = curr_dev_and_platdata(&dev, &uc_pdata, true);
+ ret = curr_dev_and_plat(&dev, &uc_pdata, true);
if (ret)
return ret;
int ret;
if (currdev && (argc < 2 || strcmp(argv[1], "-a"))) {
- ret = curr_dev_and_platdata(&dev, &uc_pdata, true);
+ ret = curr_dev_and_plat(&dev, &uc_pdata, true);
if (ret)
return CMD_RET_FAILURE;
do_status_detail(dev, uc_pdata);
int force;
int ret;
- ret = curr_dev_and_platdata(&dev, &uc_pdata, argc == 1);
+ ret = curr_dev_and_plat(&dev, &uc_pdata, argc == 1);
if (ret)
return ret;
int current;
int ret;
- ret = curr_dev_and_platdata(&dev, &uc_pdata, argc == 1);
+ ret = curr_dev_and_plat(&dev, &uc_pdata, argc == 1);
if (ret)
return ret;
int mode;
int ret;
- ret = curr_dev_and_platdata(&dev, &uc_pdata, false);
+ ret = curr_dev_and_plat(&dev, &uc_pdata, false);
if (ret)
return ret;
struct dm_regulator_uclass_plat *uc_pdata;
int ret;
- ret = curr_dev_and_platdata(&dev, &uc_pdata, true);
+ ret = curr_dev_and_plat(&dev, &uc_pdata, true);
if (ret)
return ret;
struct dm_regulator_uclass_plat *uc_pdata;
int ret;
- ret = curr_dev_and_platdata(&dev, &uc_pdata, true);
+ ret = curr_dev_and_plat(&dev, &uc_pdata, true);
if (ret)
return ret;
const char *name;
ulong fb_base;
#ifdef CONFIG_DM_VIDEO
- struct video_uc_platdata *plat;
+ struct video_uc_plat *plat;
struct video_priv *uc_priv;
struct udevice *dev;
int ret;
.post_probe = usb_hub_post_probe,
.child_pre_probe = usb_child_pre_probe,
.per_child_auto = sizeof(struct usb_device),
- .per_child_plat_auto = sizeof(struct usb_dev_platdata),
+ .per_child_plat_auto = sizeof(struct usb_dev_plat),
.per_device_auto = sizeof(struct usb_hub_device),
};
#include <dt-structs.h>
- struct mmc_platdata {
+ struct mmc_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
/* Put this first since driver model will copy the data here */
struct dtd_mmc dtplat;
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
/* Decode the device tree data */
- struct mmc_platdata *plat = dev_get_plat(dev);
+ struct mmc_plat *plat = dev_get_plat(dev);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
static int mmc_probe(struct udevice *dev)
{
- struct mmc_platdata *plat = dev_get_plat(dev);
+ struct mmc_plat *plat = dev_get_plat(dev);
#if CONFIG_IS_ENABLED(OF_PLATDATA)
/* Decode the of-platdata from the C structures */
.of_to_plat = mmc_of_to_plat,
.probe = mmc_probe,
.priv_auto = sizeof(struct mmc_priv),
- .plat_auto = sizeof(struct mmc_platdata),
+ .plat_auto = sizeof(struct mmc_plat),
};
U_BOOT_DRIVER_ALIAS(mmc_drv, vendor_mmc) /* matches compatible string */
-Note that struct mmc_platdata is defined in the C file, not in a header. This
+Note that struct mmc_plat is defined in the C file, not in a header. This
is to avoid needing to include dt-structs.h in a header file. The idea is to
keep the use of each of-platdata struct to the smallest possible code area.
There is just one driver C file for each struct, that can convert from the
.. code-block:: c
- struct exynos_spi_platdata {
+ struct exynos_spi_plat {
enum periph_id periph_id;
s32 frequency; /* Default clock frequency, -1 for none */
struct exynos_spi *regs;
U_BOOT_DRIVER(spi_exynos) = {
...
- .plat_auto = sizeof(struct exynos_spi_platdata),
+ .plat_auto = sizeof(struct exynos_spi_plat),
Here is a sample function. It gets a pointer to the platform data and
static int exynos_spi_of_to_plat(struct udevice *bus)
{
- struct exynos_spi_platdata *plat = bus->plat;
+ struct exynos_spi_plat *plat = bus->plat;
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
.. code-block:: c
- struct exynos_spi_platdata platdata_spi0 = {
+ struct exynos_spi_plat platdata_spi0 = {
.periph_id = ...
.frequency = ...
.regs = ...
static int exynos_spi_probe(struct udevice *bus)
{
- struct exynos_spi_platdata *plat = dev_get_plat(bus);
+ struct exynos_spi_plat *plat = dev_get_plat(bus);
struct exynos_spi_priv *priv = dev_get_priv(bus);
priv->regs = plat->regs;
static int exynos_spi_set_speed(struct udevice *bus, uint speed)
{
- struct exynos_spi_platdata *plat = bus->plat;
+ struct exynos_spi_plat *plat = bus->plat;
struct exynos_spi_priv *priv = dev_get_priv(bus);
int ret;
static void spi_cs_activate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct exynos_spi_platdata *pdata = dev_get_plat(bus);
+ struct exynos_spi_plat *pdata = dev_get_plat(bus);
struct exynos_spi_priv *priv = dev_get_priv(bus);
/* If it's too soon to do another transaction, wait */
The SPI uclass keeps some information about each device 'dev' on the bus:
- struct dm_spi_slave_platdata:
+ struct dm_spi_slave_plat:
This is device_get_parent_plat(dev).
This is where the chip select number is stored, along with
the default bus speed and mode. It is automatically read
.probe = tegra_ehci_usb_probe,
.remove = tegra_ehci_usb_remove,
.ops = &ehci_usb_ops,
- .plat_auto = sizeof(struct usb_platdata),
+ .plat_auto = sizeof(struct usb_plat),
.priv_auto = sizeof(struct fdt_usb),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
exists when the device is probed (not when it is bound) and is removed when
the driver is removed.
-Note that usb_platdata is currently only used to deal with setting up a bus
+Note that usb_plat is currently only used to deal with setting up a bus
in USB device mode (OTG operation). It can be omitted if that is not
supported.
handles that). Once the device is set up, you can find the device
descriptor and current configuration descriptor in this structure.
-- struct usb_platdata:
+- struct usb_plat:
This holds platform data for a controller. So far this is only used
as a work-around for controllers which can act as USB devices in OTG
mode, since the gadget framework does not use driver model.
-- struct usb_dev_platdata:
+- struct usb_dev_plat:
This holds platform data for a device. You can access it for a
device 'dev' with dev_get_parent_plat(dev). It holds the device
address and speed - anything that can be determined before the device
return _adc_channels_single_shot(dev, channel_mask, channels);
}
-static int adc_vdd_platdata_update(struct udevice *dev)
+static int adc_vdd_plat_update(struct udevice *dev)
{
struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
int ret;
return 0;
}
-static int adc_vss_platdata_update(struct udevice *dev)
+static int adc_vss_plat_update(struct udevice *dev)
{
struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
int ret;
int ret, value_sign = uc_pdata->vdd_polarity_negative ? -1 : 1;
/* Update the regulator Value. */
- ret = adc_vdd_platdata_update(dev);
+ ret = adc_vdd_plat_update(dev);
if (ret)
return ret;
int ret, value_sign = uc_pdata->vss_polarity_negative ? -1 : 1;
/* Update the regulator Value. */
- ret = adc_vss_platdata_update(dev);
+ ret = adc_vss_plat_update(dev);
if (ret)
return ret;
return 0;
}
-static int adc_vdd_platdata_set(struct udevice *dev)
+static int adc_vdd_plat_set(struct udevice *dev)
{
struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
int ret;
ret = device_get_supply_regulator(dev, "vdd-supply",
&uc_pdata->vdd_supply);
if (!ret)
- return adc_vdd_platdata_update(dev);
+ return adc_vdd_plat_update(dev);
if (ret != -ENOENT)
return ret;
return 0;
}
-static int adc_vss_platdata_set(struct udevice *dev)
+static int adc_vss_plat_set(struct udevice *dev)
{
struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
int ret;
ret = device_get_supply_regulator(dev, "vss-supply",
&uc_pdata->vss_supply);
if (!ret)
- return adc_vss_platdata_update(dev);
+ return adc_vss_plat_update(dev);
if (ret != -ENOENT)
return ret;
int ret;
/* Set ADC VDD plat: polarity, uV, regulator (phandle). */
- ret = adc_vdd_platdata_set(dev);
+ ret = adc_vdd_plat_set(dev);
if (ret)
pr_err("%s: Can't update Vdd. Error: %d", dev->name, ret);
/* Set ADC VSS plat: polarity, uV, regulator (phandle). */
- ret = adc_vss_platdata_set(dev);
+ ret = adc_vss_plat_set(dev);
if (ret)
pr_err("%s: Can't update Vss. Error: %d", dev->name, ret);
#if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
# ifdef CONFIG_DM_PCI
struct udevice *dev = uc_priv->dev;
- struct pci_child_platdata *pplat = dev_get_parent_plat(dev);
+ struct pci_child_plat *pplat = dev_get_parent_plat(dev);
# else
pci_dev_t pdev = uc_priv->dev;
unsigned short vendor;
pci_write_config_byte(dev, 0x41, 0xa1);
#endif
#else
- struct scsi_platdata *plat = dev_get_uclass_plat(dev);
+ struct scsi_plat *plat = dev_get_uclass_plat(dev);
uc_priv->mmio_base = (void *)plat->base;
#endif
int ahci_probe_scsi(struct udevice *ahci_dev, ulong base)
{
struct ahci_uc_priv *uc_priv;
- struct scsi_platdata *uc_plat;
+ struct scsi_plat *uc_plat;
struct udevice *dev;
int ret;
DECLARE_GLOBAL_DATA_PTR;
-struct socfpga_clk_platdata {
+struct socfpga_clk_plat {
void __iomem *regs;
};
* function to write the bypass register which requires a poll of the
* busy bit
*/
-static void clk_write_bypass_mainpll(struct socfpga_clk_platdata *plat, u32 val)
+static void clk_write_bypass_mainpll(struct socfpga_clk_plat *plat, u32 val)
{
CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS);
cm_wait_for_fsm();
}
-static void clk_write_bypass_perpll(struct socfpga_clk_platdata *plat, u32 val)
+static void clk_write_bypass_perpll(struct socfpga_clk_plat *plat, u32 val)
{
CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS);
cm_wait_for_fsm();
}
/* function to write the ctrl register which requires a poll of the busy bit */
-static void clk_write_ctrl(struct socfpga_clk_platdata *plat, u32 val)
+static void clk_write_ctrl(struct socfpga_clk_plat *plat, u32 val)
{
CM_REG_WRITEL(plat, val, CLKMGR_CTRL);
cm_wait_for_fsm();
},
};
-static int membus_wait_for_req(struct socfpga_clk_platdata *plat, u32 pll,
+static int membus_wait_for_req(struct socfpga_clk_plat *plat, u32 pll,
int timeout)
{
int cnt = 0;
return 0;
}
-static int membus_write_pll(struct socfpga_clk_platdata *plat, u32 pll,
+static int membus_write_pll(struct socfpga_clk_plat *plat, u32 pll,
u32 addr_offset, u32 wdat, int timeout)
{
u32 addr;
return membus_wait_for_req(plat, pll, timeout);
}
-static int membus_read_pll(struct socfpga_clk_platdata *plat, u32 pll,
+static int membus_read_pll(struct socfpga_clk_plat *plat, u32 pll,
u32 addr_offset, u32 *rdata, int timeout)
{
u32 addr;
return 0;
}
-static void membus_pll_configs(struct socfpga_clk_platdata *plat, u32 pll)
+static void membus_pll_configs(struct socfpga_clk_plat *plat, u32 pll)
{
int i;
u32 rdata;
static void clk_basic_init(struct udevice *dev,
const struct cm_config * const cfg)
{
- struct socfpga_clk_platdata *plat = dev_get_plat(dev);
+ struct socfpga_clk_plat *plat = dev_get_plat(dev);
u32 vcocalib;
if (!cfg)
CM_REG_READL(plat, CLKMGR_CTRL) & ~CLKMGR_CTRL_BOOTMODE);
}
-static u64 clk_get_vco_clk_hz(struct socfpga_clk_platdata *plat,
+static u64 clk_get_vco_clk_hz(struct socfpga_clk_plat *plat,
u32 pllglob_reg, u32 pllm_reg)
{
u64 fref, arefdiv, mdiv, reg, vco;
return vco;
}
-static u64 clk_get_main_vco_clk_hz(struct socfpga_clk_platdata *plat)
+static u64 clk_get_main_vco_clk_hz(struct socfpga_clk_plat *plat)
{
return clk_get_vco_clk_hz(plat, CLKMGR_MAINPLL_PLLGLOB,
CLKMGR_MAINPLL_PLLM);
}
-static u64 clk_get_per_vco_clk_hz(struct socfpga_clk_platdata *plat)
+static u64 clk_get_per_vco_clk_hz(struct socfpga_clk_plat *plat)
{
return clk_get_vco_clk_hz(plat, CLKMGR_PERPLL_PLLGLOB,
CLKMGR_PERPLL_PLLM);
}
-static u32 clk_get_5_1_clk_src(struct socfpga_clk_platdata *plat, u64 reg)
+static u32 clk_get_5_1_clk_src(struct socfpga_clk_plat *plat, u64 reg)
{
u32 clksrc = CM_REG_READL(plat, reg);
return (clksrc & CLKMGR_CLKSRC_MASK) >> CLKMGR_CLKSRC_OFFSET;
}
-static u64 clk_get_clksrc_hz(struct socfpga_clk_platdata *plat, u32 clksrc_reg,
+static u64 clk_get_clksrc_hz(struct socfpga_clk_plat *plat, u32 clksrc_reg,
u32 main_reg, u32 per_reg)
{
u64 clock;
return clock;
}
-static u64 clk_get_mpu_clk_hz(struct socfpga_clk_platdata *plat)
+static u64 clk_get_mpu_clk_hz(struct socfpga_clk_plat *plat)
{
u64 clock = clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_MPUCLK,
CLKMGR_MAINPLL_PLLC0,
return clock;
}
-static u32 clk_get_l3_main_clk_hz(struct socfpga_clk_platdata *plat)
+static u32 clk_get_l3_main_clk_hz(struct socfpga_clk_plat *plat)
{
return clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_NOCCLK,
CLKMGR_MAINPLL_PLLC1,
CLKMGR_PERPLL_PLLC1);
}
-static u32 clk_get_l4_main_clk_hz(struct socfpga_clk_platdata *plat)
+static u32 clk_get_l4_main_clk_hz(struct socfpga_clk_plat *plat)
{
u64 clock = clk_get_l3_main_clk_hz(plat);
return clock;
}
-static u32 clk_get_sdmmc_clk_hz(struct socfpga_clk_platdata *plat)
+static u32 clk_get_sdmmc_clk_hz(struct socfpga_clk_plat *plat)
{
u64 clock = clk_get_clksrc_hz(plat, CLKMGR_ALTR_SDMMCCTR,
CLKMGR_MAINPLL_PLLC3,
return clock / 4;
}
-static u32 clk_get_l4_sp_clk_hz(struct socfpga_clk_platdata *plat)
+static u32 clk_get_l4_sp_clk_hz(struct socfpga_clk_plat *plat)
{
u64 clock = clk_get_l3_main_clk_hz(plat);
return clock;
}
-static u32 clk_get_l4_mp_clk_hz(struct socfpga_clk_platdata *plat)
+static u32 clk_get_l4_mp_clk_hz(struct socfpga_clk_plat *plat)
{
u64 clock = clk_get_l3_main_clk_hz(plat);
return clock;
}
-static u32 clk_get_l4_sys_free_clk_hz(struct socfpga_clk_platdata *plat)
+static u32 clk_get_l4_sys_free_clk_hz(struct socfpga_clk_plat *plat)
{
if (CM_REG_READL(plat, CLKMGR_STAT) & CLKMGR_STAT_BOOTMODE)
return clk_get_l3_main_clk_hz(plat) / 2;
return clk_get_l3_main_clk_hz(plat) / 4;
}
-static u32 clk_get_emac_clk_hz(struct socfpga_clk_platdata *plat, u32 emac_id)
+static u32 clk_get_emac_clk_hz(struct socfpga_clk_plat *plat, u32 emac_id)
{
bool emacsel_a;
u32 ctl;
static ulong socfpga_clk_get_rate(struct clk *clk)
{
- struct socfpga_clk_platdata *plat = dev_get_plat(clk->dev);
+ struct socfpga_clk_plat *plat = dev_get_plat(clk->dev);
switch (clk->id) {
case AGILEX_MPU_CLK:
static int socfpga_clk_of_to_plat(struct udevice *dev)
{
- struct socfpga_clk_platdata *plat = dev_get_plat(dev);
+ struct socfpga_clk_plat *plat = dev_get_plat(dev);
fdt_addr_t addr;
addr = dev_read_addr(dev);
.ops = &socfpga_clk_ops,
.probe = socfpga_clk_probe,
.of_to_plat = socfpga_clk_of_to_plat,
- .plat_auto = sizeof(struct socfpga_clk_platdata),
+ .plat_auto = sizeof(struct socfpga_clk_plat),
};
SOCFPGA_A10_CLK_UNKNOWN_CLK,
};
-struct socfpga_a10_clk_platdata {
+struct socfpga_a10_clk_plat {
enum socfpga_a10_clk_type type;
struct clk_bulk clks;
u32 regs;
static int socfpga_a10_clk_get_upstream(struct clk *clk, struct clk **upclk)
{
- struct socfpga_a10_clk_platdata *plat = dev_get_plat(clk->dev);
+ struct socfpga_a10_clk_plat *plat = dev_get_plat(clk->dev);
u32 reg, maxval;
if (plat->clks.count == 0)
static int socfpga_a10_clk_endisable(struct clk *clk, bool enable)
{
- struct socfpga_a10_clk_platdata *plat = dev_get_plat(clk->dev);
+ struct socfpga_a10_clk_plat *plat = dev_get_plat(clk->dev);
struct clk *upclk = NULL;
int ret;
static ulong socfpga_a10_clk_get_rate(struct clk *clk)
{
- struct socfpga_a10_clk_platdata *plat = dev_get_plat(clk->dev);
+ struct socfpga_a10_clk_plat *plat = dev_get_plat(clk->dev);
struct clk *upclk = NULL;
ulong rate = 0, reg, numer, denom;
int ret;
*/
static void socfpga_a10_handoff_workaround(struct udevice *dev)
{
- struct socfpga_a10_clk_platdata *plat = dev_get_plat(dev);
+ struct socfpga_a10_clk_plat *plat = dev_get_plat(dev);
const void *fdt = gd->fdt_blob;
struct clk_bulk *bulk = &plat->clks;
int i, ret, offset = dev_of_offset(dev);
static int socfpga_a10_clk_probe(struct udevice *dev)
{
- struct socfpga_a10_clk_platdata *plat = dev_get_plat(dev);
- struct socfpga_a10_clk_platdata *pplat;
+ struct socfpga_a10_clk_plat *plat = dev_get_plat(dev);
+ struct socfpga_a10_clk_plat *pplat;
struct udevice *pdev;
const void *fdt = gd->fdt_blob;
int offset = dev_of_offset(dev);
static int socfpga_a10_of_to_plat(struct udevice *dev)
{
- struct socfpga_a10_clk_platdata *plat = dev_get_plat(dev);
+ struct socfpga_a10_clk_plat *plat = dev_get_plat(dev);
unsigned int divreg[3], gatereg[2];
int ret;
.probe = socfpga_a10_clk_probe,
.of_to_plat = socfpga_a10_of_to_plat,
- .plat_auto = sizeof(struct socfpga_a10_clk_platdata),
+ .plat_auto = sizeof(struct socfpga_a10_clk_plat),
};
DECLARE_GLOBAL_DATA_PTR;
-struct pmc_platdata {
+struct pmc_plat {
struct at91_pmc *reg_base;
struct regmap *regmap_sfr;
};
static int at91_pmc_core_probe(struct udevice *dev)
{
- struct pmc_platdata *plat = dev_get_plat(dev);
+ struct pmc_plat *plat = dev_get_plat(dev);
dev = dev_get_parent(dev);
int at91_clk_probe(struct udevice *dev)
{
struct udevice *dev_periph_container, *dev_pmc;
- struct pmc_platdata *plat = dev_get_plat(dev);
+ struct pmc_plat *plat = dev_get_plat(dev);
dev_periph_container = dev_get_parent(dev);
dev_pmc = dev_get_parent(dev_periph_container);
/* Main osc clock specific code. */
static int main_osc_clk_enable(struct clk *clk)
{
- struct pmc_platdata *plat = dev_get_plat(clk->dev);
+ struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
if (readl(&pmc->sr) & AT91_PMC_MOSCSELS)
.id = UCLASS_CLK,
.of_match = main_osc_clk_match,
.probe = main_osc_clk_probe,
- .plat_auto = sizeof(struct pmc_platdata),
+ .plat_auto = sizeof(struct pmc_plat),
.ops = &main_osc_clk_ops,
};
/* PLLA clock specific code. */
static int plla_clk_enable(struct clk *clk)
{
- struct pmc_platdata *plat = dev_get_plat(clk->dev);
+ struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
if (readl(&pmc->sr) & AT91_PMC_LOCKA)
.id = UCLASS_CLK,
.of_match = plla_clk_match,
.probe = plla_clk_probe,
- .plat_auto = sizeof(struct pmc_platdata),
+ .plat_auto = sizeof(struct pmc_plat),
.ops = &plla_clk_ops,
};
static ulong at91_plladiv_clk_get_rate(struct clk *clk)
{
- struct pmc_platdata *plat = dev_get_plat(clk->dev);
+ struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
struct clk source;
ulong clk_rate;
static ulong at91_plladiv_clk_set_rate(struct clk *clk, ulong rate)
{
- struct pmc_platdata *plat = dev_get_plat(clk->dev);
+ struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
struct clk source;
ulong parent_rate;
.id = UCLASS_CLK,
.of_match = at91_plladiv_clk_match,
.probe = at91_plladiv_clk_probe,
- .plat_auto = sizeof(struct pmc_platdata),
+ .plat_auto = sizeof(struct pmc_plat),
.ops = &at91_plladiv_clk_ops,
};
static int system_clk_enable(struct clk *clk)
{
- struct pmc_platdata *plat = dev_get_plat(clk->dev);
+ struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
u32 mask;
.name = "system-clk",
.id = UCLASS_CLK,
.probe = at91_clk_probe,
- .plat_auto = sizeof(struct pmc_platdata),
+ .plat_auto = sizeof(struct pmc_plat),
.ops = &system_clk_ops,
};
static int periph_clk_enable(struct clk *clk)
{
- struct pmc_platdata *plat = dev_get_plat(clk->dev);
+ struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
enum periph_clk_type clk_type;
void *addr;
U_BOOT_DRIVER(clk_periph) = {
.name = "periph-clk",
.id = UCLASS_CLK,
- .plat_auto = sizeof(struct pmc_platdata),
+ .plat_auto = sizeof(struct pmc_plat),
.probe = at91_clk_probe,
.ops = &periph_clk_ops,
};
static int utmi_clk_enable(struct clk *clk)
{
- struct pmc_platdata *plat = dev_get_plat(clk->dev);
+ struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
struct clk clk_dev;
ulong clk_rate;
static int utmi_clk_of_to_plat(struct udevice *dev)
{
- struct pmc_platdata *plat = dev_get_plat(dev);
+ struct pmc_plat *plat = dev_get_plat(dev);
struct udevice *syscon;
uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
.of_match = utmi_clk_match,
.probe = utmi_clk_probe,
.of_to_plat = utmi_clk_of_to_plat,
- .plat_auto = sizeof(struct pmc_platdata),
+ .plat_auto = sizeof(struct pmc_plat),
.ops = &utmi_clk_ops,
};
static ulong sama5d4_h32mx_clk_get_rate(struct clk *clk)
{
- struct pmc_platdata *plat = dev_get_plat(clk->dev);
+ struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
ulong rate = gd->arch.mck_rate_hz;
.id = UCLASS_CLK,
.of_match = sama5d4_h32mx_clk_match,
.probe = sama5d4_h32mx_clk_probe,
- .plat_auto = sizeof(struct pmc_platdata),
+ .plat_auto = sizeof(struct pmc_plat),
.ops = &sama5d4_h32mx_clk_ops,
};
static ulong generic_clk_get_rate(struct clk *clk)
{
- struct pmc_platdata *plat = dev_get_plat(clk->dev);
+ struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
struct clk parent;
ulong clk_rate;
static ulong generic_clk_set_rate(struct clk *clk, ulong rate)
{
- struct pmc_platdata *plat = dev_get_plat(clk->dev);
+ struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
struct generic_clk_priv *priv = dev_get_priv(clk->dev);
struct clk parent, best_parent;
.probe = at91_clk_probe,
.of_to_plat = generic_clk_of_to_plat,
.priv_auto = sizeof(struct generic_clk_priv),
- .plat_auto = sizeof(struct pmc_platdata),
+ .plat_auto = sizeof(struct pmc_plat),
.ops = &generic_clk_ops,
};
static ulong at91_usb_clk_get_rate(struct clk *clk)
{
- struct pmc_platdata *plat = dev_get_plat(clk->dev);
+ struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
struct clk source;
u32 tmp, usbdiv;
static ulong at91_usb_clk_set_rate(struct clk *clk, ulong rate)
{
- struct pmc_platdata *plat = dev_get_plat(clk->dev);
+ struct pmc_plat *plat = dev_get_plat(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
struct at91_usb_clk_priv *priv = dev_get_priv(clk->dev);
struct clk source, best_source;
.probe = at91_usb_clk_probe,
.of_to_plat = at91_usb_clk_of_to_plat,
.priv_auto = sizeof(struct at91_usb_clk_priv),
- .plat_auto = sizeof(struct pmc_platdata),
+ .plat_auto = sizeof(struct pmc_plat),
.ops = &at91_usb_clk_ops,
};
}
#if CONFIG_IS_ENABLED(OF_PLATDATA)
-int regmap_init_mem_platdata(struct udevice *dev, fdt_val_t *reg, int count,
- struct regmap **mapp)
+int regmap_init_mem_plat(struct udevice *dev, fdt_val_t *reg, int count,
+ struct regmap **mapp)
{
struct regmap_range *range;
struct regmap *map;
}
#endif
-int dm_scan_platdata(bool pre_reloc_only)
+int dm_scan_plat(bool pre_reloc_only)
{
int ret;
debug("dm_init() failed: %d\n", ret);
return ret;
}
- ret = dm_scan_platdata(pre_reloc_only);
+ ret = dm_scan_plat(pre_reloc_only);
if (ret) {
- debug("dm_scan_platdata() failed: %d\n", ret);
+ debug("dm_scan_plat() failed: %d\n", ret);
return ret;
}
* using OF_PLATDATA will need to ensure that this is true.
*/
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- struct syscon_base_platdata *plat = dev_get_plat(dev);
+ struct syscon_base_plat *plat = dev_get_plat(dev);
- return regmap_init_mem_platdata(dev, plat->reg, ARRAY_SIZE(plat->reg),
+ return regmap_init_mem_plat(dev, plat->reg, ARRAY_SIZE(plat->reg),
&priv->regmap);
#else
return regmap_init_mem(dev_ofnode(dev), &priv->regmap);
#include <div64.h>
#include <linux/clk-provider.h>
-struct at91_cpu_platdata {
+struct at91_cpu_plat {
const char *name;
ulong cpufreq_mhz;
ulong mckfreq_mhz;
int at91_cpu_get_desc(const struct udevice *dev, char *buf, int size)
{
- struct at91_cpu_platdata *plat = dev_get_plat(dev);
+ struct at91_cpu_plat *plat = dev_get_plat(dev);
snprintf(buf, size, "%s\n"
"Crystal frequency: %8lu MHz\n"
static int at91_cpu_get_info(const struct udevice *dev, struct cpu_info *info)
{
- struct at91_cpu_platdata *plat = dev_get_plat(dev);
+ struct at91_cpu_plat *plat = dev_get_plat(dev);
info->cpu_freq = plat->cpufreq_mhz * 1000000;
info->features = BIT(CPU_FEAT_L1_CACHE);
static int at91_cpu_probe(struct udevice *dev)
{
- struct at91_cpu_platdata *plat = dev_get_plat(dev);
+ struct at91_cpu_plat *plat = dev_get_plat(dev);
struct clk clk;
ulong rate;
int ret;
.of_match = at91_cpu_ids,
.ops = &at91_cpu_ops,
.probe = at91_cpu_probe,
- .plat_auto = sizeof(struct at91_cpu_platdata),
+ .plat_auto = sizeof(struct at91_cpu_plat),
.flags = DM_FLAG_PRE_RELOC,
};
/* BMIPS CPU driver */
int bmips_cpu_bind(struct udevice *dev)
{
- struct cpu_platdata *plat = dev_get_parent_plat(dev);
+ struct cpu_plat *plat = dev_get_parent_plat(dev);
plat->cpu_id = dev_read_u32_default(dev, "reg", -1);
plat->device_id = read_c0_prid();
U_BOOT_DRIVER(cpu_bus) = {
.name = "cpu_bus",
.id = UCLASS_SIMPLE_BUS,
- .per_child_plat_auto = sizeof(struct cpu_platdata),
+ .per_child_plat_auto = sizeof(struct cpu_plat),
};
static int uclass_cpu_init(struct uclass *uc)
static int cpu_sandbox_bind(struct udevice *dev)
{
int ret;
- struct cpu_platdata *plat = dev_get_parent_plat(dev);
+ struct cpu_plat *plat = dev_get_parent_plat(dev);
/* first examine the property in current cpu node */
ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq);
DECLARE_GLOBAL_DATA_PTR;
-struct cpu_imx_platdata {
+struct cpu_imx_plat {
const char *name;
const char *rev;
const char *type;
static void set_core_data(struct udevice *dev)
{
- struct cpu_imx_platdata *plat = dev_get_plat(dev);
+ struct cpu_imx_plat *plat = dev_get_plat(dev);
if (device_is_compatible(dev, "arm,cortex-a35")) {
plat->cpu_rsrc = SC_R_A35;
}
#if IS_ENABLED(CONFIG_IMX_SCU_THERMAL)
-static int cpu_imx_get_temp(struct cpu_imx_platdata *plat)
+static int cpu_imx_get_temp(struct cpu_imx_plat *plat)
{
struct udevice *thermal_dev;
int cpu_tmp, ret;
return cpu_tmp;
}
#else
-static int cpu_imx_get_temp(struct cpu_imx_platdata *plat)
+static int cpu_imx_get_temp(struct cpu_imx_plat *plat)
{
return 0;
}
int cpu_imx_get_desc(const struct udevice *dev, char *buf, int size)
{
- struct cpu_imx_platdata *plat = dev_get_plat(dev);
+ struct cpu_imx_plat *plat = dev_get_plat(dev);
int ret, temp;
if (size < 100)
static int cpu_imx_get_info(const struct udevice *dev, struct cpu_info *info)
{
- struct cpu_imx_platdata *plat = dev_get_plat(dev);
+ struct cpu_imx_plat *plat = dev_get_plat(dev);
info->cpu_freq = plat->freq_mhz * 1000;
info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU);
static int cpu_imx_is_current(struct udevice *dev)
{
- struct cpu_imx_platdata *plat = dev_get_plat(dev);
+ struct cpu_imx_plat *plat = dev_get_plat(dev);
if (plat->mpidr == (read_mpidr() & 0xffff))
return 1;
static ulong imx8_get_cpu_rate(struct udevice *dev)
{
- struct cpu_imx_platdata *plat = dev_get_plat(dev);
+ struct cpu_imx_plat *plat = dev_get_plat(dev);
ulong rate;
int ret;
static int imx8_cpu_probe(struct udevice *dev)
{
- struct cpu_imx_platdata *plat = dev_get_plat(dev);
+ struct cpu_imx_plat *plat = dev_get_plat(dev);
u32 cpurev;
set_core_data(dev);
.of_match = cpu_imx8_ids,
.ops = &cpu_imx8_ops,
.probe = imx8_cpu_probe,
- .plat_auto = sizeof(struct cpu_imx_platdata),
+ .plat_auto = sizeof(struct cpu_imx_plat),
.flags = DM_FLAG_PRE_RELOC,
};
static int riscv_cpu_bind(struct udevice *dev)
{
- struct cpu_platdata *plat = dev_get_parent_plat(dev);
+ struct cpu_plat *plat = dev_get_parent_plat(dev);
struct driver *drv;
int ret;
int sdram_mmr_init_full(struct udevice *dev)
{
- struct altera_sdram_platdata *plat = dev->plat;
+ struct altera_sdram_plat *plat = dev->plat;
struct altera_sdram_priv *priv = dev_get_priv(dev);
u32 i;
int ret;
struct ram_info info;
};
-struct altera_gen5_sdram_platdata {
+struct altera_gen5_sdram_plat {
struct socfpga_sdr *sdr;
};
static int altera_gen5_sdram_of_to_plat(struct udevice *dev)
{
- struct altera_gen5_sdram_platdata *plat = dev->plat;
+ struct altera_gen5_sdram_plat *plat = dev->plat;
plat->sdr = (struct socfpga_sdr *)devfdt_get_addr_index(dev, 0);
if (!plat->sdr)
{
int ret;
unsigned long sdram_size;
- struct altera_gen5_sdram_platdata *plat = dev->plat;
+ struct altera_gen5_sdram_plat *plat = dev->plat;
struct altera_gen5_sdram_priv *priv = dev_get_priv(dev);
struct socfpga_sdr_ctrl *sdr_ctrl = &plat->sdr->sdr_ctrl;
struct reset_ctl_bulk resets;
.of_match = altera_gen5_sdram_ids,
.ops = &altera_gen5_sdram_ops,
.of_to_plat = altera_gen5_sdram_of_to_plat,
- .plat_auto = sizeof(struct altera_gen5_sdram_platdata),
+ .plat_auto = sizeof(struct altera_gen5_sdram_plat),
.probe = altera_gen5_sdram_probe,
.priv_auto = sizeof(struct altera_gen5_sdram_priv),
};
*/
int sdram_mmr_init_full(struct udevice *dev)
{
- struct altera_sdram_platdata *plat = dev->plat;
+ struct altera_sdram_plat *plat = dev->plat;
struct altera_sdram_priv *priv = dev_get_priv(dev);
u32 update_value, io48_value, ddrioctl;
u32 i;
#define PGTABLE_OFF 0x4000
-u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg)
+u32 hmc_readl(struct altera_sdram_plat *plat, u32 reg)
{
return readl(plat->iomhc + reg);
}
-u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg)
+u32 hmc_ecc_readl(struct altera_sdram_plat *plat, u32 reg)
{
return readl(plat->hmc + reg);
}
-u32 hmc_ecc_writel(struct altera_sdram_platdata *plat,
+u32 hmc_ecc_writel(struct altera_sdram_plat *plat,
u32 data, u32 reg)
{
return writel(data, plat->hmc + reg);
}
-u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data,
+u32 ddr_sch_writel(struct altera_sdram_plat *plat, u32 data,
u32 reg)
{
return writel(data, plat->ddr_sch + reg);
}
-int emif_clear(struct altera_sdram_platdata *plat)
+int emif_clear(struct altera_sdram_plat *plat)
{
hmc_ecc_writel(plat, 0, RSTHANDSHAKECTRL);
false, 1000, false);
}
-int emif_reset(struct altera_sdram_platdata *plat)
+int emif_reset(struct altera_sdram_plat *plat)
{
u32 c2s, s2c, ret;
* Calculate SDRAM device size based on SDRAM controller parameters.
* Size is specified in bytes.
*/
-phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat)
+phys_size_t sdram_calculate_size(struct altera_sdram_plat *plat)
{
u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
static int altera_sdram_of_to_plat(struct udevice *dev)
{
- struct altera_sdram_platdata *plat = dev->plat;
+ struct altera_sdram_plat *plat = dev->plat;
fdt_addr_t addr;
addr = dev_read_addr_index(dev, 0);
.of_match = altera_sdram_ids,
.ops = &altera_sdram_ops,
.of_to_plat = altera_sdram_of_to_plat,
- .plat_auto = sizeof(struct altera_sdram_platdata),
+ .plat_auto = sizeof(struct altera_sdram_plat),
.probe = altera_sdram_probe,
.priv_auto = sizeof(struct altera_sdram_priv),
};
struct reset_ctl_bulk resets;
};
-struct altera_sdram_platdata {
+struct altera_sdram_plat {
void __iomem *hmc;
void __iomem *ddr_sch;
void __iomem *iomhc;
#define FW_HMC_ADAPTOR_REG_ADDR 0xf8020004
#define FW_HMC_ADAPTOR_MPU_MASK BIT(0)
-u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg);
-u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg);
-u32 hmc_ecc_writel(struct altera_sdram_platdata *plat,
+u32 hmc_readl(struct altera_sdram_plat *plat, u32 reg);
+u32 hmc_ecc_readl(struct altera_sdram_plat *plat, u32 reg);
+u32 hmc_ecc_writel(struct altera_sdram_plat *plat,
u32 data, u32 reg);
-u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data,
+u32 ddr_sch_writel(struct altera_sdram_plat *plat, u32 data,
u32 reg);
-int emif_clear(struct altera_sdram_platdata *plat);
-int emif_reset(struct altera_sdram_platdata *plat);
+int emif_clear(struct altera_sdram_plat *plat);
+int emif_reset(struct altera_sdram_plat *plat);
int poll_hmc_clock_status(void);
void sdram_clear_mem(phys_addr_t addr, phys_size_t size);
void sdram_init_ecc_bits(struct bd_info *bd);
void sdram_size_check(struct bd_info *bd);
-phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat);
+phys_size_t sdram_calculate_size(struct altera_sdram_plat *plat);
int sdram_mmr_init_full(struct udevice *dev);
#endif /* _SDRAM_SOC64_H_ */
u32 direction; /* Direction register */
};
-struct altera_pio_platdata {
+struct altera_pio_plat {
struct altera_pio_regs *regs;
int gpio_count;
const char *bank_name;
static int altera_pio_direction_input(struct udevice *dev, unsigned pin)
{
- struct altera_pio_platdata *plat = dev_get_plat(dev);
+ struct altera_pio_plat *plat = dev_get_plat(dev);
struct altera_pio_regs *const regs = plat->regs;
clrbits_le32(®s->direction, 1 << pin);
static int altera_pio_direction_output(struct udevice *dev, unsigned pin,
int val)
{
- struct altera_pio_platdata *plat = dev_get_plat(dev);
+ struct altera_pio_plat *plat = dev_get_plat(dev);
struct altera_pio_regs *const regs = plat->regs;
if (val)
static int altera_pio_get_value(struct udevice *dev, unsigned pin)
{
- struct altera_pio_platdata *plat = dev_get_plat(dev);
+ struct altera_pio_plat *plat = dev_get_plat(dev);
struct altera_pio_regs *const regs = plat->regs;
return !!(readl(®s->data) & (1 << pin));
static int altera_pio_set_value(struct udevice *dev, unsigned pin, int val)
{
- struct altera_pio_platdata *plat = dev_get_plat(dev);
+ struct altera_pio_plat *plat = dev_get_plat(dev);
struct altera_pio_regs *const regs = plat->regs;
if (val)
static int altera_pio_probe(struct udevice *dev)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
- struct altera_pio_platdata *plat = dev_get_plat(dev);
+ struct altera_pio_plat *plat = dev_get_plat(dev);
uc_priv->gpio_count = plat->gpio_count;
uc_priv->bank_name = plat->bank_name;
static int altera_pio_of_to_plat(struct udevice *dev)
{
- struct altera_pio_platdata *plat = dev_get_plat(dev);
+ struct altera_pio_plat *plat = dev_get_plat(dev);
plat->regs = map_physmem(dev_read_addr(dev),
sizeof(struct altera_pio_regs),
.of_match = altera_pio_ids,
.ops = &altera_pio_ops,
.of_to_plat = altera_pio_of_to_plat,
- .plat_auto = sizeof(struct altera_pio_platdata),
+ .plat_auto = sizeof(struct altera_pio_plat),
.probe = altera_pio_probe,
};
static int at91_gpio_probe(struct udevice *dev)
{
struct at91_port_priv *port = dev_get_priv(dev);
- struct at91_port_platdata *plat = dev_get_plat(dev);
+ struct at91_port_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct clk clk;
int ret;
.id = UCLASS_GPIO,
#if CONFIG_IS_ENABLED(OF_CONTROL)
.of_match = at91_gpio_ids,
- .plat_auto = sizeof(struct at91_port_platdata),
+ .plat_auto = sizeof(struct at91_port_plat),
#endif
.ops = &gpio_at91_ops,
.probe = at91_gpio_probe,
u32 nbanks;
};
-struct atmel_pio4_platdata {
+struct atmel_pio4_plat {
struct atmel_pio4_port *reg_base;
};
static struct atmel_pio4_port *atmel_pio4_bank_base(struct udevice *dev,
u32 bank)
{
- struct atmel_pio4_platdata *plat = dev_get_plat(dev);
+ struct atmel_pio4_plat *plat = dev_get_plat(dev);
struct atmel_pio4_port *port_base =
(struct atmel_pio4_port *)((u32)plat->reg_base +
ATMEL_PIO_BANK_OFFSET * bank);
static int atmel_pio4_probe(struct udevice *dev)
{
- struct atmel_pio4_platdata *plat = dev_get_plat(dev);
+ struct atmel_pio4_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct atmel_pioctrl_data *pioctrl_data;
struct clk clk;
.probe = atmel_pio4_probe,
.bind = atmel_pio4_bind,
.of_match = atmel_pio4_ids,
- .plat_auto = sizeof(struct atmel_pio4_platdata),
+ .plat_auto = sizeof(struct atmel_pio4_plat),
};
#endif
static int bcm2835_gpio_probe(struct udevice *dev)
{
struct bcm2835_gpios *gpios = dev_get_priv(dev);
- struct bcm2835_gpio_platdata *plat = dev_get_plat(dev);
+ struct bcm2835_gpio_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
uc_priv->bank_name = "GPIO";
#if CONFIG_IS_ENABLED(OF_CONTROL)
static int bcm2835_gpio_of_to_plat(struct udevice *dev)
{
- struct bcm2835_gpio_platdata *plat = dev_get_plat(dev);
+ struct bcm2835_gpio_plat *plat = dev_get_plat(dev);
fdt_addr_t addr;
addr = dev_read_addr(dev);
.name = "gpio_bcm2835",
.id = UCLASS_GPIO,
.of_to_plat = of_match_ptr(bcm2835_gpio_of_to_plat),
- .plat_auto = sizeof(struct bcm2835_gpio_platdata),
+ .plat_auto = sizeof(struct bcm2835_gpio_plat),
.ops = &gpio_bcm2835_ops,
.probe = bcm2835_gpio_probe,
.flags = DM_FLAG_PRE_RELOC,
static int davinci_gpio_probe(struct udevice *dev)
{
struct davinci_gpio_bank *bank = dev_get_priv(dev);
- struct davinci_gpio_platdata *plat = dev_get_plat(dev);
+ struct davinci_gpio_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
static int davinci_gpio_of_to_plat(struct udevice *dev)
{
- struct davinci_gpio_platdata *plat = dev_get_plat(dev);
+ struct davinci_gpio_plat *plat = dev_get_plat(dev);
fdt_addr_t addr;
addr = dev_read_addr(dev);
.of_to_plat = of_match_ptr(davinci_gpio_of_to_plat),
.of_match = davinci_gpio_ids,
.bind = dm_scan_fdt_dev,
- .plat_auto = sizeof(struct davinci_gpio_platdata),
+ .plat_auto = sizeof(struct davinci_gpio_plat),
.probe = davinci_gpio_probe,
.priv_auto = sizeof(struct davinci_gpio_bank),
};
#if CONFIG_IS_ENABLED(DM_GPIO)
/* Information about a GPIO bank */
-struct davinci_gpio_platdata {
+struct davinci_gpio_plat {
int bank_index;
ulong base; /* address of registers in physical memory */
const char *port_name;
struct reset_ctl_bulk resets;
};
-struct gpio_dwapb_platdata {
+struct gpio_dwapb_plat {
const char *name;
int bank;
int pins;
static int dwapb_gpio_direction_input(struct udevice *dev, unsigned pin)
{
- struct gpio_dwapb_platdata *plat = dev_get_plat(dev);
+ struct gpio_dwapb_plat *plat = dev_get_plat(dev);
clrbits_le32(plat->base + GPIO_SWPORT_DDR(plat->bank), 1 << pin);
return 0;
static int dwapb_gpio_direction_output(struct udevice *dev, unsigned pin,
int val)
{
- struct gpio_dwapb_platdata *plat = dev_get_plat(dev);
+ struct gpio_dwapb_plat *plat = dev_get_plat(dev);
setbits_le32(plat->base + GPIO_SWPORT_DDR(plat->bank), 1 << pin);
static int dwapb_gpio_set_value(struct udevice *dev, unsigned pin, int val)
{
- struct gpio_dwapb_platdata *plat = dev_get_plat(dev);
+ struct gpio_dwapb_plat *plat = dev_get_plat(dev);
if (val)
setbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin);
static int dwapb_gpio_get_function(struct udevice *dev, unsigned offset)
{
- struct gpio_dwapb_platdata *plat = dev_get_plat(dev);
+ struct gpio_dwapb_plat *plat = dev_get_plat(dev);
u32 gpio;
gpio = readl(plat->base + GPIO_SWPORT_DDR(plat->bank));
static int dwapb_gpio_get_value(struct udevice *dev, unsigned pin)
{
- struct gpio_dwapb_platdata *plat = dev_get_plat(dev);
+ struct gpio_dwapb_plat *plat = dev_get_plat(dev);
u32 value;
if (dwapb_gpio_get_function(dev, pin) == GPIOF_OUTPUT)
static int gpio_dwapb_probe(struct udevice *dev)
{
struct gpio_dev_priv *priv = dev_get_uclass_priv(dev);
- struct gpio_dwapb_platdata *plat = dev->plat;
+ struct gpio_dwapb_plat *plat = dev->plat;
if (!plat) {
/* Reset on parent device only */
static int gpio_dwapb_bind(struct udevice *dev)
{
- struct gpio_dwapb_platdata *plat = dev_get_plat(dev);
+ struct gpio_dwapb_plat *plat = dev_get_plat(dev);
struct udevice *subdev;
fdt_addr_t base;
int ret, bank = 0;
static int gpio_dwapb_remove(struct udevice *dev)
{
- struct gpio_dwapb_platdata *plat = dev_get_plat(dev);
+ struct gpio_dwapb_plat *plat = dev_get_plat(dev);
struct gpio_dwapb_priv *priv = dev_get_priv(dev);
if (!plat && priv)
static int hi6220_gpio_probe(struct udevice *dev)
{
struct gpio_bank *bank = dev_get_priv(dev);
- struct hikey_gpio_platdata *plat = dev_get_plat(dev);
+ struct hikey_gpio_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev->uclass_priv;
char name[18], *str;
static int broadwell_gpio_probe(struct udevice *dev)
{
- struct broadwell_bank_platdata *plat = dev_get_plat(dev);
+ struct broadwell_bank_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct broadwell_bank_priv *priv = dev_get_priv(dev);
struct udevice *pinctrl;
static int broadwell_gpio_of_to_plat(struct udevice *dev)
{
- struct broadwell_bank_platdata *plat = dev_get_plat(dev);
+ struct broadwell_bank_plat *plat = dev_get_plat(dev);
u32 gpiobase;
int bank;
int ret;
.of_to_plat = broadwell_gpio_of_to_plat,
.probe = broadwell_gpio_probe,
.priv_auto = sizeof(struct broadwell_bank_priv),
- .plat_auto = sizeof(struct broadwell_bank_platdata),
+ .plat_auto = sizeof(struct broadwell_bank_plat),
};
static int gpio_ich6_of_to_plat(struct udevice *dev)
{
- struct ich6_bank_platdata *plat = dev_get_plat(dev);
+ struct ich6_bank_plat *plat = dev_get_plat(dev);
u32 gpiobase;
int offset;
int ret;
static int ich6_gpio_probe(struct udevice *dev)
{
- struct ich6_bank_platdata *plat = dev_get_plat(dev);
+ struct ich6_bank_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct ich6_bank_priv *bank = dev_get_priv(dev);
const void *prop;
.of_to_plat = gpio_ich6_of_to_plat,
.probe = ich6_gpio_probe,
.priv_auto = sizeof(struct ich6_bank_priv),
- .plat_auto = sizeof(struct ich6_bank_platdata),
+ .plat_auto = sizeof(struct ich6_bank_plat),
};
* @name: gpio device name, ex GPIO0, GPIO1
* @ngpios: total number of gpios
*/
-struct iproc_gpio_platdata {
+struct iproc_gpio_plat {
struct udevice *pinctrl_dev;
struct list_head gpiomap;
void __iomem *base;
* @gpio: GPIO pin
* @set: set or clear
*/
-static inline void iproc_gpio_set_bit(struct iproc_gpio_platdata *plat,
+static inline void iproc_gpio_set_bit(struct iproc_gpio_plat *plat,
u32 reg, u32 gpio, bool set)
{
u32 offset = GPIO_REG(gpio, reg);
(set ? BIT(shift) : 0));
}
-static inline bool iproc_gpio_get_bit(struct iproc_gpio_platdata *plat,
+static inline bool iproc_gpio_get_bit(struct iproc_gpio_plat *plat,
u32 reg, u32 gpio)
{
u32 offset = GPIO_REG(gpio, reg);
* @plat: iproc GPIO device
* @gpio: GPIO pin
*/
-static u32 iproc_get_pctrl_from_gpio(struct iproc_gpio_platdata *plat, u32 gpio)
+static u32 iproc_get_pctrl_from_gpio(struct iproc_gpio_plat *plat, u32 gpio)
{
struct iproc_gpio_pctrl_map *range = NULL;
struct list_head *pos, *tmp;
*/
static int iproc_get_gpio_pctrl_mapping(struct udevice *dev)
{
- struct iproc_gpio_platdata *plat = dev_get_plat(dev);
+ struct iproc_gpio_plat *plat = dev_get_plat(dev);
struct iproc_gpio_pctrl_map *range = NULL;
struct ofnode_phandle_args args;
int index = 0, ret;
static int iproc_gpio_request(struct udevice *dev, u32 gpio, const char *label)
{
- struct iproc_gpio_platdata *plat = dev_get_plat(dev);
+ struct iproc_gpio_plat *plat = dev_get_plat(dev);
u32 pctrl;
/* nothing to do if there is no corresponding pinctrl device */
static int iproc_gpio_direction_input(struct udevice *dev, u32 gpio)
{
- struct iproc_gpio_platdata *plat = dev_get_plat(dev);
+ struct iproc_gpio_plat *plat = dev_get_plat(dev);
iproc_gpio_set_bit(plat, OUT_EN_OFFSET, gpio, false);
dev_dbg(dev, "gpio:%u set input\n", gpio);
static int iproc_gpio_direction_output(struct udevice *dev, u32 gpio, int value)
{
- struct iproc_gpio_platdata *plat = dev_get_plat(dev);
+ struct iproc_gpio_plat *plat = dev_get_plat(dev);
iproc_gpio_set_bit(plat, OUT_EN_OFFSET, gpio, true);
iproc_gpio_set_bit(plat, DATA_OUT_OFFSET, gpio, value);
static int iproc_gpio_get_value(struct udevice *dev, u32 gpio)
{
- struct iproc_gpio_platdata *plat = dev_get_plat(dev);
+ struct iproc_gpio_plat *plat = dev_get_plat(dev);
int value;
value = iproc_gpio_get_bit(plat, DATA_IN_OFFSET, gpio);
static int iproc_gpio_set_value(struct udevice *dev, u32 gpio, int value)
{
- struct iproc_gpio_platdata *plat = dev_get_plat(dev);
+ struct iproc_gpio_plat *plat = dev_get_plat(dev);
if (iproc_gpio_get_bit(plat, OUT_EN_OFFSET, gpio))
iproc_gpio_set_bit(plat, DATA_OUT_OFFSET, gpio, value);
static int iproc_gpio_get_function(struct udevice *dev, u32 gpio)
{
- struct iproc_gpio_platdata *plat = dev_get_plat(dev);
+ struct iproc_gpio_plat *plat = dev_get_plat(dev);
if (iproc_gpio_get_bit(plat, OUT_EN_OFFSET, gpio))
return GPIOF_OUTPUT;
static int iproc_gpio_of_to_plat(struct udevice *dev)
{
- struct iproc_gpio_platdata *plat = dev_get_plat(dev);
+ struct iproc_gpio_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
int ret;
char name[10];
.of_match = iproc_gpio_ids,
.ops = &iproc_gpio_ops,
.of_to_plat = iproc_gpio_of_to_plat,
- .plat_auto = sizeof(struct iproc_gpio_platdata),
+ .plat_auto = sizeof(struct iproc_gpio_plat),
};
}
#endif
-static int mpc83xx_spisel_boot_platdata_to_priv(struct udevice *dev)
+static int mpc83xx_spisel_boot_plat_to_priv(struct udevice *dev)
{
struct mpc83xx_spisel_boot *priv = dev_get_priv(dev);
struct mpc8xxx_gpio_plat *plat = dev_get_plat(dev);
struct mpc83xx_spisel_boot *data = dev_get_priv(dev);
char name[32], *str;
- mpc83xx_spisel_boot_platdata_to_priv(dev);
+ mpc83xx_spisel_boot_plat_to_priv(dev);
snprintf(name, sizeof(name), "MPC@%lx_", data->addr);
str = strdup(name);
}
#endif
-static int mpc8xxx_gpio_platdata_to_priv(struct udevice *dev)
+static int mpc8xxx_gpio_plat_to_priv(struct udevice *dev)
{
struct mpc8xxx_gpio_data *priv = dev_get_priv(dev);
struct mpc8xxx_gpio_plat *plat = dev_get_plat(dev);
struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
char name[32], *str;
- mpc8xxx_gpio_platdata_to_priv(dev);
+ mpc8xxx_gpio_plat_to_priv(dev);
snprintf(name, sizeof(name), "MPC@%lx_", data->addr);
str = strdup(name);
static void __iomem *mediatek_gpio_membase;
-struct mediatek_gpio_platdata {
+struct mediatek_gpio_plat {
char bank_name[3]; /* Name of bank, e.g. "PA", "PB" etc */
int gpio_count;
int bank;
};
-static u32 reg_offs(struct mediatek_gpio_platdata *plat, int reg)
+static u32 reg_offs(struct mediatek_gpio_plat *plat, int reg)
{
return (reg * 0x10) + (plat->bank * 0x4);
}
static int mediatek_gpio_get_value(struct udevice *dev, unsigned int offset)
{
- struct mediatek_gpio_platdata *plat = dev_get_plat(dev);
+ struct mediatek_gpio_plat *plat = dev_get_plat(dev);
return !!(ioread32(mediatek_gpio_membase +
reg_offs(plat, GPIO_REG_DATA)) & BIT(offset));
static int mediatek_gpio_set_value(struct udevice *dev, unsigned int offset,
int value)
{
- struct mediatek_gpio_platdata *plat = dev_get_plat(dev);
+ struct mediatek_gpio_plat *plat = dev_get_plat(dev);
iowrite32(BIT(offset), mediatek_gpio_membase +
reg_offs(plat, value ? GPIO_REG_DSET : GPIO_REG_DCLR));
static int mediatek_gpio_direction_input(struct udevice *dev, unsigned int offset)
{
- struct mediatek_gpio_platdata *plat = dev_get_plat(dev);
+ struct mediatek_gpio_plat *plat = dev_get_plat(dev);
clrbits_le32(mediatek_gpio_membase + reg_offs(plat, GPIO_REG_CTRL),
BIT(offset));
static int mediatek_gpio_direction_output(struct udevice *dev, unsigned int offset,
int value)
{
- struct mediatek_gpio_platdata *plat = dev_get_plat(dev);
+ struct mediatek_gpio_plat *plat = dev_get_plat(dev);
setbits_le32(mediatek_gpio_membase + reg_offs(plat, GPIO_REG_CTRL),
BIT(offset));
static int mediatek_gpio_get_function(struct udevice *dev, unsigned int offset)
{
- struct mediatek_gpio_platdata *plat = dev_get_plat(dev);
+ struct mediatek_gpio_plat *plat = dev_get_plat(dev);
u32 t;
t = ioread32(mediatek_gpio_membase + reg_offs(plat, GPIO_REG_CTRL));
static int gpio_mediatek_probe(struct udevice *dev)
{
- struct mediatek_gpio_platdata *plat = dev_get_plat(dev);
+ struct mediatek_gpio_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
/* Tell the uclass how many GPIOs we have */
*/
static int gpio_mediatek_bind(struct udevice *parent)
{
- struct mediatek_gpio_platdata *plat = parent->plat;
+ struct mediatek_gpio_plat *plat = parent->plat;
ofnode node;
int bank = 0;
int ret;
for (node = dev_read_first_subnode(parent); ofnode_valid(node);
node = dev_read_next_subnode(node)) {
- struct mediatek_gpio_platdata *plat;
+ struct mediatek_gpio_plat *plat;
struct udevice *dev;
plat = calloc(1, sizeof(*plat));
* Bank 4: 0-20 -> 21 PINS
*/
-struct mxs_gpio_platdata {
+struct mxs_gpio_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_fsl_imx23_gpio dtplat;
#endif
static int mxs_gpio_probe(struct udevice *dev)
{
- struct mxs_gpio_platdata *plat = dev_get_plat(dev);
+ struct mxs_gpio_plat *plat = dev_get_plat(dev);
struct mxs_gpio_priv *priv = dev_get_priv(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
char name[16], *str;
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
static int mxs_of_to_plat(struct udevice *dev)
{
- struct mxs_gpio_platdata *plat = dev->plat;
+ struct mxs_gpio_plat *plat = dev->plat;
struct fdtdec_phandle_args args;
int node = dev_of_offset(dev);
int ret;
.ops = &gpio_mxs_ops,
.probe = mxs_gpio_probe,
.priv_auto = sizeof(struct mxs_gpio_priv),
- .plat_auto = sizeof(struct mxs_gpio_platdata),
+ .plat_auto = sizeof(struct mxs_gpio_plat),
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.of_match = mxs_gpio_ids,
.of_to_plat = mxs_of_to_plat,
u32 pad; /* Alive GPIO Input Value Register */
};
-struct nx_gpio_platdata {
+struct nx_gpio_plat {
void *regs;
int gpio_count;
const char *bank_name;
static int nx_alive_gpio_is_check(struct udevice *dev)
{
- struct nx_gpio_platdata *plat = dev_get_plat(dev);
+ struct nx_gpio_plat *plat = dev_get_plat(dev);
const char *bank_name = plat->bank_name;
if (!strcmp(bank_name, "gpio_alv"))
static int nx_alive_gpio_direction_input(struct udevice *dev, unsigned int pin)
{
- struct nx_gpio_platdata *plat = dev_get_plat(dev);
+ struct nx_gpio_plat *plat = dev_get_plat(dev);
struct nx_alive_gpio_regs *const regs = plat->regs;
setbits_le32(®s->outputenb_reset, 1 << pin);
static int nx_alive_gpio_direction_output(struct udevice *dev, unsigned int pin,
int val)
{
- struct nx_gpio_platdata *plat = dev_get_plat(dev);
+ struct nx_gpio_plat *plat = dev_get_plat(dev);
struct nx_alive_gpio_regs *const regs = plat->regs;
if (val)
static int nx_alive_gpio_get_value(struct udevice *dev, unsigned int pin)
{
- struct nx_gpio_platdata *plat = dev_get_plat(dev);
+ struct nx_gpio_plat *plat = dev_get_plat(dev);
struct nx_alive_gpio_regs *const regs = plat->regs;
unsigned int mask = 1UL << pin;
unsigned int value;
static int nx_alive_gpio_set_value(struct udevice *dev, unsigned int pin,
int val)
{
- struct nx_gpio_platdata *plat = dev_get_plat(dev);
+ struct nx_gpio_plat *plat = dev_get_plat(dev);
struct nx_alive_gpio_regs *const regs = plat->regs;
if (val)
static int nx_alive_gpio_get_function(struct udevice *dev, unsigned int pin)
{
- struct nx_gpio_platdata *plat = dev_get_plat(dev);
+ struct nx_gpio_plat *plat = dev_get_plat(dev);
struct nx_alive_gpio_regs *const regs = plat->regs;
unsigned int mask = (1UL << pin);
unsigned int output;
static int nx_gpio_direction_input(struct udevice *dev, unsigned int pin)
{
- struct nx_gpio_platdata *plat = dev_get_plat(dev);
+ struct nx_gpio_plat *plat = dev_get_plat(dev);
struct nx_gpio_regs *const regs = plat->regs;
if (nx_alive_gpio_is_check(dev))
static int nx_gpio_direction_output(struct udevice *dev, unsigned int pin,
int val)
{
- struct nx_gpio_platdata *plat = dev_get_plat(dev);
+ struct nx_gpio_plat *plat = dev_get_plat(dev);
struct nx_gpio_regs *const regs = plat->regs;
if (nx_alive_gpio_is_check(dev))
static int nx_gpio_get_value(struct udevice *dev, unsigned int pin)
{
- struct nx_gpio_platdata *plat = dev_get_plat(dev);
+ struct nx_gpio_plat *plat = dev_get_plat(dev);
struct nx_gpio_regs *const regs = plat->regs;
unsigned int mask = 1UL << pin;
unsigned int value;
static int nx_gpio_set_value(struct udevice *dev, unsigned int pin, int val)
{
- struct nx_gpio_platdata *plat = dev_get_plat(dev);
+ struct nx_gpio_plat *plat = dev_get_plat(dev);
struct nx_gpio_regs *const regs = plat->regs;
if (nx_alive_gpio_is_check(dev))
static int nx_gpio_get_function(struct udevice *dev, unsigned int pin)
{
- struct nx_gpio_platdata *plat = dev_get_plat(dev);
+ struct nx_gpio_plat *plat = dev_get_plat(dev);
struct nx_gpio_regs *const regs = plat->regs;
unsigned int mask = (1UL << pin);
unsigned int output;
static int nx_gpio_probe(struct udevice *dev)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
- struct nx_gpio_platdata *plat = dev_get_plat(dev);
+ struct nx_gpio_plat *plat = dev_get_plat(dev);
uc_priv->gpio_count = plat->gpio_count;
uc_priv->bank_name = plat->bank_name;
static int nx_gpio_of_to_plat(struct udevice *dev)
{
- struct nx_gpio_platdata *plat = dev_get_plat(dev);
+ struct nx_gpio_plat *plat = dev_get_plat(dev);
plat->regs = map_physmem(devfdt_get_addr(dev),
sizeof(struct nx_gpio_regs),
.of_match = nx_gpio_ids,
.ops = &nx_gpio_ops,
.of_to_plat = nx_gpio_of_to_plat,
- .plat_auto = sizeof(struct nx_gpio_platdata),
+ .plat_auto = sizeof(struct nx_gpio_plat),
.probe = nx_gpio_probe,
};
static int omap_gpio_probe(struct udevice *dev)
{
struct gpio_bank *bank = dev_get_priv(dev);
- struct omap_gpio_platdata *plat = dev_get_plat(dev);
+ struct omap_gpio_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
char name[18], *str;
#if !CONFIG_IS_ENABLED(OF_CONTROL)
static int omap_gpio_bind(struct udevice *dev)
{
- struct omap_gpio_platdata *plat = dev_get_plat(dev);
+ struct omap_gpio_plat *plat = dev_get_plat(dev);
fdt_addr_t base_addr;
if (plat)
static int omap_gpio_of_to_plat(struct udevice *dev)
{
- struct omap_gpio_platdata *plat = dev_get_plat(dev);
+ struct omap_gpio_plat *plat = dev_get_plat(dev);
fdt_addr_t addr;
addr = dev_read_addr(dev);
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
.of_match = omap_gpio_ids,
.of_to_plat = of_match_ptr(omap_gpio_of_to_plat),
- .plat_auto = sizeof(struct omap_gpio_platdata),
+ .plat_auto = sizeof(struct omap_gpio_plat),
#endif
#else
.bind = omap_gpio_bind,
return pcf8575_direction_output(dev, offset, value);
}
-static int pcf8575_ofdata_platdata(struct udevice *dev)
+static int pcf8575_ofdata_plat(struct udevice *dev)
{
struct pcf8575_chip *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
.id = UCLASS_GPIO,
.ops = &pcf8575_gpio_ops,
.of_match = pcf8575_gpio_ids,
- .of_to_plat = pcf8575_ofdata_platdata,
+ .of_to_plat = pcf8575_ofdata_plat,
.probe = pcf8575_gpio_probe,
.plat_auto = sizeof(struct pcf8575_chip),
};
#define RATE_SET(gpio) (0x1 << (gpio + 16))
/* Platform data for each bank */
-struct exynos_gpio_platdata {
+struct exynos_gpio_plat {
struct s5p_gpio_bank *bank;
const char *bank_name; /* Name of port, e.g. 'gpa0" */
};
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct exynos_bank_info *priv = dev->priv;
- struct exynos_gpio_platdata *plat = dev->plat;
+ struct exynos_gpio_plat *plat = dev->plat;
/* Only child devices have ports */
if (!plat)
*/
static int gpio_exynos_bind(struct udevice *parent)
{
- struct exynos_gpio_platdata *plat = parent->plat;
+ struct exynos_gpio_plat *plat = parent->plat;
struct s5p_gpio_bank *bank, *base;
const void *blob = gd->fdt_blob;
int node;
for (node = fdt_first_subnode(blob, dev_of_offset(parent)), bank = base;
node > 0;
node = fdt_next_subnode(blob, node), bank++) {
- struct exynos_gpio_platdata *plat;
+ struct exynos_gpio_plat *plat;
struct udevice *dev;
fdt_addr_t reg;
int ret;
static int sifive_gpio_probe(struct udevice *dev)
{
- struct sifive_gpio_platdata *plat = dev_get_plat(dev);
+ struct sifive_gpio_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
char name[18], *str;
static int sifive_gpio_direction_input(struct udevice *dev, u32 offset)
{
- struct sifive_gpio_platdata *plat = dev_get_plat(dev);
+ struct sifive_gpio_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
if (offset > uc_priv->gpio_count)
static int sifive_gpio_direction_output(struct udevice *dev, u32 offset,
int value)
{
- struct sifive_gpio_platdata *plat = dev_get_plat(dev);
+ struct sifive_gpio_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
if (offset > uc_priv->gpio_count)
static int sifive_gpio_get_value(struct udevice *dev, u32 offset)
{
- struct sifive_gpio_platdata *plat = dev_get_plat(dev);
+ struct sifive_gpio_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
int val;
int dir;
static int sifive_gpio_set_value(struct udevice *dev, u32 offset, int value)
{
- struct sifive_gpio_platdata *plat = dev_get_plat(dev);
+ struct sifive_gpio_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
if (offset > uc_priv->gpio_count)
static int sifive_gpio_get_function(struct udevice *dev, unsigned int offset)
{
- struct sifive_gpio_platdata *plat = dev_get_plat(dev);
+ struct sifive_gpio_plat *plat = dev_get_plat(dev);
u32 outdir, indir, val;
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
static int sifive_gpio_of_to_plat(struct udevice *dev)
{
- struct sifive_gpio_platdata *plat = dev_get_plat(dev);
+ struct sifive_gpio_plat *plat = dev_get_plat(dev);
fdt_addr_t addr;
addr = dev_read_addr(dev);
.id = UCLASS_GPIO,
.of_match = sifive_gpio_match,
.of_to_plat = of_match_ptr(sifive_gpio_of_to_plat),
- .plat_auto = sizeof(struct sifive_gpio_platdata),
+ .plat_auto = sizeof(struct sifive_gpio_plat),
.ops = &sifive_gpio_ops,
.probe = sifive_gpio_probe,
};
#define SUNXI_GPIOS_PER_BANK SUNXI_GPIO_A_NR
-struct sunxi_gpio_platdata {
+struct sunxi_gpio_plat {
struct sunxi_gpio *regs;
const char *bank_name; /* Name of bank, e.g. "B" */
int gpio_count;
static int sunxi_gpio_direction_input(struct udevice *dev, unsigned offset)
{
- struct sunxi_gpio_platdata *plat = dev_get_plat(dev);
+ struct sunxi_gpio_plat *plat = dev_get_plat(dev);
sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_INPUT);
static int sunxi_gpio_direction_output(struct udevice *dev, unsigned offset,
int value)
{
- struct sunxi_gpio_platdata *plat = dev_get_plat(dev);
+ struct sunxi_gpio_plat *plat = dev_get_plat(dev);
u32 num = GPIO_NUM(offset);
sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_OUTPUT);
static int sunxi_gpio_get_value(struct udevice *dev, unsigned offset)
{
- struct sunxi_gpio_platdata *plat = dev_get_plat(dev);
+ struct sunxi_gpio_plat *plat = dev_get_plat(dev);
u32 num = GPIO_NUM(offset);
unsigned dat;
static int sunxi_gpio_set_value(struct udevice *dev, unsigned offset,
int value)
{
- struct sunxi_gpio_platdata *plat = dev_get_plat(dev);
+ struct sunxi_gpio_plat *plat = dev_get_plat(dev);
u32 num = GPIO_NUM(offset);
clrsetbits_le32(&plat->regs->dat, 1 << num, value ? (1 << num) : 0);
static int sunxi_gpio_get_function(struct udevice *dev, unsigned offset)
{
- struct sunxi_gpio_platdata *plat = dev_get_plat(dev);
+ struct sunxi_gpio_plat *plat = dev_get_plat(dev);
int func;
func = sunxi_gpio_get_cfgbank(plat->regs, offset);
static int gpio_sunxi_probe(struct udevice *dev)
{
- struct sunxi_gpio_platdata *plat = dev_get_plat(dev);
+ struct sunxi_gpio_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
/* Tell the uclass how many GPIOs we have */
{
struct sunxi_gpio_soc_data *soc_data =
(struct sunxi_gpio_soc_data *)dev_get_driver_data(parent);
- struct sunxi_gpio_platdata *plat = parent->plat;
+ struct sunxi_gpio_plat *plat = parent->plat;
struct sunxi_gpio_reg *ctlr;
int bank, ret;
ctlr = dev_read_addr_ptr(parent);
for (bank = 0; bank < soc_data->no_banks; bank++) {
- struct sunxi_gpio_platdata *plat;
+ struct sunxi_gpio_plat *plat;
struct udevice *dev;
plat = calloc(1, sizeof(*plat));
uint32_t port_count;
};
-struct tegra186_gpio_platdata {
+struct tegra186_gpio_plat {
const char *name;
uint32_t *regs;
};
static uint32_t *tegra186_gpio_reg(struct udevice *dev, uint32_t reg,
uint32_t gpio)
{
- struct tegra186_gpio_platdata *plat = dev->plat;
+ struct tegra186_gpio_plat *plat = dev->plat;
uint32_t index = (reg + (gpio * TEGRA186_GPIO_PER_GPIO_STRIDE)) / 4;
return &(plat->regs[index]);
*/
static int tegra186_gpio_bind(struct udevice *parent)
{
- struct tegra186_gpio_platdata *parent_plat = parent->plat;
+ struct tegra186_gpio_plat *parent_plat = parent->plat;
struct tegra186_gpio_ctlr_data *ctlr_data =
(struct tegra186_gpio_ctlr_data *)dev_get_driver_data(parent);
uint32_t *regs;
return -EINVAL;
for (port = 0; port < ctlr_data->port_count; port++) {
- struct tegra186_gpio_platdata *plat;
+ struct tegra186_gpio_plat *plat;
struct udevice *dev;
plat = calloc(1, sizeof(*plat));
static int tegra186_gpio_probe(struct udevice *dev)
{
- struct tegra186_gpio_platdata *plat = dev->plat;
+ struct tegra186_gpio_plat *plat = dev->plat;
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
/* Only child devices have ports */
static const int DIRECTION_INPUT = 0;
static const int DIRECTION_OUTPUT = 1;
-struct tegra_gpio_platdata {
+struct tegra_gpio_plat {
struct gpio_ctlr_bank *bank;
const char *port_name; /* Name of port, e.g. "B" */
int base_gpio; /* Port number for this port (0, 1,.., n-1) */
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct tegra_port_info *priv = dev->priv;
- struct tegra_gpio_platdata *plat = dev->plat;
+ struct tegra_gpio_plat *plat = dev->plat;
/* Only child devices have ports */
if (!plat)
*/
static int gpio_tegra_bind(struct udevice *parent)
{
- struct tegra_gpio_platdata *plat = parent->plat;
+ struct tegra_gpio_plat *plat = parent->plat;
struct gpio_ctlr *ctlr;
int bank_count;
int bank;
int port;
for (port = 0; port < TEGRA_PORTS_PER_BANK; port++) {
- struct tegra_gpio_platdata *plat;
+ struct tegra_gpio_plat *plat;
struct udevice *dev;
int base_port;
static int vybrid_gpio_probe(struct udevice *dev)
{
struct vybrid_gpios *gpios = dev_get_priv(dev);
- struct vybrid_gpio_platdata *plat = dev_get_plat(dev);
+ struct vybrid_gpio_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
uc_priv->bank_name = plat->port_name;
return 0;
}
-static int vybrid_gpio_odata_to_platdata(struct udevice *dev)
+static int vybrid_gpio_odata_to_plat(struct udevice *dev)
{
- struct vybrid_gpio_platdata *plat = dev_get_plat(dev);
+ struct vybrid_gpio_plat *plat = dev_get_plat(dev);
fdt_addr_t base_addr;
base_addr = dev_read_addr(dev);
.id = UCLASS_GPIO,
.ops = &gpio_vybrid_ops,
.of_match = vybrid_gpio_ids,
- .of_to_plat = vybrid_gpio_odata_to_platdata,
+ .of_to_plat = vybrid_gpio_odata_to_plat,
.probe = vybrid_gpio_probe,
.priv_auto = sizeof(struct vybrid_gpios),
- .plat_auto = sizeof(struct vybrid_gpio_platdata),
+ .plat_auto = sizeof(struct vybrid_gpio_plat),
};
u32 gpiodir;
};
-struct xilinx_gpio_platdata {
+struct xilinx_gpio_plat {
struct gpio_regs *regs;
int bank_max[XILINX_GPIO_MAX_BANK];
int bank_input[XILINX_GPIO_MAX_BANK];
static int xilinx_gpio_get_bank_pin(unsigned offset, u32 *bank_num,
u32 *bank_pin_num, struct udevice *dev)
{
- struct xilinx_gpio_platdata *plat = dev_get_plat(dev);
+ struct xilinx_gpio_plat *plat = dev_get_plat(dev);
u32 bank, max_pins;
/* the first gpio is 0 not 1 */
u32 pin_num = offset;
static int xilinx_gpio_set_value(struct udevice *dev, unsigned offset,
int value)
{
- struct xilinx_gpio_platdata *plat = dev_get_plat(dev);
+ struct xilinx_gpio_plat *plat = dev_get_plat(dev);
struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
int val, ret;
u32 bank, pin;
static int xilinx_gpio_get_value(struct udevice *dev, unsigned offset)
{
- struct xilinx_gpio_platdata *plat = dev_get_plat(dev);
+ struct xilinx_gpio_plat *plat = dev_get_plat(dev);
struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
int val, ret;
u32 bank, pin;
static int xilinx_gpio_get_function(struct udevice *dev, unsigned offset)
{
- struct xilinx_gpio_platdata *plat = dev_get_plat(dev);
+ struct xilinx_gpio_plat *plat = dev_get_plat(dev);
int val, ret;
u32 bank, pin;
static int xilinx_gpio_direction_output(struct udevice *dev, unsigned offset,
int value)
{
- struct xilinx_gpio_platdata *plat = dev_get_plat(dev);
+ struct xilinx_gpio_plat *plat = dev_get_plat(dev);
int val, ret;
u32 bank, pin;
static int xilinx_gpio_direction_input(struct udevice *dev, unsigned offset)
{
- struct xilinx_gpio_platdata *plat = dev_get_plat(dev);
+ struct xilinx_gpio_plat *plat = dev_get_plat(dev);
int val, ret;
u32 bank, pin;
static int xilinx_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
struct ofnode_phandle_args *args)
{
- struct xilinx_gpio_platdata *plat = dev_get_plat(dev);
+ struct xilinx_gpio_plat *plat = dev_get_plat(dev);
desc->offset = args->args[0];
static int xilinx_gpio_probe(struct udevice *dev)
{
- struct xilinx_gpio_platdata *plat = dev_get_plat(dev);
+ struct xilinx_gpio_plat *plat = dev_get_plat(dev);
struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
const void *label_ptr;
static int xilinx_gpio_of_to_plat(struct udevice *dev)
{
- struct xilinx_gpio_platdata *plat = dev_get_plat(dev);
+ struct xilinx_gpio_plat *plat = dev_get_plat(dev);
int is_dual;
plat->regs = (struct gpio_regs *)dev_read_addr(dev);
.of_match = xilinx_gpio_ids,
.of_to_plat = xilinx_gpio_of_to_plat,
.probe = xilinx_gpio_probe,
- .plat_auto = sizeof(struct xilinx_gpio_platdata),
+ .plat_auto = sizeof(struct xilinx_gpio_plat),
.priv_auto = sizeof(struct xilinx_gpio_privdata),
};
#define PMC_GPIO_NR_GPIOS 116
#define PMC_GPIO_MAX_BANK 5
-struct zynq_gpio_platdata {
+struct zynq_gpio_plat {
phys_addr_t base;
const struct zynq_platform_data *p_data;
};
unsigned int *bank_pin_num,
struct udevice *dev)
{
- struct zynq_gpio_platdata *plat = dev_get_plat(dev);
+ struct zynq_gpio_plat *plat = dev_get_plat(dev);
u32 bank;
for (bank = 0; bank < plat->p_data->max_bank; bank++) {
static int gpio_is_valid(unsigned gpio, struct udevice *dev)
{
- struct zynq_gpio_platdata *plat = dev_get_plat(dev);
+ struct zynq_gpio_plat *plat = dev_get_plat(dev);
return gpio < plat->p_data->ngpio;
}
{
u32 data;
unsigned int bank_num, bank_pin_num;
- struct zynq_gpio_platdata *plat = dev_get_plat(dev);
+ struct zynq_gpio_plat *plat = dev_get_plat(dev);
if (check_gpio(gpio, dev) < 0)
return -1;
static int zynq_gpio_set_value(struct udevice *dev, unsigned gpio, int value)
{
unsigned int reg_offset, bank_num, bank_pin_num;
- struct zynq_gpio_platdata *plat = dev_get_plat(dev);
+ struct zynq_gpio_plat *plat = dev_get_plat(dev);
if (check_gpio(gpio, dev) < 0)
return -1;
{
u32 reg;
unsigned int bank_num, bank_pin_num;
- struct zynq_gpio_platdata *plat = dev_get_plat(dev);
+ struct zynq_gpio_plat *plat = dev_get_plat(dev);
if (check_gpio(gpio, dev) < 0)
return -1;
{
u32 reg;
unsigned int bank_num, bank_pin_num;
- struct zynq_gpio_platdata *plat = dev_get_plat(dev);
+ struct zynq_gpio_plat *plat = dev_get_plat(dev);
if (check_gpio(gpio, dev) < 0)
return -1;
{
u32 reg;
unsigned int bank_num, bank_pin_num;
- struct zynq_gpio_platdata *plat = dev_get_plat(dev);
+ struct zynq_gpio_plat *plat = dev_get_plat(dev);
if (check_gpio(offset, dev) < 0)
return -1;
static int zynq_gpio_probe(struct udevice *dev)
{
- struct zynq_gpio_platdata *plat = dev_get_plat(dev);
+ struct zynq_gpio_plat *plat = dev_get_plat(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
const void *label_ptr;
static int zynq_gpio_of_to_plat(struct udevice *dev)
{
- struct zynq_gpio_platdata *plat = dev_get_plat(dev);
+ struct zynq_gpio_plat *plat = dev_get_plat(dev);
plat->base = (phys_addr_t)dev_read_addr(dev);
.of_match = zynq_gpio_ids,
.of_to_plat = zynq_gpio_of_to_plat,
.probe = zynq_gpio_probe,
- .plat_auto = sizeof(struct zynq_gpio_platdata),
+ .plat_auto = sizeof(struct zynq_gpio_plat),
};
* i2c emulation works using an 'emul' node at the bus level. Each device in
* that node is in the UCLASS_I2C_EMUL uclass, and emulates one i2c device. A
* pointer to the device it emulates is in the 'dev' property of the emul device
- * uclass plat (struct i2c_emul_platdata), put there by i2c_emul_find().
+ * uclass plat (struct i2c_emul_plat), put there by i2c_emul_find().
* When sandbox wants an emulator for a device, it calls i2c_emul_find() which
* searches for the emulator with the correct address. To find the device for an
* emulator, call i2c_emul_get_device().
*/
/**
- * struct i2c_emul_uc_platdata - information about the emulator for this device
+ * struct i2c_emul_uc_plat - information about the emulator for this device
*
* This is used by devices in UCLASS_I2C_EMUL to record information about the
* device being emulated. It is accessible with dev_get_uclass_plat()
*
* @dev: Device being emulated
*/
-struct i2c_emul_uc_platdata {
+struct i2c_emul_uc_plat {
struct udevice *dev;
};
struct udevice *i2c_emul_get_device(struct udevice *emul)
{
- struct i2c_emul_uc_platdata *uc_plat = dev_get_uclass_plat(emul);
+ struct i2c_emul_uc_plat *uc_plat = dev_get_uclass_plat(emul);
return uc_plat->dev;
}
int i2c_emul_find(struct udevice *dev, struct udevice **emulp)
{
- struct i2c_emul_uc_platdata *uc_plat;
+ struct i2c_emul_uc_plat *uc_plat;
struct udevice *emul;
int ret;
UCLASS_DRIVER(i2c_emul) = {
.id = UCLASS_I2C_EMUL,
.name = "i2c_emul",
- .per_device_plat_auto = sizeof(struct i2c_emul_uc_platdata),
+ .per_device_plat_auto = sizeof(struct i2c_emul_uc_plat),
};
/*
static int omap_i2c_probe(struct udevice *bus)
{
struct omap_i2c *priv = dev_get_priv(bus);
- struct omap_i2c_platdata *plat = dev_get_plat(bus);
+ struct omap_i2c_plat *plat = dev_get_plat(bus);
priv->speed = plat->speed;
priv->regs = map_physmem(plat->base, sizeof(void *),
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
static int omap_i2c_of_to_plat(struct udevice *bus)
{
- struct omap_i2c_platdata *plat = dev_get_plat(bus);
+ struct omap_i2c_plat *plat = dev_get_plat(bus);
plat->base = dev_read_addr(bus);
plat->speed = dev_read_u32_default(bus, "clock-frequency",
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.of_match = omap_i2c_ids,
.of_to_plat = omap_i2c_of_to_plat,
- .plat_auto = sizeof(struct omap_i2c_platdata),
+ .plat_auto = sizeof(struct omap_i2c_plat),
#endif
.probe = omap_i2c_probe,
.priv_auto = sizeof(struct omap_i2c),
};
/* LED_control structures */
-struct cortina_led_platdata {
+struct cortina_led_plat {
void __iomem *ctrl_regs;
u16 rate1; /* blink rate setting 0 */
u16 rate2; /* blink rate setting 1 */
/* Top-level LED node */
if (!uc_plat->label) {
- struct cortina_led_platdata *plt = dev_get_plat(dev);
+ struct cortina_led_plat *plt = dev_get_plat(dev);
plt->rate1 =
dev_read_u32_default(dev, "Cortina,blink-rate1", 256);
/* Top-level LED node */
if (!uc_plat->label) {
- struct cortina_led_platdata *plat = dev_get_plat(dev);
+ struct cortina_led_plat *plat = dev_get_plat(dev);
u32 reg_value, val;
u16 rate1, rate2;
.of_to_plat = ca_led_of_to_plat,
.bind = cortina_led_bind,
.probe = cortina_led_probe,
- .plat_auto = sizeof(struct cortina_led_platdata),
+ .plat_auto = sizeof(struct cortina_led_plat),
.priv_auto = sizeof(struct cortina_led_cfg),
.ops = &cortina_led_ops,
};
u32 timestamp; /* Timestamp */
};
-struct altera_sysid_platdata {
+struct altera_sysid_plat {
struct altera_sysid_regs *regs;
};
static int altera_sysid_read(struct udevice *dev,
int offset, void *buf, int size)
{
- struct altera_sysid_platdata *plat = dev->plat;
+ struct altera_sysid_plat *plat = dev->plat;
struct altera_sysid_regs *const regs = plat->regs;
u32 *sysid = buf;
static int altera_sysid_of_to_plat(struct udevice *dev)
{
- struct altera_sysid_platdata *plat = dev_get_plat(dev);
+ struct altera_sysid_plat *plat = dev_get_plat(dev);
plat->regs = map_physmem(dev_read_addr(dev),
sizeof(struct altera_sysid_regs),
.id = UCLASS_MISC,
.of_match = altera_sysid_ids,
.of_to_plat = altera_sysid_of_to_plat,
- .plat_auto = sizeof(struct altera_sysid_platdata),
+ .plat_auto = sizeof(struct altera_sysid_plat),
.ops = &altera_sysid_ops,
};
}
#endif
-static int select_fs_dev(struct device_platdata *plat)
+static int select_fs_dev(struct device_plat *plat)
{
int ret;
ofnode fs_loader_node = dev_ofnode(dev);
if (ofnode_valid(fs_loader_node)) {
- struct device_platdata *plat;
+ struct device_plat *plat;
plat = dev->plat;
if (!ofnode_read_u32_array(fs_loader_node,
{
#if CONFIG_IS_ENABLED(DM) && CONFIG_IS_ENABLED(BLK)
int ret;
- struct device_platdata *plat = dev->plat;
+ struct device_plat *plat = dev->plat;
if (plat->phandlepart.phandle) {
ofnode node = ofnode_get_by_phandle(plat->phandlepart.phandle);
.of_match = fs_loader_ids,
.probe = fs_loader_probe,
.of_to_plat = fs_loader_of_to_plat,
- .plat_auto = sizeof(struct device_platdata),
+ .plat_auto = sizeof(struct device_plat),
.priv_auto = sizeof(struct firmware),
};
u32 cr;
};
-struct microchip_flexcom_platdata {
+struct microchip_flexcom_plat {
struct microchip_flexcom_regs *regs;
u32 flexcom_mode;
};
static int microchip_flexcom_of_to_plat(struct udevice *dev)
{
- struct microchip_flexcom_platdata *plat = dev_get_plat(dev);
+ struct microchip_flexcom_plat *plat = dev_get_plat(dev);
int ret;
plat->regs = map_physmem(dev_read_addr(dev),
.id = UCLASS_MISC,
.of_match = microchip_flexcom_ids,
.of_to_plat = microchip_flexcom_of_to_plat,
- .plat_auto = sizeof(struct microchip_flexcom_platdata),
+ .plat_auto = sizeof(struct microchip_flexcom_plat),
};
void *pcr_reg_address(struct udevice *dev, uint offset)
{
- struct p2sb_child_platdata *pplat = dev_get_parent_plat(dev);
+ struct p2sb_child_plat *pplat = dev_get_parent_plat(dev);
struct udevice *p2sb = dev_get_parent(dev);
struct p2sb_uc_priv *upriv = dev_get_uclass_priv(p2sb);
uintptr_t reg_addr;
int p2sb_get_port_id(struct udevice *dev)
{
- struct p2sb_child_platdata *pplat = dev_get_parent_plat(dev);
+ struct p2sb_child_plat *pplat = dev_get_parent_plat(dev);
return pplat->pid;
}
int p2sb_set_port_id(struct udevice *dev, int portid)
{
struct udevice *ps2b;
- struct p2sb_child_platdata *pplat;
+ struct p2sb_child_plat *pplat;
if (!CONFIG_IS_ENABLED(OF_PLATDATA))
return -ENOSYS;
static int p2sb_child_post_bind(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- struct p2sb_child_platdata *pplat = dev_get_parent_plat(dev);
+ struct p2sb_child_plat *pplat = dev_get_parent_plat(dev);
int ret;
u32 pid;
.per_device_auto = sizeof(struct p2sb_uc_priv),
.post_bind = p2sb_post_bind,
.child_post_bind = p2sb_child_post_bind,
- .per_child_plat_auto = sizeof(struct p2sb_child_platdata),
+ .per_child_plat_auto = sizeof(struct p2sb_child_plat),
};
#include <p2sb.h>
/**
- * struct p2sb_emul_platdata - platform data for this device
+ * struct p2sb_emul_plat - platform data for this device
*
* @command: Current PCI command value
* @bar: Current base address values
*/
-struct p2sb_emul_platdata {
+struct p2sb_emul_plat {
u16 command;
u32 bar[6];
};
uint offset, ulong *valuep,
enum pci_size_t size)
{
- struct p2sb_emul_platdata *plat = dev_get_plat(emul);
+ struct p2sb_emul_plat *plat = dev_get_plat(emul);
switch (offset) {
case PCI_COMMAND:
static int sandbox_p2sb_emul_write_config(struct udevice *emul, uint offset,
ulong value, enum pci_size_t size)
{
- struct p2sb_emul_platdata *plat = dev_get_plat(emul);
+ struct p2sb_emul_plat *plat = dev_get_plat(emul);
switch (offset) {
case PCI_COMMAND:
static int sandbox_p2sb_emul_find_bar(struct udevice *emul, unsigned int addr,
int *barnump, unsigned int *offsetp)
{
- struct p2sb_emul_platdata *plat = dev_get_plat(emul);
+ struct p2sb_emul_plat *plat = dev_get_plat(emul);
int barnum;
for (barnum = 0; barnum < ARRAY_SIZE(barinfo); barnum++) {
return log_msg_ret("No client", ret);
device_foreach_child(dev, p2sb) {
- struct p2sb_child_platdata *pplat =
+ struct p2sb_child_plat *pplat =
dev_get_parent_plat(dev);
log_debug(" - child %s, pid %d, want %d\n", dev->name,
.of_match = sandbox_p2sb_emul_ids,
.ops = &sandbox_p2sb_emul_emul_ops,
.priv_auto = sizeof(struct p2sb_emul_priv),
- .plat_auto = sizeof(struct p2sb_emul_platdata),
+ .plat_auto = sizeof(struct p2sb_emul_plat),
};
static struct pci_device_id sandbox_p2sb_emul_supported[] = {
/* 0x14 efuse strobe finish control register */
};
-struct rockchip_efuse_platdata {
+struct rockchip_efuse_plat {
void __iomem *base;
struct clk *clk;
};
static int rockchip_rk3399_efuse_read(struct udevice *dev, int offset,
void *buf, int size)
{
- struct rockchip_efuse_platdata *plat = dev_get_plat(dev);
+ struct rockchip_efuse_plat *plat = dev_get_plat(dev);
struct rockchip_efuse_regs *efuse =
(struct rockchip_efuse_regs *)plat->base;
static int rockchip_efuse_of_to_plat(struct udevice *dev)
{
- struct rockchip_efuse_platdata *plat = dev_get_plat(dev);
+ struct rockchip_efuse_plat *plat = dev_get_plat(dev);
plat->base = dev_read_addr_ptr(dev);
return 0;
.id = UCLASS_MISC,
.of_match = rockchip_efuse_ids,
.of_to_plat = rockchip_efuse_of_to_plat,
- .plat_auto = sizeof(struct rockchip_efuse_platdata),
+ .plat_auto = sizeof(struct rockchip_efuse_plat),
.ops = &rockchip_efuse_ops,
};
#define OTPC_TIMEOUT 10000
-struct rockchip_otp_platdata {
+struct rockchip_otp_plat {
void __iomem *base;
unsigned long secure_conf_base;
unsigned long otp_mask_base;
};
-static int rockchip_otp_wait_status(struct rockchip_otp_platdata *otp,
+static int rockchip_otp_wait_status(struct rockchip_otp_plat *otp,
u32 flag)
{
int delay = OTPC_TIMEOUT;
return 0;
}
-static int rockchip_otp_ecc_enable(struct rockchip_otp_platdata *otp,
+static int rockchip_otp_ecc_enable(struct rockchip_otp_plat *otp,
bool enable)
{
int ret = 0;
static int rockchip_px30_otp_read(struct udevice *dev, int offset,
void *buf, int size)
{
- struct rockchip_otp_platdata *otp = dev_get_plat(dev);
+ struct rockchip_otp_plat *otp = dev_get_plat(dev);
u8 *buffer = buf;
int ret = 0;
static int rockchip_otp_of_to_plat(struct udevice *dev)
{
- struct rockchip_otp_platdata *otp = dev_get_plat(dev);
+ struct rockchip_otp_plat *otp = dev_get_plat(dev);
otp->base = dev_read_addr_ptr(dev);
.of_match = rockchip_otp_ids,
.ops = &rockchip_otp_ops,
.of_to_plat = rockchip_otp_of_to_plat,
- .plat_auto = sizeof(struct rockchip_otp_platdata),
+ .plat_auto = sizeof(struct rockchip_otp_plat),
};
int sandbox_adder_read(struct udevice *dev, ulong address, void *data,
enum axi_size_t size)
{
- struct p2sb_child_platdata *pplat = dev_get_parent_plat(dev);
+ struct p2sb_child_plat *pplat = dev_get_parent_plat(dev);
u32 *val = data;
*val = pplat->pid << 24 | address;
u32 pwe; /* Write enable input (defines program cycle) */
};
-struct sifive_otp_platdata {
+struct sifive_otp_plat {
struct sifive_otp_regs __iomem *regs;
u32 total_fuses;
};
static int sifive_otp_read(struct udevice *dev, int offset,
void *buf, int size)
{
- struct sifive_otp_platdata *plat = dev_get_plat(dev);
+ struct sifive_otp_plat *plat = dev_get_plat(dev);
struct sifive_otp_regs *regs = (struct sifive_otp_regs *)plat->regs;
/* Check if offset and size are multiple of BYTES_PER_FUSE */
static int sifive_otp_write(struct udevice *dev, int offset,
const void *buf, int size)
{
- struct sifive_otp_platdata *plat = dev_get_plat(dev);
+ struct sifive_otp_plat *plat = dev_get_plat(dev);
struct sifive_otp_regs *regs = (struct sifive_otp_regs *)plat->regs;
/* Check if offset and size are multiple of BYTES_PER_FUSE */
static int sifive_otp_of_to_plat(struct udevice *dev)
{
- struct sifive_otp_platdata *plat = dev_get_plat(dev);
+ struct sifive_otp_plat *plat = dev_get_plat(dev);
int ret;
plat->regs = dev_read_addr_ptr(dev);
.id = UCLASS_MISC,
.of_match = sifive_otp_ids,
.of_to_plat = sifive_otp_of_to_plat,
- .plat_auto = sizeof(struct sifive_otp_platdata),
+ .plat_auto = sizeof(struct sifive_otp_plat),
.ops = &sifive_otp_ops,
};
#include <linux/ctype.h>
/**
- * struct swap_case_platdata - platform data for this device
+ * struct swap_case_plat - platform data for this device
*
* @command: Current PCI command value
* @bar: Current base address values
*/
-struct swap_case_platdata {
+struct swap_case_plat {
u16 command;
u32 bar[6];
};
uint offset, ulong *valuep,
enum pci_size_t size)
{
- struct swap_case_platdata *plat = dev_get_plat(emul);
+ struct swap_case_plat *plat = dev_get_plat(emul);
/*
* The content of the EA capability structure is handled elsewhere to
static int sandbox_swap_case_write_config(struct udevice *emul, uint offset,
ulong value, enum pci_size_t size)
{
- struct swap_case_platdata *plat = dev_get_plat(emul);
+ struct swap_case_plat *plat = dev_get_plat(emul);
switch (offset) {
case PCI_COMMAND:
static int sandbox_swap_case_find_bar(struct udevice *emul, unsigned int addr,
int *barnump, unsigned int *offsetp)
{
- struct swap_case_platdata *plat = dev_get_plat(emul);
+ struct swap_case_plat *plat = dev_get_plat(emul);
int barnum;
for (barnum = 0; barnum < ARRAY_SIZE(barinfo); barnum++) {
.of_match = sandbox_swap_case_ids,
.ops = &sandbox_swap_case_emul_ops,
.priv_auto = sizeof(struct swap_case_priv),
- .plat_auto = sizeof(struct swap_case_platdata),
+ .plat_auto = sizeof(struct swap_case_plat),
};
static struct pci_device_id sandbox_swap_case_supported[] = {
static inline void *get_regbase(const struct mmc *mmc)
{
- struct meson_mmc_platdata *pdata = mmc->priv;
+ struct meson_mmc_plat *pdata = mmc->priv;
return pdata->regbase;
}
static void meson_mmc_setup_addr(struct mmc *mmc, struct mmc_data *data)
{
- struct meson_mmc_platdata *pdata = mmc->priv;
+ struct meson_mmc_plat *pdata = mmc->priv;
unsigned int data_size;
uint32_t data_addr = 0;
struct mmc_data *data)
{
struct mmc *mmc = mmc_get_mmc_dev(dev);
- struct meson_mmc_platdata *pdata = mmc->priv;
+ struct meson_mmc_plat *pdata = mmc->priv;
uint32_t status;
ulong start;
int ret = 0;
static int meson_mmc_of_to_plat(struct udevice *dev)
{
- struct meson_mmc_platdata *pdata = dev_get_plat(dev);
+ struct meson_mmc_plat *pdata = dev_get_plat(dev);
fdt_addr_t addr;
addr = dev_read_addr(dev);
static int meson_mmc_probe(struct udevice *dev)
{
- struct meson_mmc_platdata *pdata = dev_get_plat(dev);
+ struct meson_mmc_plat *pdata = dev_get_plat(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct mmc *mmc = &pdata->mmc;
struct mmc_config *cfg = &pdata->cfg;
int meson_mmc_bind(struct udevice *dev)
{
- struct meson_mmc_platdata *pdata = dev_get_plat(dev);
+ struct meson_mmc_plat *pdata = dev_get_plat(dev);
return mmc_bind(dev, &pdata->mmc, &pdata->cfg);
}
.probe = meson_mmc_probe,
.bind = meson_mmc_bind,
.of_to_plat = meson_mmc_of_to_plat,
- .plat_auto = sizeof(struct meson_mmc_platdata),
+ .plat_auto = sizeof(struct meson_mmc_plat),
};
#ifdef CONFIG_PWRSEQ
#define MESON_SD_EMMC_CMD_RSP2 0x64
#define MESON_SD_EMMC_CMD_RSP3 0x68
-struct meson_mmc_platdata {
+struct meson_mmc_plat {
struct mmc_config cfg;
struct mmc mmc;
void *regbase;
#include <dm/read.h>
#include <dt-structs.h>
-struct mxsmmc_platdata {
+struct mxsmmc_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_fsl_imx23_mmc dtplat;
#endif
static int
mxsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *data)
{
- struct mxsmmc_platdata *plat = dev_get_plat(dev);
+ struct mxsmmc_plat *plat = dev_get_plat(dev);
struct mxsmmc_priv *priv = dev_get_priv(dev);
struct mxs_ssp_regs *ssp_regs = priv->regs;
struct mmc *mmc = &plat->mmc;
static int mxsmmc_get_cd(struct udevice *dev)
{
- struct mxsmmc_platdata *plat = dev_get_plat(dev);
+ struct mxsmmc_plat *plat = dev_get_plat(dev);
struct mxsmmc_priv *priv = dev_get_priv(dev);
struct mxs_ssp_regs *ssp_regs = priv->regs;
static int mxsmmc_set_ios(struct udevice *dev)
{
- struct mxsmmc_platdata *plat = dev_get_plat(dev);
+ struct mxsmmc_plat *plat = dev_get_plat(dev);
struct mxsmmc_priv *priv = dev_get_priv(dev);
struct mxs_ssp_regs *ssp_regs = priv->regs;
struct mmc *mmc = &plat->mmc;
static int mxsmmc_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
- struct mxsmmc_platdata *plat = dev_get_plat(dev);
+ struct mxsmmc_plat *plat = dev_get_plat(dev);
struct mxsmmc_priv *priv = dev_get_priv(dev);
struct blk_desc *bdesc;
struct mmc *mmc;
#if CONFIG_IS_ENABLED(BLK)
static int mxsmmc_bind(struct udevice *dev)
{
- struct mxsmmc_platdata *plat = dev_get_plat(dev);
+ struct mxsmmc_plat *plat = dev_get_plat(dev);
return mmc_bind(dev, &plat->mmc, &plat->cfg);
}
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
static int mxsmmc_of_to_plat(struct udevice *bus)
{
- struct mxsmmc_platdata *plat = bus->plat;
+ struct mxsmmc_plat *plat = bus->plat;
u32 prop[2];
int ret;
#endif
.probe = mxsmmc_probe,
.priv_auto = sizeof(struct mxsmmc_priv),
- .plat_auto = sizeof(struct mxsmmc_platdata),
+ .plat_auto = sizeof(struct mxsmmc_plat),
};
U_BOOT_DRIVER_ALIAS(fsl_imx23_mmc, fsl_imx28_mmc)
u32 chip_select;
};
-struct altera_qspi_platdata {
+struct altera_qspi_plat {
struct altera_qspi_regs *regs;
void *base;
unsigned long size;
{
struct mtd_info *mtd = info->mtd;
struct udevice *dev = mtd->dev;
- struct altera_qspi_platdata *pdata = dev_get_plat(dev);
+ struct altera_qspi_plat *pdata = dev_get_plat(dev);
ulong base = (ulong)pdata->base;
loff_t to = addr - base;
size_t retlen;
static int altera_qspi_erase(struct mtd_info *mtd, struct erase_info *instr)
{
struct udevice *dev = mtd->dev;
- struct altera_qspi_platdata *pdata = dev_get_plat(dev);
+ struct altera_qspi_plat *pdata = dev_get_plat(dev);
struct altera_qspi_regs *regs = pdata->regs;
size_t addr = instr->addr;
size_t len = instr->len;
size_t *retlen, u_char *buf)
{
struct udevice *dev = mtd->dev;
- struct altera_qspi_platdata *pdata = dev_get_plat(dev);
+ struct altera_qspi_plat *pdata = dev_get_plat(dev);
memcpy_fromio(buf, pdata->base + from, len);
*retlen = len;
size_t *retlen, const u_char *buf)
{
struct udevice *dev = mtd->dev;
- struct altera_qspi_platdata *pdata = dev_get_plat(dev);
+ struct altera_qspi_plat *pdata = dev_get_plat(dev);
struct altera_qspi_regs *regs = pdata->regs;
u32 stat;
uint64_t *len)
{
struct udevice *dev = mtd->dev;
- struct altera_qspi_platdata *pdata = dev_get_plat(dev);
+ struct altera_qspi_plat *pdata = dev_get_plat(dev);
struct altera_qspi_regs *regs = pdata->regs;
int shift0 = ffs(QUADSPI_SR_BP2_0) - 1;
int shift3 = ffs(QUADSPI_SR_BP3) - 1 - 3;
static int altera_qspi_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
{
struct udevice *dev = mtd->dev;
- struct altera_qspi_platdata *pdata = dev_get_plat(dev);
+ struct altera_qspi_plat *pdata = dev_get_plat(dev);
struct altera_qspi_regs *regs = pdata->regs;
u32 sector_start, sector_end;
u32 num_sectors;
static int altera_qspi_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
{
struct udevice *dev = mtd->dev;
- struct altera_qspi_platdata *pdata = dev_get_plat(dev);
+ struct altera_qspi_plat *pdata = dev_get_plat(dev);
struct altera_qspi_regs *regs = pdata->regs;
u32 mem_op;
static int altera_qspi_probe(struct udevice *dev)
{
- struct altera_qspi_platdata *pdata = dev_get_plat(dev);
+ struct altera_qspi_plat *pdata = dev_get_plat(dev);
struct altera_qspi_regs *regs = pdata->regs;
unsigned long base = (unsigned long)pdata->base;
struct mtd_info *mtd;
static int altera_qspi_of_to_plat(struct udevice *dev)
{
- struct altera_qspi_platdata *pdata = dev_get_plat(dev);
+ struct altera_qspi_plat *pdata = dev_get_plat(dev);
void *blob = (void *)gd->fdt_blob;
int node = dev_of_offset(dev);
const char *list, *end;
.id = UCLASS_MTD,
.of_match = altera_qspi_ids,
.of_to_plat = altera_qspi_of_to_plat,
- .plat_auto = sizeof(struct altera_qspi_platdata),
+ .plat_auto = sizeof(struct altera_qspi_plat),
.probe = altera_qspi_probe,
};
const struct flash_info *data;
struct sandbox_spi_flash_plat_data *pdata = dev_get_plat(dev);
struct sandbox_state *state = state_get_current();
- struct dm_spi_slave_platdata *slave_plat;
+ struct dm_spi_slave_plat *slave_plat;
struct udevice *bus = dev->parent;
const char *spec = NULL;
struct udevice *emul;
#include <asm/arch/system_manager.h>
-struct dwmac_socfpga_platdata {
+struct dwmac_socfpga_plat {
struct dw_eth_pdata dw_eth_pdata;
void *phy_intf;
u32 reg_shift;
static int dwmac_socfpga_of_to_plat(struct udevice *dev)
{
- struct dwmac_socfpga_platdata *pdata = dev_get_plat(dev);
+ struct dwmac_socfpga_plat *pdata = dev_get_plat(dev);
struct regmap *regmap;
struct ofnode_phandle_args args;
void *range;
static int dwmac_socfpga_probe(struct udevice *dev)
{
- struct dwmac_socfpga_platdata *pdata = dev_get_plat(dev);
+ struct dwmac_socfpga_plat *pdata = dev_get_plat(dev);
struct eth_pdata *edata = &pdata->dw_eth_pdata.eth_pdata;
struct reset_ctl_bulk reset_bulk;
int ret;
.probe = dwmac_socfpga_probe,
.ops = &designware_eth_ops,
.priv_auto = sizeof(struct dw_eth_dev),
- .plat_auto = sizeof(struct dwmac_socfpga_platdata),
+ .plat_auto = sizeof(struct dwmac_socfpga_plat),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
/* sets up primary MAC addresses in DT/IERB */
void fdt_fixup_enetc_mac(void *blob)
{
- struct pci_child_platdata *ppdata;
+ struct pci_child_plat *ppdata;
struct eth_pdata *pdata;
struct udevice *dev;
struct uclass *uc;
static int enetc_ls1028a_write_hwaddr(struct udevice *dev)
{
- struct pci_child_platdata *ppdata = dev_get_parent_plat(dev);
+ struct pci_child_plat *ppdata = dev_get_parent_plat(dev);
const int devfn_to_pf[] = {0, 1, 2, -1, -1, -1, 3};
struct eth_pdata *plat = dev_get_plat(dev);
int devfn = PCI_FUNC(ppdata->devfn);
*
* dw_eth_pdata: Required platform data for designware driver (must be first)
*/
-struct gmac_rockchip_platdata {
+struct gmac_rockchip_plat {
struct dw_eth_pdata dw_eth_pdata;
bool clock_input;
int tx_delay;
struct rk_gmac_ops {
int (*fix_mac_speed)(struct dw_eth_dev *priv);
- void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata);
- void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
+ void (*set_to_rmii)(struct gmac_rockchip_plat *pdata);
+ void (*set_to_rgmii)(struct gmac_rockchip_plat *pdata);
};
static int gmac_rockchip_of_to_plat(struct udevice *dev)
{
- struct gmac_rockchip_platdata *pdata = dev_get_plat(dev);
+ struct gmac_rockchip_plat *pdata = dev_get_plat(dev);
const char *string;
string = dev_read_string(dev, "clock_in_out");
return 0;
}
-static void px30_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
+static void px30_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata)
{
struct px30_grf *grf;
enum {
PX30_GMAC_PHY_INTF_SEL_RMII);
}
-static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_plat *pdata)
{
struct rk322x_grf *grf;
enum {
pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT);
}
-static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_plat *pdata)
{
struct rk3288_grf *grf;
pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
}
-static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
+static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata)
{
struct rk3308_grf *grf;
enum {
RK3308_GMAC_PHY_INTF_SEL_RMII);
}
-static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_plat *pdata)
{
struct rk3328_grf_regs *grf;
enum {
pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT);
}
-static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_plat *pdata)
{
struct rk3368_grf *grf;
enum {
pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT);
}
-static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_plat *pdata)
{
struct rk3399_grf_regs *grf;
pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT);
}
-static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
+static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata)
{
struct rv1108_grf *grf;
static int gmac_rockchip_probe(struct udevice *dev)
{
- struct gmac_rockchip_platdata *pdata = dev_get_plat(dev);
+ struct gmac_rockchip_plat *pdata = dev_get_plat(dev);
struct rk_gmac_ops *ops =
(struct rk_gmac_ops *)dev_get_driver_data(dev);
struct dw_eth_pdata *dw_pdata = dev_get_plat(dev);
.probe = gmac_rockchip_probe,
.ops = &gmac_rockchip_eth_ops,
.priv_auto = sizeof(struct dw_eth_dev),
- .plat_auto = sizeof(struct gmac_rockchip_platdata),
+ .plat_auto = sizeof(struct gmac_rockchip_plat),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#ifdef CONFIG_DM_ETH
static int rtl8169_eth_probe(struct udevice *dev)
{
- struct pci_child_platdata *pplat = dev_get_parent_plat(dev);
+ struct pci_child_plat *pplat = dev_get_parent_plat(dev);
struct rtl8169_private *priv = dev_get_priv(dev);
struct eth_pdata *plat = dev_get_plat(dev);
u32 iobase;
struct blk_desc *desc = dev_get_uclass_plat(udev);
struct nvme_ns *ns = dev_get_priv(udev);
u8 flbas;
- struct pci_child_platdata *pplat;
+ struct pci_child_plat *pplat;
struct nvme_id_ns *id;
id = memalign(ndev->page_size, sizeof(struct nvme_id_ns));
/*
* This uclass is a child of the pci bus. Its plat is not defined here so
- * is defined by its parent, UCLASS_PCI, which uses struct pci_child_platdata.
+ * is defined by its parent, UCLASS_PCI, which uses struct pci_child_plat.
* See per_child_plat_auto in UCLASS_DRIVER(pci).
*/
UCLASS_DRIVER(pci_emul_parent) = {
pci_dev_t dm_pci_get_bdf(const struct udevice *dev)
{
- struct pci_child_platdata *pplat = dev_get_parent_plat(dev);
+ struct pci_child_plat *pplat = dev_get_parent_plat(dev);
struct udevice *bus = dev->parent;
/*
for (device_find_first_child(bus, &dev);
dev;
device_find_next_child(&dev)) {
- struct pci_child_platdata *pplat;
+ struct pci_child_plat *pplat;
pplat = dev_get_parent_plat(dev);
if (pplat && pplat->devfn == find_devfn) {
static int pci_device_matches_ids(struct udevice *dev,
struct pci_device_id *ids)
{
- struct pci_child_platdata *pplat;
+ struct pci_child_plat *pplat;
int i;
pplat = dev_get_parent_plat(dev);
unsigned int device, int *indexp,
struct udevice **devp)
{
- struct pci_child_platdata *pplat;
+ struct pci_child_plat *pplat;
struct udevice *dev;
for (device_find_first_child(bus, &dev);
for (pci_find_first_device(&dev);
dev;
pci_find_next_device(&dev)) {
- struct pci_child_platdata *pplat = dev_get_parent_plat(dev);
+ struct pci_child_plat *pplat = dev_get_parent_plat(dev);
if (pplat->class == find_class && !index--) {
*devp = dev;
int pci_auto_config_devices(struct udevice *bus)
{
struct pci_controller *hose = bus->uclass_priv;
- struct pci_child_platdata *pplat;
+ struct pci_child_plat *pplat;
unsigned int sub_bus;
struct udevice *dev;
int ret;
PCI_MAX_PCI_FUNCTIONS - 1);
for (bdf = PCI_BDF(bus->seq, 0, 0); bdf <= end;
bdf += PCI_BDF(0, 0, 1)) {
- struct pci_child_platdata *pplat;
+ struct pci_child_plat *pplat;
struct udevice *dev;
ulong class;
static int pci_uclass_child_post_bind(struct udevice *dev)
{
- struct pci_child_platdata *pplat;
+ struct pci_child_plat *pplat;
if (!dev_of_valid(dev))
return 0;
}
static phys_addr_t dm_pci_map_ea_virt(struct udevice *dev, int ea_off,
- struct pci_child_platdata *pdata)
+ struct pci_child_plat *pdata)
{
phys_addr_t addr = 0;
}
static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags,
- int ea_off, struct pci_child_platdata *pdata)
+ int ea_off, struct pci_child_plat *pdata)
{
int ea_cnt, i, entry_size;
int bar_id = (bar - PCI_BASE_ADDRESS_0) >> 2;
void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
{
- struct pci_child_platdata *pdata = dev_get_parent_plat(dev);
+ struct pci_child_plat *pdata = dev_get_parent_plat(dev);
struct udevice *udev = dev;
pci_addr_t pci_bus_addr;
u32 bar_response;
bdf += PCI_BDF(0, 0, vf_offset);
for (vf = 0; vf < num_vfs; vf++) {
- struct pci_child_platdata *pplat;
+ struct pci_child_plat *pplat;
ulong class;
pci_bus_read_config(bus, bdf, PCI_CLASS_DEVICE,
.post_probe = pci_uclass_post_probe,
.child_post_bind = pci_uclass_child_post_bind,
.per_device_auto = sizeof(struct pci_controller),
- .per_child_plat_auto = sizeof(struct pci_child_platdata),
+ .per_child_plat_auto = sizeof(struct pci_child_plat),
};
static const struct dm_pci_ops pci_bridge_ops = {
static int pci_rom_probe(struct udevice *dev, struct pci_rom_header **hdrp)
{
- struct pci_child_platdata *pplat = dev_get_parent_plat(dev);
+ struct pci_child_plat *pplat = dev_get_parent_plat(dev);
struct pci_rom_header *rom_header;
struct pci_rom_data *rom_data;
u16 rom_vendor, rom_device;
int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void),
int exec_method)
{
- struct pci_child_platdata *pplat = dev_get_parent_plat(dev);
+ struct pci_child_plat *pplat = dev_get_parent_plat(dev);
struct pci_rom_header *rom = NULL, *ram = NULL;
int vesa_mode = -1;
bool emulate, alloced;
#ifdef CONFIG_DM_VIDEO
int vbe_setup_video_priv(struct vesa_mode_info *vesa,
struct video_priv *uc_priv,
- struct video_uc_platdata *plat)
+ struct video_uc_plat *plat)
{
if (!vesa->x_resolution)
return log_msg_ret("No x resolution", -ENXIO);
int vbe_setup_video(struct udevice *dev, int (*int15_handler)(void))
{
- struct video_uc_platdata *plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
int ret;
/* Attach an emulator if we can */
.child_post_bind = dm_scan_fdt_dev,
- .per_child_plat_auto = sizeof(struct pci_child_platdata),
+ .per_child_plat_auto = sizeof(struct pci_child_plat),
};
struct mtk_pcie *pcie = dev_get_priv(bus);
struct mtk_pcie_port *port;
struct udevice *dev;
- struct pci_child_platdata *pplat = NULL;
+ struct pci_child_plat *pplat = NULL;
int ret = 0;
if (PCI_BUS(bdf) != 0) {
int intel_pinctrl_of_to_plat(struct udevice *dev,
const struct pad_community *comm, int num_cfgs)
{
- struct p2sb_child_platdata *pplat = dev_get_parent_plat(dev);
+ struct p2sb_child_plat *pplat = dev_get_parent_plat(dev);
struct intel_pinctrl_priv *priv = dev_get_priv(dev);
if (!comm) {
#include <asm/intel_pinctrl_defs.h>
/**
- * struct apl_gpio_platdata - platform data for each device
+ * struct apl_gpio_plat - platform data for each device
*
* @dtplat: of-platdata data from C struct
*/
-struct apl_gpio_platdata {
+struct apl_gpio_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
/* Put this first since driver model will copy the data here */
struct dtd_intel_apl_pinctrl dtplat;
static int apl_pinctrl_of_to_plat(struct udevice *dev)
{
- struct p2sb_child_platdata *pplat;
+ struct p2sb_child_plat *pplat;
const struct pad_community *comm = NULL;
int i;
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- struct apl_gpio_platdata *plat = dev_get_plat(dev);
+ struct apl_gpio_plat *plat = dev_get_plat(dev);
int ret;
/*
#endif
.of_to_plat = apl_pinctrl_of_to_plat,
.priv_auto = sizeof(struct intel_pinctrl_priv),
- .plat_auto = sizeof(struct apl_gpio_platdata),
+ .plat_auto = sizeof(struct apl_gpio_plat),
};
* framework groups, Atmel PIO groups will be called banks.
*/
-struct atmel_pio4_platdata {
+struct atmel_pio4_plat {
struct atmel_pio4_port *reg_base;
};
static inline struct atmel_pio4_port *atmel_pio4_bank_base(struct udevice *dev,
u32 bank)
{
- struct atmel_pio4_platdata *plat = dev_get_plat(dev);
+ struct atmel_pio4_plat *plat = dev_get_plat(dev);
struct atmel_pio4_port *bank_base =
(struct atmel_pio4_port *)((u32)plat->reg_base +
ATMEL_PIO_BANK_OFFSET * bank);
static int atmel_pinctrl_probe(struct udevice *dev)
{
- struct atmel_pio4_platdata *plat = dev_get_plat(dev);
+ struct atmel_pio4_plat *plat = dev_get_plat(dev);
fdt_addr_t addr_base;
dev = dev_get_parent(dev);
.id = UCLASS_PINCTRL,
.of_match = atmel_pinctrl_match,
.probe = atmel_pinctrl_probe,
- .plat_auto = sizeof(struct atmel_pio4_platdata),
+ .plat_auto = sizeof(struct atmel_pio4_plat),
.ops = &atmel_pinctrl_ops,
};
#include <linux/ioport.h>
/**
- * struct qe_io_platdata
+ * struct qe_io_plat
*
* @base: Base register address
* @num_par_io_ports number of io ports
*/
-struct qe_io_platdata {
+struct qe_io_plat {
qepio83xx_t *base;
u32 num_io_ports;
};
#else
static int qe_io_of_to_plat(struct udevice *dev)
{
- struct qe_io_platdata *plat = dev->plat;
+ struct qe_io_plat *plat = dev->plat;
fdt_addr_t addr;
addr = dev_read_addr(dev);
*/
static int par_io_of_config_node(struct udevice *dev, ofnode pio)
{
- struct qe_io_platdata *plat = dev->plat;
+ struct qe_io_plat *plat = dev->plat;
qepio83xx_t *par_io = plat->base;
const unsigned int *pio_map;
int pio_map_len;
.of_match = of_match_ptr(par_io_pinctrl_match),
.probe = par_io_pinctrl_probe,
.of_to_plat = qe_io_of_to_plat,
- .plat_auto = sizeof(struct qe_io_platdata),
+ .plat_auto = sizeof(struct qe_io_plat),
.ops = &par_io_pinctrl_ops,
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.flags = DM_FLAG_PRE_RELOC,
/* oe = 1, pu = 1, od = 1 */
#define BIDIR_PU (OE | PU | OD)
-struct sti_pinctrl_platdata {
+struct sti_pinctrl_plat {
struct regmap *regmap;
};
*/
void sti_alternate_select(struct udevice *dev, struct sti_pin_desc *pin_desc)
{
- struct sti_pinctrl_platdata *plat = dev_get_plat(dev);
+ struct sti_pinctrl_plat *plat = dev_get_plat(dev);
unsigned long sysconf, *sysconfreg;
int alt = pin_desc->alt;
int bank = pin_desc->bank;
/* pin configuration */
void sti_pin_configure(struct udevice *dev, struct sti_pin_desc *pin_desc)
{
- struct sti_pinctrl_platdata *plat = dev_get_plat(dev);
+ struct sti_pinctrl_plat *plat = dev_get_plat(dev);
int bit;
int oe = 0, pu = 0, od = 0;
unsigned long *sysconfreg;
static int sti_pinctrl_probe(struct udevice *dev)
{
- struct sti_pinctrl_platdata *plat = dev_get_plat(dev);
+ struct sti_pinctrl_plat *plat = dev_get_plat(dev);
struct udevice *syscon;
int err;
.of_match = sti_pinctrl_ids,
.ops = &sti_pinctrl_ops,
.probe = sti_pinctrl_probe,
- .plat_auto = sizeof(struct sti_pinctrl_platdata),
+ .plat_auto = sizeof(struct sti_pinctrl_plat),
.ops = &sti_pinctrl_ops,
};
DECLARE_GLOBAL_DATA_PTR;
-struct r7s72100_pfc_platdata {
+struct r7s72100_pfc_plat {
void __iomem *base;
};
static void r7s72100_pfc_set_function(struct udevice *dev, u16 bank, u16 line,
u16 func, u16 inbuf, u16 bidir)
{
- struct r7s72100_pfc_platdata *plat = dev_get_plat(dev);
+ struct r7s72100_pfc_plat *plat = dev_get_plat(dev);
clrsetbits_le16(plat->base + PFCAE(bank), BIT(line),
(func & BIT(2)) ? BIT(line) : 0);
static int r7s72100_pfc_probe(struct udevice *dev)
{
- struct r7s72100_pfc_platdata *plat = dev_get_plat(dev);
+ struct r7s72100_pfc_plat *plat = dev_get_plat(dev);
fdt_addr_t addr_base;
ofnode node;
.id = UCLASS_PINCTRL,
.of_match = r7s72100_pfc_match,
.probe = r7s72100_pfc_probe,
- .plat_auto = sizeof(struct r7s72100_pfc_platdata),
+ .plat_auto = sizeof(struct r7s72100_pfc_plat),
.ops = &r7s72100_pfc_ops,
};
upriv->gen_pmcon1, upriv->gen_pmcon2, upriv->gen_pmcon3);
}
-int pmc_ofdata_to_uc_platdata(struct udevice *dev)
+int pmc_ofdata_to_uc_plat(struct udevice *dev)
{
struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
int ret;
#include <power/acpi_pmc.h>
/**
- * struct pmc_emul_platdata - platform data for this device
+ * struct pmc_emul_plat - platform data for this device
*
* @command: Current PCI command value
* @bar: Current base address values
*/
-struct pmc_emul_platdata {
+struct pmc_emul_plat {
u16 command;
u32 bar[6];
};
static int sandbox_pmc_emul_read_config(const struct udevice *emul, uint offset,
ulong *valuep, enum pci_size_t size)
{
- struct pmc_emul_platdata *plat = dev_get_plat(emul);
+ struct pmc_emul_plat *plat = dev_get_plat(emul);
switch (offset) {
case PCI_COMMAND:
static int sandbox_pmc_emul_write_config(struct udevice *emul, uint offset,
ulong value, enum pci_size_t size)
{
- struct pmc_emul_platdata *plat = dev_get_plat(emul);
+ struct pmc_emul_plat *plat = dev_get_plat(emul);
switch (offset) {
case PCI_COMMAND:
static int sandbox_pmc_emul_find_bar(struct udevice *emul, unsigned int addr,
int *barnump, unsigned int *offsetp)
{
- struct pmc_emul_platdata *plat = dev_get_plat(emul);
+ struct pmc_emul_plat *plat = dev_get_plat(emul);
int barnum;
for (barnum = 0; barnum < ARRAY_SIZE(barinfo); barnum++) {
.ops = &sandbox_pmc_emul_emul_ops,
.probe = sandbox_pmc_probe,
.priv_auto = sizeof(struct pmc_emul_priv),
- .plat_auto = sizeof(struct pmc_emul_platdata),
+ .plat_auto = sizeof(struct pmc_emul_plat),
};
static struct pci_device_id sandbox_pmc_emul_supported[] = {
upriv->pmc_bar0 = map_sysmem(base, 0x2000);
upriv->gpe_cfg = (u32 *)(upriv->pmc_bar0 + GPIO_GPE_CFG);
- return pmc_ofdata_to_uc_platdata(dev);
+ return pmc_ofdata_to_uc_plat(dev);
}
static struct acpi_pmc_ops sandbox_pmc_ops = {
static int imx8_power_domain_on(struct power_domain *power_domain)
{
struct udevice *dev = power_domain->dev;
- struct imx8_power_domain_platdata *pdata;
+ struct imx8_power_domain_plat *pdata;
struct imx8_power_domain_priv *ppriv;
sc_err_t ret;
int err;
return err;
}
- pdata = (struct imx8_power_domain_platdata *)dev_get_plat(dev);
+ pdata = (struct imx8_power_domain_plat *)dev_get_plat(dev);
ppriv = (struct imx8_power_domain_priv *)dev_get_priv(dev);
debug("%s(power_domain=%s) resource_id %d\n", __func__, dev->name,
struct udevice *child;
struct imx8_power_domain_priv *ppriv;
struct imx8_power_domain_priv *child_ppriv;
- struct imx8_power_domain_platdata *pdata;
+ struct imx8_power_domain_plat *pdata;
sc_err_t ret;
ppriv = dev_get_priv(dev);
struct udevice *child;
struct imx8_power_domain_priv *ppriv;
struct imx8_power_domain_priv *child_ppriv;
- struct imx8_power_domain_platdata *pdata;
+ struct imx8_power_domain_plat *pdata;
sc_err_t ret;
struct power_domain parent_pd;
if (device_get_uclass_id(parent) == UCLASS_POWER_DOMAIN) {
pdata =
- (struct imx8_power_domain_platdata *)dev_get_plat(parent);
+ (struct imx8_power_domain_plat *)dev_get_plat(parent);
ppriv = (struct imx8_power_domain_priv *)dev_get_priv(parent);
debug("%s, %s, state_on %d\n", __func__, parent->name,
static int imx8_power_domain_of_to_plat(struct udevice *dev)
{
int reg;
- struct imx8_power_domain_platdata *pdata = dev_get_plat(dev);
+ struct imx8_power_domain_plat *pdata = dev_get_plat(dev);
reg = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", -1);
if (reg == -1) {
.bind = imx8_power_domain_bind,
.probe = imx8_power_domain_probe,
.of_to_plat = imx8_power_domain_of_to_plat,
- .plat_auto = sizeof(struct imx8_power_domain_platdata),
+ .plat_auto = sizeof(struct imx8_power_domain_plat),
.priv_auto = sizeof(struct imx8_power_domain_priv),
.ops = &imx8_power_domain_ops,
.flags = DM_FLAG_DEFAULT_PD_CTRL_OFF,
static int imx8m_power_domain_on(struct power_domain *power_domain)
{
struct udevice *dev = power_domain->dev;
- struct imx8m_power_domain_platdata *pdata;
+ struct imx8m_power_domain_plat *pdata;
pdata = dev_get_plat(dev);
static int imx8m_power_domain_off(struct power_domain *power_domain)
{
struct udevice *dev = power_domain->dev;
- struct imx8m_power_domain_platdata *pdata;
+ struct imx8m_power_domain_plat *pdata;
pdata = dev_get_plat(dev);
if (pdata->resource_id < 0)
static int imx8m_power_domain_of_to_plat(struct udevice *dev)
{
- struct imx8m_power_domain_platdata *pdata = dev_get_plat(dev);
+ struct imx8m_power_domain_plat *pdata = dev_get_plat(dev);
pdata->resource_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"reg", -1);
.bind = imx8m_power_domain_bind,
.probe = imx8m_power_domain_probe,
.of_to_plat = imx8m_power_domain_of_to_plat,
- .plat_auto = sizeof(struct imx8m_power_domain_platdata),
+ .plat_auto = sizeof(struct imx8m_power_domain_plat),
.ops = &imx8m_power_domain_ops,
};
};
/**
- * struct bd71837_platdata - describe regulator control registers
+ * struct bd71837_plat - describe regulator control registers
*
* @name: name of the regulator. Used for matching the dt-entry
* @enable_reg: register address used to enable/disable regulator
* @sel_mask: bit to toggle in order to transfer the register control to SW
* @dvs: whether the voltage can be changed when regulator is enabled
*/
-struct bd71837_platdata {
+struct bd71837_plat {
const char *name;
u8 enable_reg;
u8 enablemask;
* is powering NXP i.MX8. In this use-case we (for now) only allow control
* for BUCK3 and BUCK4 which are not boot critical.
*/
-static struct bd71837_platdata bd71837_reg_data[] = {
+static struct bd71837_plat bd71837_reg_data[] = {
/* Bucks 1-4 which support dynamic voltage scaling */
BD_DATA("BUCK1", BD718XX_BUCK1_CTRL, HW_STATE_CONTROL,
BD718XX_BUCK1_VOLT_RUN, DVS_BUCK_RUN_MASK, dvs_buck_vranges, 0,
BD71837_LDO7_MASK, ldo7_vranges, 0, false, BD718XX_LDO_SEL),
};
-static struct bd71837_platdata bd71847_reg_data[] = {
+static struct bd71837_plat bd71847_reg_data[] = {
/* Bucks 1 and 2 which support dynamic voltage scaling */
BD_DATA("BUCK1", BD718XX_BUCK1_CTRL, HW_STATE_CONTROL,
BD718XX_BUCK1_VOLT_RUN, DVS_BUCK_RUN_MASK, dvs_buck_vranges, 0,
static int bd71837_get_enable(struct udevice *dev)
{
int val;
- struct bd71837_platdata *plat = dev_get_plat(dev);
+ struct bd71837_plat *plat = dev_get_plat(dev);
/*
* boot critical regulators on bd71837 must not be controlled by sw
static int bd71837_set_enable(struct udevice *dev, bool enable)
{
int val = 0;
- struct bd71837_platdata *plat = dev_get_plat(dev);
+ struct bd71837_plat *plat = dev_get_plat(dev);
/*
* boot critical regulators on bd71837 must not be controlled by sw
unsigned int range;
int i;
int found = 0;
- struct bd71837_platdata *plat = dev_get_plat(dev);
+ struct bd71837_plat *plat = dev_get_plat(dev);
/*
* An under/overshooting may occur if voltage is changed for other
{
unsigned int reg, range;
unsigned int tmp;
- struct bd71837_platdata *plat = dev_get_plat(dev);
+ struct bd71837_plat *plat = dev_get_plat(dev);
int i;
reg = pmic_reg_read(dev->parent, plat->volt_reg);
static int bd71837_regulator_probe(struct udevice *dev)
{
- struct bd71837_platdata *plat = dev_get_plat(dev);
+ struct bd71837_plat *plat = dev_get_plat(dev);
int i, ret;
struct dm_regulator_uclass_plat *uc_pdata;
int type;
- struct bd71837_platdata *init_data;
+ struct bd71837_plat *init_data;
int data_amnt;
type = dev_get_driver_data(dev_get_parent(dev));
.id = UCLASS_REGULATOR,
.ops = &bd71837_regulator_ops,
.probe = bd71837_regulator_probe,
- .plat_auto = sizeof(struct bd71837_platdata),
+ .plat_auto = sizeof(struct bd71837_plat),
};
FAN53555_MONITOR,
};
-struct fan53555_platdata {
+struct fan53555_plat {
/* Voltage setting register */
unsigned int vol_reg;
unsigned int sleep_reg;
static int fan53555_regulator_of_to_plat(struct udevice *dev)
{
- struct fan53555_platdata *dev_pdata = dev_get_plat(dev);
+ struct fan53555_plat *dev_pdata = dev_get_plat(dev);
struct dm_regulator_uclass_plat *uc_pdata =
dev_get_uclass_plat(dev);
u32 sleep_vsel;
static int fan53555_regulator_get_value(struct udevice *dev)
{
- struct fan53555_platdata *pdata = dev_get_plat(dev);
+ struct fan53555_plat *pdata = dev_get_plat(dev);
struct fan53555_priv *priv = dev_get_priv(dev);
int reg;
int voltage;
static int fan53555_regulator_set_value(struct udevice *dev, int uV)
{
- struct fan53555_platdata *pdata = dev_get_plat(dev);
+ struct fan53555_plat *pdata = dev_get_plat(dev);
struct fan53555_priv *priv = dev_get_priv(dev);
u8 vol;
.id = UCLASS_REGULATOR,
.ops = &fan53555_regulator_ops,
.of_to_plat = fan53555_regulator_of_to_plat,
- .plat_auto = sizeof(struct fan53555_platdata),
+ .plat_auto = sizeof(struct fan53555_plat),
.priv_auto = sizeof(struct fan53555_priv),
.probe = fan53555_probe,
};
static int fixed_regulator_of_to_plat(struct udevice *dev)
{
struct dm_regulator_uclass_plat *uc_pdata;
- struct regulator_common_platdata *dev_pdata;
+ struct regulator_common_plat *dev_pdata;
dev_pdata = dev_get_plat(dev);
uc_pdata = dev_get_uclass_plat(dev);
.ops = &fixed_regulator_ops,
.of_match = fixed_regulator_ids,
.of_to_plat = fixed_regulator_of_to_plat,
- .plat_auto = sizeof(struct regulator_common_platdata),
+ .plat_auto = sizeof(struct regulator_common_plat),
};
#define GPIO_REGULATOR_MAX_STATES 2
-struct gpio_regulator_platdata {
- struct regulator_common_platdata common;
+struct gpio_regulator_plat {
+ struct regulator_common_plat common;
struct gpio_desc gpio; /* GPIO for regulator voltage control */
int states[GPIO_REGULATOR_MAX_STATES];
int voltages[GPIO_REGULATOR_MAX_STATES];
static int gpio_regulator_of_to_plat(struct udevice *dev)
{
struct dm_regulator_uclass_plat *uc_pdata;
- struct gpio_regulator_platdata *dev_pdata;
+ struct gpio_regulator_plat *dev_pdata;
struct gpio_desc *gpio;
int ret, count, i, j;
u32 states_array[GPIO_REGULATOR_MAX_STATES * 2];
static int gpio_regulator_get_value(struct udevice *dev)
{
struct dm_regulator_uclass_plat *uc_pdata;
- struct gpio_regulator_platdata *dev_pdata = dev_get_plat(dev);
+ struct gpio_regulator_plat *dev_pdata = dev_get_plat(dev);
int enable;
if (!dev_pdata->gpio.dev)
static int gpio_regulator_set_value(struct udevice *dev, int uV)
{
- struct gpio_regulator_platdata *dev_pdata = dev_get_plat(dev);
+ struct gpio_regulator_plat *dev_pdata = dev_get_plat(dev);
int ret;
bool enable;
static int gpio_regulator_get_enable(struct udevice *dev)
{
- struct gpio_regulator_platdata *dev_pdata = dev_get_plat(dev);
+ struct gpio_regulator_plat *dev_pdata = dev_get_plat(dev);
return regulator_common_get_enable(dev, &dev_pdata->common);
}
static int gpio_regulator_set_enable(struct udevice *dev, bool enable)
{
- struct gpio_regulator_platdata *dev_pdata = dev_get_plat(dev);
+ struct gpio_regulator_plat *dev_pdata = dev_get_plat(dev);
return regulator_common_set_enable(dev, &dev_pdata->common, enable);
}
.ops = &gpio_regulator_ops,
.of_match = gpio_regulator_ids,
.of_to_plat = gpio_regulator_of_to_plat,
- .plat_auto = sizeof(struct gpio_regulator_platdata),
+ .plat_auto = sizeof(struct gpio_regulator_plat),
};
};
/**
- * struct pfuze100_regulator_platdata - platform data for pfuze100
+ * struct pfuze100_regulator_plat - platform data for pfuze100
*
* @desc: Points the description entry of one regulator of pfuze100
*/
-struct pfuze100_regulator_platdata {
+struct pfuze100_regulator_plat {
struct pfuze100_regulator_desc *desc;
};
static int pfuze100_regulator_probe(struct udevice *dev)
{
struct dm_regulator_uclass_plat *uc_pdata;
- struct pfuze100_regulator_platdata *plat = dev_get_plat(dev);
+ struct pfuze100_regulator_plat *plat = dev_get_plat(dev);
struct pfuze100_regulator_desc *desc;
switch (dev_get_driver_data(dev_get_parent(dev))) {
static int pfuze100_regulator_mode(struct udevice *dev, int op, int *opmode)
{
int val;
- struct pfuze100_regulator_platdata *plat = dev_get_plat(dev);
+ struct pfuze100_regulator_plat *plat = dev_get_plat(dev);
struct pfuze100_regulator_desc *desc = plat->desc;
if (op == PMIC_OP_GET) {
{
int i;
int val;
- struct pfuze100_regulator_platdata *plat = dev_get_plat(dev);
+ struct pfuze100_regulator_plat *plat = dev_get_plat(dev);
struct pfuze100_regulator_desc *desc = plat->desc;
struct dm_regulator_uclass_plat *uc_pdata =
dev_get_uclass_plat(dev);
.id = UCLASS_REGULATOR,
.ops = &pfuze100_regulator_ops,
.probe = pfuze100_regulator_probe,
- .plat_auto = sizeof(struct pfuze100_regulator_platdata),
+ .plat_auto = sizeof(struct pfuze100_regulator_plat),
};
#include "regulator_common.h"
int regulator_common_of_to_plat(struct udevice *dev,
- struct regulator_common_platdata *dev_pdata,
+ struct regulator_common_plat *dev_pdata,
const char *enable_gpio_name)
{
struct gpio_desc *gpio;
}
int regulator_common_get_enable(const struct udevice *dev,
- struct regulator_common_platdata *dev_pdata)
+ struct regulator_common_plat *dev_pdata)
{
/* Enable GPIO is optional */
if (!dev_pdata->gpio.dev)
}
int regulator_common_set_enable(const struct udevice *dev,
- struct regulator_common_platdata *dev_pdata, bool enable)
+ struct regulator_common_plat *dev_pdata, bool enable)
{
int ret;
#include <asm/gpio.h>
-struct regulator_common_platdata {
+struct regulator_common_plat {
struct gpio_desc gpio; /* GPIO for regulator enable control */
unsigned int startup_delay_us;
unsigned int off_on_delay_us;
};
int regulator_common_of_to_plat(struct udevice *dev,
- struct regulator_common_platdata *dev_pdata,
- const char *enable_gpio_name);
+ struct regulator_common_plat *dev_pdata, const
+ char *enable_gpio_name);
int regulator_common_get_enable(const struct udevice *dev,
- struct regulator_common_platdata *dev_pdata);
+ struct regulator_common_plat *dev_pdata);
int regulator_common_set_enable(const struct udevice *dev,
- struct regulator_common_platdata *dev_pdata, bool enable);
+ struct regulator_common_plat *dev_pdata, bool enable);
#endif /* _REGULATOR_COMMON_H */
}
#if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int conv_of_platdata(struct udevice *dev)
+static int conv_of_plat(struct udevice *dev)
{
struct rk3368_sdram_params *plat = dev_get_plat(dev);
struct dtd_rockchip_rk3368_dmc *of_plat = &plat->of_plat;
struct dram_info *priv = dev_get_priv(dev);
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- ret = conv_of_platdata(dev);
+ ret = conv_of_plat(dev);
if (ret)
return ret;
#endif
#endif /* CONFIG_SPL_BUILD */
#if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int conv_of_platdata(struct udevice *dev)
+static int conv_of_plat(struct udevice *dev)
{
struct rk3188_sdram_params *plat = dev_get_plat(dev);
struct dtd_rockchip_rk3188_dmc *of_plat = &plat->of_plat;
memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base));
/* rk3188 supports dual-channel, set default channel num to 2 */
plat->num_channels = 1;
- ret = regmap_init_mem_platdata(dev, of_plat->reg,
- ARRAY_SIZE(of_plat->reg) / 2,
- &plat->map);
+ ret = regmap_init_mem_plat(dev, of_plat->reg,
+ ARRAY_SIZE(of_plat->reg) / 2, &plat->map);
if (ret)
return ret;
#ifdef CONFIG_SPL_BUILD
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- ret = conv_of_platdata(dev);
+ ret = conv_of_plat(dev);
if (ret)
return ret;
#endif
#endif /* CONFIG_TPL_BUILD */
#if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int conv_of_platdata(struct udevice *dev)
+static int conv_of_plat(struct udevice *dev)
{
struct rk322x_sdram_params *plat = dev_get_plat(dev);
struct dtd_rockchip_rk322x_dmc *of_plat = &plat->of_plat;
memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base));
plat->num_channels = 1;
- ret = regmap_init_mem_platdata(dev, of_plat->reg,
- ARRAY_SIZE(of_plat->reg) / 2,
- &plat->map);
+ ret = regmap_init_mem_plat(dev, of_plat->reg,
+ ARRAY_SIZE(of_plat->reg) / 2, &plat->map);
if (ret)
return ret;
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
#ifdef CONFIG_TPL_BUILD
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- ret = conv_of_platdata(dev);
+ ret = conv_of_plat(dev);
if (ret)
return ret;
#endif
#endif /* CONFIG_SPL_BUILD */
#if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int conv_of_platdata(struct udevice *dev)
+static int conv_of_plat(struct udevice *dev)
{
struct rk3288_sdram_params *plat = dev_get_plat(dev);
struct dtd_rockchip_rk3288_dmc *of_plat = &plat->of_plat;
memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base));
/* Rk3288 supports dual-channel, set default channel num to 2 */
plat->num_channels = 2;
- ret = regmap_init_mem_platdata(dev, of_plat->reg,
- ARRAY_SIZE(of_plat->reg) / 2,
- &plat->map);
+ ret = regmap_init_mem_plat(dev, of_plat->reg,
+ ARRAY_SIZE(of_plat->reg) / 2, &plat->map);
if (ret)
return ret;
#if defined(CONFIG_TPL_BUILD) || \
(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- ret = conv_of_platdata(dev);
+ ret = conv_of_plat(dev);
if (ret)
return ret;
#endif
};
#if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int conv_of_platdata(struct udevice *dev)
+static int conv_of_plat(struct udevice *dev)
{
struct rockchip_dmc_plat *plat = dev_get_plat(dev);
struct dtd_rockchip_rk3328_dmc *dtplat = &plat->dtplat;
int ret;
- ret = regmap_init_mem_platdata(dev, dtplat->reg,
- ARRAY_SIZE(dtplat->reg) / 2,
- &plat->map);
+ ret = regmap_init_mem_plat(dev, dtplat->reg,
+ ARRAY_SIZE(dtplat->reg) / 2, &plat->map);
if (ret)
return ret;
struct rk3328_sdram_params *params =
(void *)dtplat->rockchip_sdram_params;
- ret = conv_of_platdata(dev);
+ ret = conv_of_plat(dev);
if (ret)
return ret;
#endif
}
#if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int conv_of_platdata(struct udevice *dev)
+static int conv_of_plat(struct udevice *dev)
{
struct rockchip_dmc_plat *plat = dev_get_plat(dev);
struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat;
int ret;
- ret = regmap_init_mem_platdata(dev, dtplat->reg,
- ARRAY_SIZE(dtplat->reg) / 2,
- &plat->map);
+ ret = regmap_init_mem_plat(dev, dtplat->reg,
+ ARRAY_SIZE(dtplat->reg) / 2, &plat->map);
if (ret)
return ret;
struct rk3399_sdram_params *params =
(void *)dtplat->rockchip_sdram_params;
- ret = conv_of_platdata(dev);
+ ret = conv_of_plat(dev);
if (ret)
return ret;
#endif
#include <rng.h>
#include <asm/io.h>
-struct meson_rng_platdata {
+struct meson_rng_plat {
fdt_addr_t base;
struct clk clk;
};
*/
static int meson_rng_read(struct udevice *dev, void *data, size_t len)
{
- struct meson_rng_platdata *pdata = dev_get_plat(dev);
+ struct meson_rng_plat *pdata = dev_get_plat(dev);
char *buffer = (char *)data;
while (len) {
*/
static int meson_rng_probe(struct udevice *dev)
{
- struct meson_rng_platdata *pdata = dev_get_plat(dev);
+ struct meson_rng_plat *pdata = dev_get_plat(dev);
int err;
err = clk_enable(&pdata->clk);
*/
static int meson_rng_remove(struct udevice *dev)
{
- struct meson_rng_platdata *pdata = dev_get_plat(dev);
+ struct meson_rng_plat *pdata = dev_get_plat(dev);
return clk_disable(&pdata->clk);
}
*/
static int meson_rng_of_to_plat(struct udevice *dev)
{
- struct meson_rng_platdata *pdata = dev_get_plat(dev);
+ struct meson_rng_plat *pdata = dev_get_plat(dev);
int err;
pdata->base = dev_read_addr(dev);
.ops = &meson_rng_ops,
.probe = meson_rng_probe,
.remove = meson_rng_remove,
- .plat_auto = sizeof(struct meson_rng_platdata),
+ .plat_auto = sizeof(struct meson_rng_plat),
.of_to_plat = meson_rng_of_to_plat,
};
int (*rk_rng_read)(struct udevice *dev, void *data, size_t len);
};
-struct rk_rng_platdata {
+struct rk_rng_plat {
fdt_addr_t base;
struct rk_rng_soc_data *soc_data;
};
static int rk_v1_rng_read(struct udevice *dev, void *data, size_t len)
{
- struct rk_rng_platdata *pdata = dev_get_priv(dev);
+ struct rk_rng_plat *pdata = dev_get_priv(dev);
u32 reg = 0;
int retval;
static int rk_v2_rng_read(struct udevice *dev, void *data, size_t len)
{
- struct rk_rng_platdata *pdata = dev_get_priv(dev);
+ struct rk_rng_plat *pdata = dev_get_priv(dev);
u32 reg = 0;
int retval;
unsigned int i;
int ret = -EIO;
- struct rk_rng_platdata *pdata = dev_get_priv(dev);
+ struct rk_rng_plat *pdata = dev_get_priv(dev);
if (!len)
return 0;
static int rockchip_rng_of_to_plat(struct udevice *dev)
{
- struct rk_rng_platdata *pdata = dev_get_priv(dev);
+ struct rk_rng_plat *pdata = dev_get_priv(dev);
memset(pdata, 0x00, sizeof(*pdata));
static int rockchip_rng_probe(struct udevice *dev)
{
- struct rk_rng_platdata *pdata = dev_get_priv(dev);
+ struct rk_rng_plat *pdata = dev_get_priv(dev);
pdata->soc_data = (struct rk_rng_soc_data *)dev_get_driver_data(dev);
.ops = &rockchip_rng_ops,
.probe = rockchip_rng_probe,
.of_to_plat = rockchip_rng_of_to_plat,
- .priv_auto = sizeof(struct rk_rng_platdata),
+ .priv_auto = sizeof(struct rk_rng_plat),
};
#define RNG_DR 0x08
-struct stm32_rng_platdata {
+struct stm32_rng_plat {
fdt_addr_t base;
struct clk clk;
struct reset_ctl rst;
int retval, i;
u32 sr, count, reg;
size_t increment;
- struct stm32_rng_platdata *pdata = dev_get_plat(dev);
+ struct stm32_rng_plat *pdata = dev_get_plat(dev);
while (len > 0) {
retval = readl_poll_timeout(pdata->base + RNG_SR, sr,
return 0;
}
-static int stm32_rng_init(struct stm32_rng_platdata *pdata)
+static int stm32_rng_init(struct stm32_rng_plat *pdata)
{
int err;
return 0;
}
-static int stm32_rng_cleanup(struct stm32_rng_platdata *pdata)
+static int stm32_rng_cleanup(struct stm32_rng_plat *pdata)
{
writel(0, pdata->base + RNG_CR);
static int stm32_rng_probe(struct udevice *dev)
{
- struct stm32_rng_platdata *pdata = dev_get_plat(dev);
+ struct stm32_rng_plat *pdata = dev_get_plat(dev);
reset_assert(&pdata->rst);
udelay(20);
static int stm32_rng_remove(struct udevice *dev)
{
- struct stm32_rng_platdata *pdata = dev_get_plat(dev);
+ struct stm32_rng_plat *pdata = dev_get_plat(dev);
return stm32_rng_cleanup(pdata);
}
static int stm32_rng_of_to_plat(struct udevice *dev)
{
- struct stm32_rng_platdata *pdata = dev_get_plat(dev);
+ struct stm32_rng_plat *pdata = dev_get_plat(dev);
int err;
pdata->base = dev_read_addr(dev);
.ops = &stm32_rng_ops,
.probe = stm32_rng_probe,
.remove = stm32_rng_remove,
- .plat_auto = sizeof(struct stm32_rng_platdata),
+ .plat_auto = sizeof(struct stm32_rng_plat),
.of_to_plat = stm32_rng_of_to_plat,
};
#define RTC_CR_START (1 << 0)
-struct pl031_platdata {
+struct pl031_plat {
phys_addr_t base;
};
static inline u32 pl031_read_reg(struct udevice *dev, int reg)
{
- struct pl031_platdata *pdata = dev_get_plat(dev);
+ struct pl031_plat *pdata = dev_get_plat(dev);
return readl(pdata->base + reg);
}
static inline u32 pl031_write_reg(struct udevice *dev, int reg, u32 value)
{
- struct pl031_platdata *pdata = dev_get_plat(dev);
+ struct pl031_plat *pdata = dev_get_plat(dev);
return writel(value, pdata->base + reg);
}
static int pl031_of_to_plat(struct udevice *dev)
{
- struct pl031_platdata *pdata = dev_get_plat(dev);
+ struct pl031_plat *pdata = dev_get_plat(dev);
pdata->base = dev_read_addr(dev);
.of_match = pl031_ids,
.probe = pl031_probe,
.of_to_plat = pl031_of_to_plat,
- .plat_auto = sizeof(struct pl031_platdata),
+ .plat_auto = sizeof(struct pl031_plat),
.ops = &pl031_ops,
};
UCLASS_DRIVER(scsi) = {
.id = UCLASS_SCSI,
.name = "scsi",
- .per_device_plat_auto = sizeof(struct scsi_platdata),
+ .per_device_plat_auto = sizeof(struct scsi_plat),
};
{
struct blk_desc *block_dev = dev_get_uclass_plat(dev);
struct udevice *bdev = dev->parent;
- struct scsi_platdata *uc_plat = dev_get_uclass_plat(bdev);
+ struct scsi_plat *uc_plat = dev_get_uclass_plat(bdev);
lbaint_t start, blks, max_blks;
uintptr_t buf_addr;
unsigned short smallblks = 0;
{
struct blk_desc *block_dev = dev_get_uclass_plat(dev);
struct udevice *bdev = dev->parent;
- struct scsi_platdata *uc_plat = dev_get_uclass_plat(bdev);
+ struct scsi_plat *uc_plat = dev_get_uclass_plat(bdev);
lbaint_t start, blks, max_blks;
uintptr_t buf_addr;
unsigned short smallblks;
int scsi_scan_dev(struct udevice *dev, bool verbose)
{
- struct scsi_platdata *uc_plat; /* scsi controller plat */
+ struct scsi_plat *uc_plat; /* scsi controller plat */
int ret;
int i;
int lun;
u32 control; /* Control register */
};
-struct altera_jtaguart_platdata {
+struct altera_jtaguart_plat {
struct altera_jtaguart_regs *regs;
};
static int altera_jtaguart_putc(struct udevice *dev, const char ch)
{
- struct altera_jtaguart_platdata *plat = dev->plat;
+ struct altera_jtaguart_plat *plat = dev->plat;
struct altera_jtaguart_regs *const regs = plat->regs;
u32 st = readl(®s->control);
static int altera_jtaguart_pending(struct udevice *dev, bool input)
{
- struct altera_jtaguart_platdata *plat = dev->plat;
+ struct altera_jtaguart_plat *plat = dev->plat;
struct altera_jtaguart_regs *const regs = plat->regs;
u32 st = readl(®s->control);
static int altera_jtaguart_getc(struct udevice *dev)
{
- struct altera_jtaguart_platdata *plat = dev->plat;
+ struct altera_jtaguart_plat *plat = dev->plat;
struct altera_jtaguart_regs *const regs = plat->regs;
u32 val;
static int altera_jtaguart_probe(struct udevice *dev)
{
#ifdef CONFIG_ALTERA_JTAG_UART_BYPASS
- struct altera_jtaguart_platdata *plat = dev->plat;
+ struct altera_jtaguart_plat *plat = dev->plat;
struct altera_jtaguart_regs *const regs = plat->regs;
writel(ALTERA_JTAG_AC, ®s->control); /* clear AC flag */
static int altera_jtaguart_of_to_plat(struct udevice *dev)
{
- struct altera_jtaguart_platdata *plat = dev_get_plat(dev);
+ struct altera_jtaguart_plat *plat = dev_get_plat(dev);
plat->regs = map_physmem(dev_read_addr(dev),
sizeof(struct altera_jtaguart_regs),
.id = UCLASS_SERIAL,
.of_match = altera_jtaguart_ids,
.of_to_plat = altera_jtaguart_of_to_plat,
- .plat_auto = sizeof(struct altera_jtaguart_platdata),
+ .plat_auto = sizeof(struct altera_jtaguart_plat),
.probe = altera_jtaguart_probe,
.ops = &altera_jtaguart_ops,
};
u32 endofpacket; /* End-of-packet reg */
};
-struct altera_uart_platdata {
+struct altera_uart_plat {
struct altera_uart_regs *regs;
unsigned int uartclk;
};
static int altera_uart_setbrg(struct udevice *dev, int baudrate)
{
- struct altera_uart_platdata *plat = dev->plat;
+ struct altera_uart_plat *plat = dev->plat;
struct altera_uart_regs *const regs = plat->regs;
u32 div;
static int altera_uart_putc(struct udevice *dev, const char ch)
{
- struct altera_uart_platdata *plat = dev->plat;
+ struct altera_uart_plat *plat = dev->plat;
struct altera_uart_regs *const regs = plat->regs;
if (!(readl(®s->status) & ALTERA_UART_TRDY))
static int altera_uart_pending(struct udevice *dev, bool input)
{
- struct altera_uart_platdata *plat = dev->plat;
+ struct altera_uart_plat *plat = dev->plat;
struct altera_uart_regs *const regs = plat->regs;
u32 st = readl(®s->status);
static int altera_uart_getc(struct udevice *dev)
{
- struct altera_uart_platdata *plat = dev->plat;
+ struct altera_uart_plat *plat = dev->plat;
struct altera_uart_regs *const regs = plat->regs;
if (!(readl(®s->status) & ALTERA_UART_RRDY))
static int altera_uart_of_to_plat(struct udevice *dev)
{
- struct altera_uart_platdata *plat = dev_get_plat(dev);
+ struct altera_uart_plat *plat = dev_get_plat(dev);
plat->regs = map_physmem(dev_read_addr(dev),
sizeof(struct altera_uart_regs),
.id = UCLASS_SERIAL,
.of_match = altera_uart_ids,
.of_to_plat = altera_uart_of_to_plat,
- .plat_auto = sizeof(struct altera_uart_platdata),
+ .plat_auto = sizeof(struct altera_uart_plat),
.probe = altera_uart_probe,
.ops = &altera_uart_ops,
};
static int atmel_serial_probe(struct udevice *dev)
{
- struct atmel_serial_platdata *plat = dev->plat;
+ struct atmel_serial_plat *plat = dev->plat;
struct atmel_serial_priv *priv = dev_get_priv(dev);
int ret;
#if CONFIG_IS_ENABLED(OF_CONTROL)
.id = UCLASS_SERIAL,
#if CONFIG_IS_ENABLED(OF_CONTROL)
.of_match = atmel_serial_ids,
- .plat_auto = sizeof(struct atmel_serial_platdata),
+ .plat_auto = sizeof(struct atmel_serial_plat),
#endif
.probe = atmel_serial_probe,
.ops = &atmel_serial_ops,
static int lpc32xx_hsuart_probe(struct udevice *dev)
{
- struct lpc32xx_hsuart_platdata *plat = dev_get_plat(dev);
+ struct lpc32xx_hsuart_plat *plat = dev_get_plat(dev);
struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
priv->hsuart = (struct hsuart_regs *)plat->base;
* on a platform
*/
#ifdef CONFIG_NS16550_DYNAMIC
-static void serial_out_dynamic(struct ns16550_platdata *plat, u8 *addr,
+static void serial_out_dynamic(struct ns16550_plat *plat, u8 *addr,
int value)
{
if (plat->flags & NS16550_FLAG_IO) {
}
}
-static int serial_in_dynamic(struct ns16550_platdata *plat, u8 *addr)
+static int serial_in_dynamic(struct ns16550_plat *plat, u8 *addr)
{
if (plat->flags & NS16550_FLAG_IO) {
return inb(addr);
}
}
#else
-static inline void serial_out_dynamic(struct ns16550_platdata *plat, u8 *addr,
+static inline void serial_out_dynamic(struct ns16550_plat *plat, u8 *addr,
int value)
{
}
-static inline int serial_in_dynamic(struct ns16550_platdata *plat, u8 *addr)
+static inline int serial_in_dynamic(struct ns16550_plat *plat, u8 *addr)
{
return 0;
}
static void ns16550_writeb(NS16550_t port, int offset, int value)
{
- struct ns16550_platdata *plat = port->plat;
+ struct ns16550_plat *plat = port->plat;
unsigned char *addr;
offset *= 1 << plat->reg_shift;
static int ns16550_readb(NS16550_t port, int offset)
{
- struct ns16550_platdata *plat = port->plat;
+ struct ns16550_plat *plat = port->plat;
unsigned char *addr;
offset *= 1 << plat->reg_shift;
static u32 ns16550_getfcr(NS16550_t port)
{
- struct ns16550_platdata *plat = port->plat;
+ struct ns16550_plat *plat = port->plat;
return plat->fcr;
}
static int ns16550_serial_setbrg(struct udevice *dev, int baudrate)
{
struct NS16550 *const com_port = dev_get_priv(dev);
- struct ns16550_platdata *plat = com_port->plat;
+ struct ns16550_plat *plat = com_port->plat;
int clock_divisor;
clock_divisor = ns16550_calc_divisor(com_port, plat->clock, baudrate);
struct serial_device_info *info)
{
struct NS16550 *const com_port = dev_get_priv(dev);
- struct ns16550_platdata *plat = com_port->plat;
+ struct ns16550_plat *plat = com_port->plat;
info->type = SERIAL_CHIP_16550_COMPATIBLE;
#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
return 0;
}
-static int ns16550_serial_assign_base(struct ns16550_platdata *plat, ulong base)
+static int ns16550_serial_assign_base(struct ns16550_plat *plat, ulong base)
{
if (base == FDT_ADDR_T_NONE)
return -EINVAL;
int ns16550_serial_probe(struct udevice *dev)
{
- struct ns16550_platdata *plat = dev->plat;
+ struct ns16550_plat *plat = dev->plat;
struct NS16550 *const com_port = dev_get_priv(dev);
struct reset_ctl_bulk reset_bulk;
fdt_addr_t addr;
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
int ns16550_serial_of_to_plat(struct udevice *dev)
{
- struct ns16550_platdata *plat = dev->plat;
+ struct ns16550_plat *plat = dev->plat;
const u32 port_type = dev_get_driver_data(dev);
fdt_addr_t addr;
struct clk clk;
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.of_match = ns16550_serial_ids,
.of_to_plat = ns16550_serial_of_to_plat,
- .plat_auto = sizeof(struct ns16550_platdata),
+ .plat_auto = sizeof(struct ns16550_plat),
#endif
.priv_auto = sizeof(struct NS16550),
.probe = ns16550_serial_probe,
DECLARE_GLOBAL_DATA_PTR;
-struct sandbox_serial_platdata {
+struct sandbox_serial_plat {
int colour; /* Text colour to use for output, -1 for none */
};
static int sandbox_serial_remove(struct udevice *dev)
{
- struct sandbox_serial_platdata *plat = dev->plat;
+ struct sandbox_serial_plat *plat = dev->plat;
if (plat->colour != -1)
output_ansi_reset();
static int sandbox_serial_putc(struct udevice *dev, const char ch)
{
struct sandbox_serial_priv *priv = dev_get_priv(dev);
- struct sandbox_serial_platdata *plat = dev->plat;
+ struct sandbox_serial_plat *plat = dev->plat;
/* With of-platdata we don't real the colour correctly, so disable it */
if (!CONFIG_IS_ENABLED(OF_PLATDATA) && priv->start_of_line &&
static int sandbox_serial_of_to_plat(struct udevice *dev)
{
- struct sandbox_serial_platdata *plat = dev->plat;
+ struct sandbox_serial_plat *plat = dev->plat;
const char *colour;
int i;
.id = UCLASS_SERIAL,
.of_match = sandbox_serial_ids,
.of_to_plat = sandbox_serial_of_to_plat,
- .plat_auto = sizeof(struct sandbox_serial_platdata),
+ .plat_auto = sizeof(struct sandbox_serial_plat),
.priv_auto = sizeof(struct sandbox_serial_priv),
.probe = sandbox_serial_probe,
.remove = sandbox_serial_remove,
};
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
-static const struct sandbox_serial_platdata platdata_non_fdt = {
+static const struct sandbox_serial_plat platdata_non_fdt = {
.colour = -1,
};
};
-struct arc_serial_platdata {
+struct arc_serial_plat {
struct arc_serial_regs *reg;
unsigned int uartclk;
};
static int arc_serial_setbrg(struct udevice *dev, int baudrate)
{
- struct arc_serial_platdata *plat = dev->plat;
+ struct arc_serial_plat *plat = dev->plat;
struct arc_serial_regs *const regs = plat->reg;
int arc_console_baud = gd->cpu_clk / (baudrate * 4) - 1;
static int arc_serial_putc(struct udevice *dev, const char c)
{
- struct arc_serial_platdata *plat = dev->plat;
+ struct arc_serial_plat *plat = dev->plat;
struct arc_serial_regs *const regs = plat->reg;
while (!(readb(®s->status) & UART_TXEMPTY))
static int arc_serial_pending(struct udevice *dev, bool input)
{
- struct arc_serial_platdata *plat = dev->plat;
+ struct arc_serial_plat *plat = dev->plat;
struct arc_serial_regs *const regs = plat->reg;
uint32_t status = readb(®s->status);
static int arc_serial_getc(struct udevice *dev)
{
- struct arc_serial_platdata *plat = dev->plat;
+ struct arc_serial_plat *plat = dev->plat;
struct arc_serial_regs *const regs = plat->reg;
while (!arc_serial_tstc(regs))
static int arc_serial_of_to_plat(struct udevice *dev)
{
- struct arc_serial_platdata *plat = dev_get_plat(dev);
+ struct arc_serial_plat *plat = dev_get_plat(dev);
DECLARE_GLOBAL_DATA_PTR;
plat->reg = dev_read_addr_ptr(dev);
.id = UCLASS_SERIAL,
.of_match = arc_serial_ids,
.of_to_plat = arc_serial_of_to_plat,
- .plat_auto = sizeof(struct arc_serial_platdata),
+ .plat_auto = sizeof(struct arc_serial_plat),
.probe = arc_serial_probe,
.ops = &arc_serial_ops,
};
static int bcm283x_mu_serial_setbrg(struct udevice *dev, int baudrate)
{
- struct bcm283x_mu_serial_platdata *plat = dev_get_plat(dev);
+ struct bcm283x_mu_serial_plat *plat = dev_get_plat(dev);
struct bcm283x_mu_priv *priv = dev_get_priv(dev);
struct bcm283x_mu_regs *regs = priv->regs;
u32 divider;
static int bcm283x_mu_serial_probe(struct udevice *dev)
{
- struct bcm283x_mu_serial_platdata *plat = dev_get_plat(dev);
+ struct bcm283x_mu_serial_plat *plat = dev_get_plat(dev);
struct bcm283x_mu_priv *priv = dev_get_priv(dev);
fdt_addr_t addr;
.name = "serial_bcm283x_mu",
.id = UCLASS_SERIAL,
.of_match = of_match_ptr(bcm283x_mu_serial_id),
- .plat_auto = sizeof(struct bcm283x_mu_serial_platdata),
+ .plat_auto = sizeof(struct bcm283x_mu_serial_plat),
.probe = bcm283x_mu_serial_probe,
.ops = &bcm283x_mu_serial_ops,
#if !CONFIG_IS_ENABLED(OF_CONTROL) || CONFIG_IS_ENABLED(OF_BOARD)
static int bcm283x_pl011_serial_probe(struct udevice *dev)
{
- struct pl01x_serial_platdata *plat = dev_get_plat(dev);
+ struct pl01x_serial_plat *plat = dev_get_plat(dev);
int ret;
/* Don't spawn the device if it's not muxed */
.id = UCLASS_SERIAL,
.of_match = of_match_ptr(bcm283x_pl011_serial_id),
.probe = bcm283x_pl011_serial_probe,
- .plat_auto = sizeof(struct pl01x_serial_platdata),
+ .plat_auto = sizeof(struct pl01x_serial_plat),
.ops = &bcm283x_pl011_serial_ops,
#if !CONFIG_IS_ENABLED(OF_CONTROL) || CONFIG_IS_ENABLED(OF_BOARD)
.flags = DM_FLAG_PRE_RELOC,
static int coreboot_of_to_plat(struct udevice *dev)
{
- struct ns16550_platdata *plat = dev_get_plat(dev);
+ struct ns16550_plat *plat = dev_get_plat(dev);
struct cb_serial *cb_info = lib_sysinfo.serial;
plat->base = cb_info->baseaddr;
.id = UCLASS_SERIAL,
.of_match = coreboot_serial_ids,
.priv_auto = sizeof(struct NS16550),
- .plat_auto = sizeof(struct ns16550_platdata),
+ .plat_auto = sizeof(struct ns16550_plat),
.of_to_plat = coreboot_of_to_plat,
.probe = ns16550_serial_probe,
.ops = &ns16550_serial_ops,
#define UART_MUL 0x34
#define UART_DIV 0x38
-static void mid_writel(struct ns16550_platdata *plat, int offset, int value)
+static void mid_writel(struct ns16550_plat *plat, int offset, int value)
{
unsigned char *addr;
static int mid_serial_probe(struct udevice *dev)
{
- struct ns16550_platdata *plat = dev_get_plat(dev);
+ struct ns16550_plat *plat = dev_get_plat(dev);
/*
* Initialize fractional divider correctly for Intel Edison
.id = UCLASS_SERIAL,
.of_match = mid_serial_ids,
.of_to_plat = ns16550_serial_of_to_plat,
- .plat_auto = sizeof(struct ns16550_platdata),
+ .plat_auto = sizeof(struct ns16550_plat),
.priv_auto = sizeof(struct NS16550),
.probe = mid_serial_probe,
.ops = &ns16550_serial_ops,
return 0;
}
-struct linflex_serial_platdata {
+struct linflex_serial_plat {
struct linflex_fsl *base_addr;
u8 port_id; /* do we need this? */
};
static int linflex_serial_probe(struct udevice *dev)
{
- struct linflex_serial_platdata *plat = dev->plat;
+ struct linflex_serial_plat *plat = dev->plat;
struct linflex_serial_priv *priv = dev_get_priv(dev);
priv->lfuart = (struct linflex_fsl *)plat->base_addr;
DEV_IMXRT,
};
-struct lpuart_serial_platdata {
+struct lpuart_serial_plat {
void *reg;
enum lpuart_devtype devtype;
ulong flags;
static bool is_lpuart32(struct udevice *dev)
{
- struct lpuart_serial_platdata *plat = dev->plat;
+ struct lpuart_serial_plat *plat = dev->plat;
return plat->flags & LPUART_FLAG_REGMAP_32BIT_REG;
}
static void _lpuart_serial_setbrg(struct udevice *dev,
int baudrate)
{
- struct lpuart_serial_platdata *plat = dev_get_plat(dev);
+ struct lpuart_serial_plat *plat = dev_get_plat(dev);
struct lpuart_fsl *base = plat->reg;
u32 clk;
u16 sbr;
__raw_writeb(sbr & 0xff, &base->ubdl);
}
-static int _lpuart_serial_getc(struct lpuart_serial_platdata *plat)
+static int _lpuart_serial_getc(struct lpuart_serial_plat *plat)
{
struct lpuart_fsl *base = plat->reg;
while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR)))
return __raw_readb(&base->ud);
}
-static void _lpuart_serial_putc(struct lpuart_serial_platdata *plat,
+static void _lpuart_serial_putc(struct lpuart_serial_plat *plat,
const char c)
{
struct lpuart_fsl *base = plat->reg;
}
/* Test whether a character is in the RX buffer */
-static int _lpuart_serial_tstc(struct lpuart_serial_platdata *plat)
+static int _lpuart_serial_tstc(struct lpuart_serial_plat *plat)
{
struct lpuart_fsl *base = plat->reg;
*/
static int _lpuart_serial_init(struct udevice *dev)
{
- struct lpuart_serial_platdata *plat = dev_get_plat(dev);
+ struct lpuart_serial_plat *plat = dev_get_plat(dev);
struct lpuart_fsl *base = (struct lpuart_fsl *)plat->reg;
u8 ctrl;
static void _lpuart32_serial_setbrg_7ulp(struct udevice *dev,
int baudrate)
{
- struct lpuart_serial_platdata *plat = dev_get_plat(dev);
+ struct lpuart_serial_plat *plat = dev_get_plat(dev);
struct lpuart_fsl_reg32 *base = plat->reg;
u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
u32 clk;
static void _lpuart32_serial_setbrg(struct udevice *dev,
int baudrate)
{
- struct lpuart_serial_platdata *plat = dev_get_plat(dev);
+ struct lpuart_serial_plat *plat = dev_get_plat(dev);
struct lpuart_fsl_reg32 *base = plat->reg;
u32 clk;
u32 sbr;
lpuart_write32(plat->flags, &base->baud, sbr);
}
-static int _lpuart32_serial_getc(struct lpuart_serial_platdata *plat)
+static int _lpuart32_serial_getc(struct lpuart_serial_plat *plat)
{
struct lpuart_fsl_reg32 *base = plat->reg;
u32 stat, val;
return val & 0x3ff;
}
-static void _lpuart32_serial_putc(struct lpuart_serial_platdata *plat,
+static void _lpuart32_serial_putc(struct lpuart_serial_plat *plat,
const char c)
{
struct lpuart_fsl_reg32 *base = plat->reg;
}
/* Test whether a character is in the RX buffer */
-static int _lpuart32_serial_tstc(struct lpuart_serial_platdata *plat)
+static int _lpuart32_serial_tstc(struct lpuart_serial_plat *plat)
{
struct lpuart_fsl_reg32 *base = plat->reg;
u32 water;
*/
static int _lpuart32_serial_init(struct udevice *dev)
{
- struct lpuart_serial_platdata *plat = dev_get_plat(dev);
+ struct lpuart_serial_plat *plat = dev_get_plat(dev);
struct lpuart_fsl_reg32 *base = (struct lpuart_fsl_reg32 *)plat->reg;
u32 val, tx_fifo_size;
static int lpuart_serial_setbrg(struct udevice *dev, int baudrate)
{
- struct lpuart_serial_platdata *plat = dev_get_plat(dev);
+ struct lpuart_serial_plat *plat = dev_get_plat(dev);
if (is_lpuart32(dev)) {
if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8 ||
static int lpuart_serial_getc(struct udevice *dev)
{
- struct lpuart_serial_platdata *plat = dev->plat;
+ struct lpuart_serial_plat *plat = dev->plat;
if (is_lpuart32(dev))
return _lpuart32_serial_getc(plat);
static int lpuart_serial_putc(struct udevice *dev, const char c)
{
- struct lpuart_serial_platdata *plat = dev->plat;
+ struct lpuart_serial_plat *plat = dev->plat;
if (is_lpuart32(dev))
_lpuart32_serial_putc(plat, c);
static int lpuart_serial_pending(struct udevice *dev, bool input)
{
- struct lpuart_serial_platdata *plat = dev->plat;
+ struct lpuart_serial_plat *plat = dev->plat;
struct lpuart_fsl *reg = plat->reg;
struct lpuart_fsl_reg32 *reg32 = plat->reg;
u32 stat;
static int lpuart_serial_of_to_plat(struct udevice *dev)
{
- struct lpuart_serial_platdata *plat = dev->plat;
+ struct lpuart_serial_plat *plat = dev->plat;
const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
fdt_addr_t addr;
.id = UCLASS_SERIAL,
.of_match = lpuart_serial_ids,
.of_to_plat = lpuart_serial_of_to_plat,
- .plat_auto = sizeof(struct lpuart_serial_platdata),
+ .plat_auto = sizeof(struct lpuart_serial_plat),
.probe = lpuart_serial_probe,
.ops = &lpuart_serial_ops,
};
static int coldfire_serial_probe(struct udevice *dev)
{
- struct coldfire_serial_platdata *plat = dev->plat;
+ struct coldfire_serial_plat *plat = dev->plat;
plat->port = dev->seq;
static int coldfire_serial_putc(struct udevice *dev, const char ch)
{
- struct coldfire_serial_platdata *plat = dev->plat;
+ struct coldfire_serial_plat *plat = dev->plat;
uart_t *uart = (uart_t *)plat->base;
/* Wait for last character to go. */
static int coldfire_serial_getc(struct udevice *dev)
{
- struct coldfire_serial_platdata *plat = dev->plat;
+ struct coldfire_serial_plat *plat = dev->plat;
uart_t *uart = (uart_t *)(plat->base);
/* Wait for a character to arrive. */
int coldfire_serial_setbrg(struct udevice *dev, int baudrate)
{
- struct coldfire_serial_platdata *plat = dev->plat;
+ struct coldfire_serial_plat *plat = dev->plat;
uart_t *uart = (uart_t *)(plat->base);
mcf_serial_setbrg_common(uart, baudrate);
static int coldfire_serial_pending(struct udevice *dev, bool input)
{
- struct coldfire_serial_platdata *plat = dev->plat;
+ struct coldfire_serial_plat *plat = dev->plat;
uart_t *uart = (uart_t *)(plat->base);
if (input)
static int coldfire_of_to_plat(struct udevice *dev)
{
- struct coldfire_serial_platdata *plat = dev_get_plat(dev);
+ struct coldfire_serial_plat *plat = dev_get_plat(dev);
fdt_addr_t addr_base;
addr_base = dev_read_addr(dev);
.id = UCLASS_SERIAL,
.of_match = coldfire_serial_ids,
.of_to_plat = coldfire_of_to_plat,
- .plat_auto = sizeof(struct coldfire_serial_platdata),
+ .plat_auto = sizeof(struct coldfire_serial_plat),
.probe = coldfire_serial_probe,
.ops = &coldfire_serial_ops,
.flags = DM_FLAG_PRE_RELOC,
u32 misc;
};
-struct meson_serial_platdata {
+struct meson_serial_plat {
struct meson_uart *reg;
};
static int meson_serial_probe(struct udevice *dev)
{
- struct meson_serial_platdata *plat = dev->plat;
+ struct meson_serial_plat *plat = dev->plat;
struct meson_uart *const uart = plat->reg;
meson_serial_init(uart);
static void meson_serial_rx_error(struct udevice *dev)
{
- struct meson_serial_platdata *plat = dev->plat;
+ struct meson_serial_plat *plat = dev->plat;
struct meson_uart *const uart = plat->reg;
u32 val = readl(&uart->control);
static int meson_serial_getc(struct udevice *dev)
{
- struct meson_serial_platdata *plat = dev->plat;
+ struct meson_serial_plat *plat = dev->plat;
struct meson_uart *const uart = plat->reg;
uint32_t status = readl(&uart->status);
static int meson_serial_putc(struct udevice *dev, const char ch)
{
- struct meson_serial_platdata *plat = dev->plat;
+ struct meson_serial_plat *plat = dev->plat;
struct meson_uart *const uart = plat->reg;
if (readl(&uart->status) & AML_UART_TX_FULL)
static int meson_serial_pending(struct udevice *dev, bool input)
{
- struct meson_serial_platdata *plat = dev->plat;
+ struct meson_serial_plat *plat = dev->plat;
struct meson_uart *const uart = plat->reg;
uint32_t status = readl(&uart->status);
static int meson_serial_of_to_plat(struct udevice *dev)
{
- struct meson_serial_platdata *plat = dev->plat;
+ struct meson_serial_plat *plat = dev->plat;
fdt_addr_t addr;
addr = dev_read_addr(dev);
.probe = meson_serial_probe,
.ops = &meson_serial_ops,
.of_to_plat = meson_serial_of_to_plat,
- .plat_auto = sizeof(struct meson_serial_platdata),
+ .plat_auto = sizeof(struct meson_serial_plat),
};
#ifdef CONFIG_DEBUG_UART_MESON
#include <serial.h>
#include <asm/io.h>
-struct mvebu_platdata {
+struct mvebu_plat {
void __iomem *base;
};
static int mvebu_serial_putc(struct udevice *dev, const char ch)
{
- struct mvebu_platdata *plat = dev_get_plat(dev);
+ struct mvebu_plat *plat = dev_get_plat(dev);
void __iomem *base = plat->base;
while (readl(base + UART_STATUS_REG) & UART_STATUS_TXFIFO_FULL)
static int mvebu_serial_getc(struct udevice *dev)
{
- struct mvebu_platdata *plat = dev_get_plat(dev);
+ struct mvebu_plat *plat = dev_get_plat(dev);
void __iomem *base = plat->base;
while (!(readl(base + UART_STATUS_REG) & UART_STATUS_RX_RDY))
static int mvebu_serial_pending(struct udevice *dev, bool input)
{
- struct mvebu_platdata *plat = dev_get_plat(dev);
+ struct mvebu_plat *plat = dev_get_plat(dev);
void __iomem *base = plat->base;
if (readl(base + UART_STATUS_REG) & UART_STATUS_RX_RDY)
static int mvebu_serial_setbrg(struct udevice *dev, int baudrate)
{
- struct mvebu_platdata *plat = dev_get_plat(dev);
+ struct mvebu_plat *plat = dev_get_plat(dev);
void __iomem *base = plat->base;
/*
static int mvebu_serial_probe(struct udevice *dev)
{
- struct mvebu_platdata *plat = dev_get_plat(dev);
+ struct mvebu_plat *plat = dev_get_plat(dev);
void __iomem *base = plat->base;
/* reset FIFOs */
static int mvebu_serial_of_to_plat(struct udevice *dev)
{
- struct mvebu_platdata *plat = dev_get_plat(dev);
+ struct mvebu_plat *plat = dev_get_plat(dev);
plat->base = dev_read_addr_ptr(dev);
.id = UCLASS_SERIAL,
.of_match = mvebu_serial_ids,
.of_to_plat = mvebu_serial_of_to_plat,
- .plat_auto = sizeof(struct mvebu_platdata),
+ .plat_auto = sizeof(struct mvebu_plat),
.probe = mvebu_serial_probe,
.ops = &mvebu_serial_ops,
};
int mxc_serial_setbrg(struct udevice *dev, int baudrate)
{
- struct mxc_serial_platdata *plat = dev->plat;
+ struct mxc_serial_plat *plat = dev->plat;
u32 clk = imx_get_uartclk();
_mxc_serial_setbrg(plat->reg, clk, baudrate, plat->use_dte);
static int mxc_serial_probe(struct udevice *dev)
{
- struct mxc_serial_platdata *plat = dev->plat;
+ struct mxc_serial_plat *plat = dev->plat;
_mxc_serial_init(plat->reg, plat->use_dte);
static int mxc_serial_getc(struct udevice *dev)
{
- struct mxc_serial_platdata *plat = dev->plat;
+ struct mxc_serial_plat *plat = dev->plat;
struct mxc_uart *const uart = plat->reg;
if (readl(&uart->ts) & UTS_RXEMPTY)
static int mxc_serial_putc(struct udevice *dev, const char ch)
{
- struct mxc_serial_platdata *plat = dev->plat;
+ struct mxc_serial_plat *plat = dev->plat;
struct mxc_uart *const uart = plat->reg;
if (!(readl(&uart->ts) & UTS_TXEMPTY))
static int mxc_serial_pending(struct udevice *dev, bool input)
{
- struct mxc_serial_platdata *plat = dev->plat;
+ struct mxc_serial_plat *plat = dev->plat;
struct mxc_uart *const uart = plat->reg;
uint32_t sr2 = readl(&uart->sr2);
#if CONFIG_IS_ENABLED(OF_CONTROL)
static int mxc_serial_of_to_plat(struct udevice *dev)
{
- struct mxc_serial_platdata *plat = dev->plat;
+ struct mxc_serial_plat *plat = dev->plat;
fdt_addr_t addr;
addr = dev_read_addr(dev);
#if CONFIG_IS_ENABLED(OF_CONTROL)
.of_match = mxc_serial_ids,
.of_to_plat = mxc_serial_of_to_plat,
- .plat_auto = sizeof(struct mxc_serial_platdata),
+ .plat_auto = sizeof(struct mxc_serial_plat),
#endif
.probe = mxc_serial_probe,
.ops = &mxc_serial_ops,
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
static int omap_serial_of_to_plat(struct udevice *dev)
{
- struct ns16550_platdata *plat = dev->plat;
+ struct ns16550_plat *plat = dev->plat;
fdt_addr_t addr;
struct clk clk;
int err;
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.of_match = omap_serial_ids,
.of_to_plat = omap_serial_of_to_plat,
- .plat_auto = sizeof(struct ns16550_platdata),
+ .plat_auto = sizeof(struct ns16550_plat),
#endif
.priv_auto = sizeof(struct NS16550),
.probe = ns16550_serial_probe,
int pl01x_serial_setbrg(struct udevice *dev, int baudrate)
{
- struct pl01x_serial_platdata *plat = dev_get_plat(dev);
+ struct pl01x_serial_plat *plat = dev_get_plat(dev);
struct pl01x_priv *priv = dev_get_priv(dev);
if (!plat->skip_init) {
int pl01x_serial_probe(struct udevice *dev)
{
- struct pl01x_serial_platdata *plat = dev_get_plat(dev);
+ struct pl01x_serial_plat *plat = dev_get_plat(dev);
struct pl01x_priv *priv = dev_get_priv(dev);
priv->regs = (struct pl01x_regs *)plat->base;
int pl01x_serial_of_to_plat(struct udevice *dev)
{
- struct pl01x_serial_platdata *plat = dev_get_plat(dev);
+ struct pl01x_serial_plat *plat = dev_get_plat(dev);
struct clk clk;
fdt_addr_t addr;
int ret;
.id = UCLASS_SERIAL,
.of_match = of_match_ptr(pl01x_serial_id),
.of_to_plat = of_match_ptr(pl01x_serial_of_to_plat),
- .plat_auto = sizeof(struct pl01x_serial_platdata),
+ .plat_auto = sizeof(struct pl01x_serial_plat),
.probe = pl01x_serial_probe,
.ops = &pl01x_serial_ops,
.flags = DM_FLAG_PRE_RELOC,
#ifdef CONFIG_DM_SERIAL
static int pxa_serial_probe(struct udevice *dev)
{
- struct pxa_serial_platdata *plat = dev->plat;
+ struct pxa_serial_plat *plat = dev->plat;
pxa_setbrg_common((struct pxa_uart_regs *)plat->base, plat->port,
plat->baudrate);
static int pxa_serial_putc(struct udevice *dev, const char ch)
{
- struct pxa_serial_platdata *plat = dev->plat;
+ struct pxa_serial_plat *plat = dev->plat;
struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base;
/* Wait for last character to go. */
static int pxa_serial_getc(struct udevice *dev)
{
- struct pxa_serial_platdata *plat = dev->plat;
+ struct pxa_serial_plat *plat = dev->plat;
struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base;
/* Wait for a character to arrive. */
int pxa_serial_setbrg(struct udevice *dev, int baudrate)
{
- struct pxa_serial_platdata *plat = dev->plat;
+ struct pxa_serial_plat *plat = dev->plat;
struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base;
int port = plat->port;
static int pxa_serial_pending(struct udevice *dev, bool input)
{
- struct pxa_serial_platdata *plat = dev->plat;
+ struct pxa_serial_plat *plat = dev->plat;
struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base;
if (input)
#include <asm/arch-rockchip/clock.h>
#if defined(CONFIG_ROCKCHIP_RK3188)
-struct rockchip_uart_platdata {
+struct rockchip_uart_plat {
struct dtd_rockchip_rk3188_uart dtplat;
- struct ns16550_platdata plat;
+ struct ns16550_plat plat;
};
struct dtd_rockchip_rk3188_uart *dtplat, s_dtplat;
#elif defined(CONFIG_ROCKCHIP_RK3288)
-struct rockchip_uart_platdata {
+struct rockchip_uart_plat {
struct dtd_rockchip_rk3288_uart dtplat;
- struct ns16550_platdata plat;
+ struct ns16550_plat plat;
};
struct dtd_rockchip_rk3288_uart *dtplat, s_dtplat;
#endif
static int rockchip_serial_probe(struct udevice *dev)
{
- struct rockchip_uart_platdata *plat = dev_get_plat(dev);
+ struct rockchip_uart_plat *plat = dev_get_plat(dev);
/* Create some new platform data for the standard driver */
plat->plat.base = plat->dtplat.reg[0];
.name = "rockchip_rk3188_uart",
.id = UCLASS_SERIAL,
.priv_auto = sizeof(struct NS16550),
- .plat_auto = sizeof(struct rockchip_uart_platdata),
+ .plat_auto = sizeof(struct rockchip_uart_plat),
.probe = rockchip_serial_probe,
.ops = &ns16550_serial_ops,
.flags = DM_FLAG_PRE_RELOC,
.name = "rockchip_rk3288_uart",
.id = UCLASS_SERIAL,
.priv_auto = sizeof(struct NS16550),
- .plat_auto = sizeof(struct rockchip_uart_platdata),
+ .plat_auto = sizeof(struct rockchip_uart_plat),
.probe = rockchip_serial_probe,
.ops = &ns16550_serial_ops,
.flags = DM_FLAG_PRE_RELOC,
#define TX_FIFO_FULL (1 << 24)
/* Information about a serial port */
-struct s5p_serial_platdata {
+struct s5p_serial_plat {
struct s5p_uart *reg; /* address of registers in physical memory */
u8 port_id; /* uart port number */
};
#ifndef CONFIG_SPL_BUILD
int s5p_serial_setbrg(struct udevice *dev, int baudrate)
{
- struct s5p_serial_platdata *plat = dev->plat;
+ struct s5p_serial_plat *plat = dev->plat;
struct s5p_uart *const uart = plat->reg;
u32 uclk;
static int s5p_serial_probe(struct udevice *dev)
{
- struct s5p_serial_platdata *plat = dev->plat;
+ struct s5p_serial_plat *plat = dev->plat;
struct s5p_uart *const uart = plat->reg;
s5p_serial_init(uart);
static int s5p_serial_getc(struct udevice *dev)
{
- struct s5p_serial_platdata *plat = dev->plat;
+ struct s5p_serial_plat *plat = dev->plat;
struct s5p_uart *const uart = plat->reg;
if (!(readl(&uart->ufstat) & RX_FIFO_COUNT_MASK))
static int s5p_serial_putc(struct udevice *dev, const char ch)
{
- struct s5p_serial_platdata *plat = dev->plat;
+ struct s5p_serial_plat *plat = dev->plat;
struct s5p_uart *const uart = plat->reg;
if (readl(&uart->ufstat) & TX_FIFO_FULL)
static int s5p_serial_pending(struct udevice *dev, bool input)
{
- struct s5p_serial_platdata *plat = dev->plat;
+ struct s5p_serial_plat *plat = dev->plat;
struct s5p_uart *const uart = plat->reg;
uint32_t ufstat = readl(&uart->ufstat);
static int s5p_serial_of_to_plat(struct udevice *dev)
{
- struct s5p_serial_platdata *plat = dev->plat;
+ struct s5p_serial_plat *plat = dev->plat;
fdt_addr_t addr;
addr = dev_read_addr(dev);
.id = UCLASS_SERIAL,
.of_match = s5p_serial_ids,
.of_to_plat = s5p_serial_of_to_plat,
- .plat_auto = sizeof(struct s5p_serial_platdata),
+ .plat_auto = sizeof(struct s5p_serial_plat),
.probe = s5p_serial_probe,
.ops = &s5p_serial_ops,
};
static int sh_serial_setbrg(struct udevice *dev, int baudrate)
{
- struct sh_serial_platdata *plat = dev_get_plat(dev);
+ struct sh_serial_plat *plat = dev_get_plat(dev);
struct uart_port *priv = dev_get_priv(dev);
sh_serial_setbrg_generic(priv, plat->clk, baudrate);
static int sh_serial_probe(struct udevice *dev)
{
- struct sh_serial_platdata *plat = dev_get_plat(dev);
+ struct sh_serial_plat *plat = dev_get_plat(dev);
struct uart_port *priv = dev_get_priv(dev);
priv->membase = (unsigned char *)plat->base;
static int sh_serial_of_to_plat(struct udevice *dev)
{
- struct sh_serial_platdata *plat = dev_get_plat(dev);
+ struct sh_serial_plat *plat = dev_get_plat(dev);
struct clk sh_serial_clk;
fdt_addr_t addr;
int ret;
.id = UCLASS_SERIAL,
.of_match = of_match_ptr(sh_serial_id),
.of_to_plat = of_match_ptr(sh_serial_of_to_plat),
- .plat_auto = sizeof(struct sh_serial_platdata),
+ .plat_auto = sizeof(struct sh_serial_plat),
.probe = sh_serial_probe,
.ops = &sh_serial_ops,
#if !CONFIG_IS_ENABLED(OF_CONTROL)
u32 div;
};
-struct sifive_uart_platdata {
+struct sifive_uart_plat {
unsigned long clock;
struct uart_sifive *regs;
};
{
int ret;
struct clk clk;
- struct sifive_uart_platdata *plat = dev_get_plat(dev);
+ struct sifive_uart_plat *plat = dev_get_plat(dev);
u32 clock = 0;
ret = clk_get_by_index(dev, 0, &clk);
static int sifive_serial_probe(struct udevice *dev)
{
- struct sifive_uart_platdata *plat = dev_get_plat(dev);
+ struct sifive_uart_plat *plat = dev_get_plat(dev);
/* No need to reinitialize the UART after relocation */
if (gd->flags & GD_FLG_RELOC)
static int sifive_serial_getc(struct udevice *dev)
{
int c;
- struct sifive_uart_platdata *plat = dev_get_plat(dev);
+ struct sifive_uart_plat *plat = dev_get_plat(dev);
struct uart_sifive *regs = plat->regs;
while ((c = _sifive_serial_getc(regs)) == -EAGAIN) ;
static int sifive_serial_putc(struct udevice *dev, const char ch)
{
int rc;
- struct sifive_uart_platdata *plat = dev_get_plat(dev);
+ struct sifive_uart_plat *plat = dev_get_plat(dev);
while ((rc = _sifive_serial_putc(plat->regs, ch)) == -EAGAIN) ;
static int sifive_serial_pending(struct udevice *dev, bool input)
{
- struct sifive_uart_platdata *plat = dev_get_plat(dev);
+ struct sifive_uart_plat *plat = dev_get_plat(dev);
struct uart_sifive *regs = plat->regs;
if (input)
static int sifive_serial_of_to_plat(struct udevice *dev)
{
- struct sifive_uart_platdata *plat = dev_get_plat(dev);
+ struct sifive_uart_plat *plat = dev_get_plat(dev);
plat->regs = (struct uart_sifive *)dev_read_addr(dev);
if (IS_ERR(plat->regs))
.id = UCLASS_SERIAL,
.of_match = sifive_serial_ids,
.of_to_plat = sifive_serial_of_to_plat,
- .plat_auto = sizeof(struct sifive_uart_platdata),
+ .plat_auto = sizeof(struct sifive_uart_plat),
.probe = sifive_serial_probe,
.ops = &sifive_serial_ops,
};
static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
{
- struct stm32x7_serial_platdata *plat = dev_get_plat(dev);
+ struct stm32x7_serial_plat *plat = dev_get_plat(dev);
_stm32_serial_setbrg(plat->base, plat->uart_info,
plat->clock_rate, baudrate);
static int stm32_serial_setconfig(struct udevice *dev, uint serial_config)
{
- struct stm32x7_serial_platdata *plat = dev_get_plat(dev);
+ struct stm32x7_serial_plat *plat = dev_get_plat(dev);
bool stm32f4 = plat->uart_info->stm32f4;
u8 uart_enable_bit = plat->uart_info->uart_enable_bit;
u32 cr1 = plat->base + CR1_OFFSET(stm32f4);
static int stm32_serial_getc(struct udevice *dev)
{
- struct stm32x7_serial_platdata *plat = dev_get_plat(dev);
+ struct stm32x7_serial_plat *plat = dev_get_plat(dev);
bool stm32f4 = plat->uart_info->stm32f4;
fdt_addr_t base = plat->base;
u32 isr = readl(base + ISR_OFFSET(stm32f4));
static int stm32_serial_putc(struct udevice *dev, const char c)
{
- struct stm32x7_serial_platdata *plat = dev_get_plat(dev);
+ struct stm32x7_serial_plat *plat = dev_get_plat(dev);
return _stm32_serial_putc(plat->base, plat->uart_info, c);
}
static int stm32_serial_pending(struct udevice *dev, bool input)
{
- struct stm32x7_serial_platdata *plat = dev_get_plat(dev);
+ struct stm32x7_serial_plat *plat = dev_get_plat(dev);
bool stm32f4 = plat->uart_info->stm32f4;
fdt_addr_t base = plat->base;
static int stm32_serial_probe(struct udevice *dev)
{
- struct stm32x7_serial_platdata *plat = dev_get_plat(dev);
+ struct stm32x7_serial_plat *plat = dev_get_plat(dev);
struct clk clk;
struct reset_ctl reset;
int ret;
static int stm32_serial_of_to_plat(struct udevice *dev)
{
- struct stm32x7_serial_platdata *plat = dev_get_plat(dev);
+ struct stm32x7_serial_plat *plat = dev_get_plat(dev);
plat->base = dev_read_addr(dev);
if (plat->base == FDT_ADDR_T_NONE)
.id = UCLASS_SERIAL,
.of_match = of_match_ptr(stm32_serial_id),
.of_to_plat = of_match_ptr(stm32_serial_of_to_plat),
- .plat_auto = sizeof(struct stm32x7_serial_platdata),
+ .plat_auto = sizeof(struct stm32x7_serial_plat),
.ops = &stm32_serial_ops,
.probe = stm32_serial_probe,
#if !CONFIG_IS_ENABLED(OF_CONTROL)
};
/* Information about a serial port */
-struct stm32x7_serial_platdata {
+struct stm32x7_serial_plat {
fdt_addr_t base; /* address of registers in physical memory */
struct stm32_uart_info *uart_info;
unsigned long int clock_rate;
unsigned int control;
};
-struct uartlite_platdata {
+struct uartlite_plat {
struct uartlite *regs;
};
static int uartlite_serial_putc(struct udevice *dev, const char ch)
{
- struct uartlite_platdata *plat = dev_get_plat(dev);
+ struct uartlite_plat *plat = dev_get_plat(dev);
struct uartlite *regs = plat->regs;
if (uart_in32(®s->status) & SR_TX_FIFO_FULL)
static int uartlite_serial_getc(struct udevice *dev)
{
- struct uartlite_platdata *plat = dev_get_plat(dev);
+ struct uartlite_plat *plat = dev_get_plat(dev);
struct uartlite *regs = plat->regs;
if (!(uart_in32(®s->status) & SR_RX_FIFO_VALID_DATA))
static int uartlite_serial_pending(struct udevice *dev, bool input)
{
- struct uartlite_platdata *plat = dev_get_plat(dev);
+ struct uartlite_plat *plat = dev_get_plat(dev);
struct uartlite *regs = plat->regs;
if (input)
static int uartlite_serial_probe(struct udevice *dev)
{
- struct uartlite_platdata *plat = dev_get_plat(dev);
+ struct uartlite_plat *plat = dev_get_plat(dev);
struct uartlite *regs = plat->regs;
int ret;
static int uartlite_serial_of_to_plat(struct udevice *dev)
{
- struct uartlite_platdata *plat = dev_get_plat(dev);
+ struct uartlite_plat *plat = dev_get_plat(dev);
plat->regs = dev_read_addr_ptr(dev);
.id = UCLASS_SERIAL,
.of_match = uartlite_serial_ids,
.of_to_plat = uartlite_serial_of_to_plat,
- .plat_auto = sizeof(struct uartlite_platdata),
+ .plat_auto = sizeof(struct uartlite_plat),
.probe = uartlite_serial_probe,
.ops = &uartlite_serial_ops,
};
u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */
};
-struct zynq_uart_platdata {
+struct zynq_uart_plat {
struct uart_zynq *regs;
};
static int zynq_serial_setbrg(struct udevice *dev, int baudrate)
{
- struct zynq_uart_platdata *plat = dev_get_plat(dev);
+ struct zynq_uart_plat *plat = dev_get_plat(dev);
unsigned long clock;
int ret;
static int zynq_serial_probe(struct udevice *dev)
{
- struct zynq_uart_platdata *plat = dev_get_plat(dev);
+ struct zynq_uart_plat *plat = dev_get_plat(dev);
struct uart_zynq *regs = plat->regs;
u32 val;
static int zynq_serial_getc(struct udevice *dev)
{
- struct zynq_uart_platdata *plat = dev_get_plat(dev);
+ struct zynq_uart_plat *plat = dev_get_plat(dev);
struct uart_zynq *regs = plat->regs;
if (readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY)
static int zynq_serial_putc(struct udevice *dev, const char ch)
{
- struct zynq_uart_platdata *plat = dev_get_plat(dev);
+ struct zynq_uart_plat *plat = dev_get_plat(dev);
return _uart_zynq_serial_putc(plat->regs, ch);
}
static int zynq_serial_pending(struct udevice *dev, bool input)
{
- struct zynq_uart_platdata *plat = dev_get_plat(dev);
+ struct zynq_uart_plat *plat = dev_get_plat(dev);
struct uart_zynq *regs = plat->regs;
if (input)
static int zynq_serial_of_to_plat(struct udevice *dev)
{
- struct zynq_uart_platdata *plat = dev_get_plat(dev);
+ struct zynq_uart_plat *plat = dev_get_plat(dev);
plat->regs = (struct uart_zynq *)dev_read_addr(dev);
if (IS_ERR(plat->regs))
.id = UCLASS_SERIAL,
.of_match = zynq_serial_ids,
.of_to_plat = zynq_serial_of_to_plat,
- .plat_auto = sizeof(struct zynq_uart_platdata),
+ .plat_auto = sizeof(struct zynq_uart_plat),
.probe = zynq_serial_probe,
.ops = &zynq_serial_ops,
};
#define JTAG_ID_PARTNO_SHIFT 12
#define JTAG_ID_PARTNO_MASK (0xffff << 12)
-struct soc_ti_k3_platdata {
+struct soc_ti_k3_plat {
const char *family;
const char *revision;
};
static int soc_ti_k3_get_family(struct udevice *dev, char *buf, int size)
{
- struct soc_ti_k3_platdata *plat = dev_get_plat(dev);
+ struct soc_ti_k3_plat *plat = dev_get_plat(dev);
snprintf(buf, size, "%s", plat->family);
static int soc_ti_k3_get_revision(struct udevice *dev, char *buf, int size)
{
- struct soc_ti_k3_platdata *plat = dev_get_plat(dev);
+ struct soc_ti_k3_plat *plat = dev_get_plat(dev);
snprintf(buf, size, "SR%s", plat->revision);
int soc_ti_k3_probe(struct udevice *dev)
{
- struct soc_ti_k3_platdata *plat = dev_get_plat(dev);
+ struct soc_ti_k3_plat *plat = dev_get_plat(dev);
u32 idreg;
void *idreg_addr;
.ops = &soc_ti_k3_ops,
.of_match = soc_ti_k3_ids,
.probe = soc_ti_k3_probe,
- .plat_auto = sizeof(struct soc_ti_k3_platdata),
+ .plat_auto = sizeof(struct soc_ti_k3_plat),
};
static int bd82x6x_azalia_probe(struct udevice *dev)
{
- struct pci_child_platdata *plat;
+ struct pci_child_plat *plat;
struct hda_codec_priv *priv;
struct udevice *pch;
u32 codec_mask;
u32 slave_sel;
};
-struct altera_spi_platdata {
+struct altera_spi_plat {
struct altera_spi_regs *regs;
};
struct udevice *bus = dev->parent;
struct altera_spi_priv *priv = dev_get_priv(bus);
struct altera_spi_regs *const regs = priv->regs;
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
/* assume spi core configured to do 8 bit transfers */
unsigned int bytes = bitlen / 8;
static int altera_spi_probe(struct udevice *bus)
{
- struct altera_spi_platdata *plat = dev_get_plat(bus);
+ struct altera_spi_plat *plat = dev_get_plat(bus);
struct altera_spi_priv *priv = dev_get_priv(bus);
priv->regs = plat->regs;
static int altera_spi_of_to_plat(struct udevice *bus)
{
- struct altera_spi_platdata *plat = dev_get_plat(bus);
+ struct altera_spi_plat *plat = dev_get_plat(bus);
plat->regs = map_physmem(dev_read_addr(bus),
sizeof(struct altera_spi_regs),
.of_match = altera_spi_ids,
.ops = &altera_spi_ops,
.of_to_plat = altera_spi_of_to_plat,
- .plat_auto = sizeof(struct altera_spi_platdata),
+ .plat_auto = sizeof(struct altera_spi_plat),
.priv_auto = sizeof(struct altera_spi_priv),
.probe = altera_spi_probe,
};
static int atcspi200_spi_claim_bus(struct udevice *dev)
{
- struct dm_spi_slave_platdata *slave_plat =
+ struct dm_spi_slave_plat *slave_plat =
dev_get_parent_plat(dev);
struct udevice *bus = dev->parent;
struct nds_spi_slave *ns = dev_get_priv(bus);
{
struct udevice *bus = dev_get_parent(dev);
struct ath79_spi_priv *priv = dev_get_priv(bus);
- struct dm_spi_slave_platdata *slave = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *slave = dev_get_parent_plat(dev);
u8 *rx = din;
const u8 *tx = dout;
u8 curbyte, curbitlen, restbits;
#define spi_writel(as, reg, value) \
writel(value, as->regs + ATMEL_SPI_##reg)
-struct atmel_spi_platdata {
+struct atmel_spi_plat {
struct at91_spi *regs;
};
static int atmel_spi_claim_bus(struct udevice *dev)
{
struct udevice *bus = dev_get_parent(dev);
- struct atmel_spi_platdata *bus_plat = dev_get_plat(bus);
+ struct atmel_spi_plat *bus_plat = dev_get_plat(bus);
struct atmel_spi_priv *priv = dev_get_priv(bus);
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
struct at91_spi *reg_base = bus_plat->regs;
u32 cs = slave_plat->cs;
u32 freq = priv->freq;
static int atmel_spi_release_bus(struct udevice *dev)
{
struct udevice *bus = dev_get_parent(dev);
- struct atmel_spi_platdata *bus_plat = dev_get_plat(bus);
+ struct atmel_spi_plat *bus_plat = dev_get_plat(bus);
writel(ATMEL_SPI_CR_SPIDIS, &bus_plat->regs->cr);
#if CONFIG_IS_ENABLED(DM_GPIO)
struct udevice *bus = dev_get_parent(dev);
struct atmel_spi_priv *priv = dev_get_priv(bus);
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
u32 cs = slave_plat->cs;
if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
#if CONFIG_IS_ENABLED(DM_GPIO)
struct udevice *bus = dev_get_parent(dev);
struct atmel_spi_priv *priv = dev_get_priv(bus);
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
u32 cs = slave_plat->cs;
if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
const void *dout, void *din, unsigned long flags)
{
struct udevice *bus = dev_get_parent(dev);
- struct atmel_spi_platdata *bus_plat = dev_get_plat(bus);
+ struct atmel_spi_plat *bus_plat = dev_get_plat(bus);
struct at91_spi *reg_base = bus_plat->regs;
u32 len_tx, len_rx, len;
static int atmel_spi_probe(struct udevice *bus)
{
- struct atmel_spi_platdata *bus_plat = dev_get_plat(bus);
+ struct atmel_spi_plat *bus_plat = dev_get_plat(bus);
int ret;
ret = atmel_spi_enable_clk(bus);
.id = UCLASS_SPI,
.of_match = atmel_spi_ids,
.ops = &atmel_spi_ops,
- .plat_auto = sizeof(struct atmel_spi_platdata),
+ .plat_auto = sizeof(struct atmel_spi_plat),
.priv_auto = sizeof(struct atmel_spi_priv),
.probe = atmel_spi_probe,
};
}
static void bcm63xx_hsspi_activate_cs(struct bcm63xx_hsspi_priv *priv,
- struct dm_spi_slave_platdata *plat)
+ struct dm_spi_slave_plat *plat)
{
uint32_t clr, set;
const void *dout, void *din, unsigned long flags)
{
struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent);
- struct dm_spi_slave_platdata *plat = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);
size_t data_bytes = bitlen / 8;
size_t step_size = HSSPI_FIFO_SIZE;
uint16_t opcode = 0;
static int bcm63xx_hsspi_child_pre_probe(struct udevice *dev)
{
struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent);
- struct dm_spi_slave_platdata *plat = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);
/* check cs */
if (plat->cs >= priv->num_cs) {
}
if (flags & SPI_XFER_END) {
- struct dm_spi_slave_platdata *plat =
+ struct dm_spi_slave_plat *plat =
dev_get_parent_plat(dev);
uint16_t val, cmd;
int ret;
struct bcm63xx_spi_priv *priv = dev_get_priv(dev->parent);
const unsigned long *regs = priv->regs;
struct spi_slave *slave = dev_get_parent_priv(dev);
- struct dm_spi_slave_platdata *plat = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);
/* check cs */
if (plat->cs >= priv->num_cs) {
BASE_LAST,
};
-struct bcmstb_spi_platdata {
+struct bcmstb_spi_plat {
void *base[4];
};
static int bcmstb_spi_of_to_plat(struct udevice *bus)
{
- struct bcmstb_spi_platdata *plat = dev_get_plat(bus);
+ struct bcmstb_spi_plat *plat = dev_get_plat(bus);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(bus);
int ret = 0;
static int bcmstb_spi_probe(struct udevice *bus)
{
- struct bcmstb_spi_platdata *plat = dev_get_plat(bus);
+ struct bcmstb_spi_plat *plat = dev_get_plat(bus);
struct bcmstb_spi_priv *priv = dev_get_priv(bus);
priv->regs = plat->base[HIF_MSPI];
.ops = &bcmstb_spi_ops,
.of_to_plat = bcmstb_spi_of_to_plat,
.probe = bcmstb_spi_probe,
- .plat_auto = sizeof(struct bcmstb_spi_platdata),
+ .plat_auto = sizeof(struct bcmstb_spi_plat),
.priv_auto = sizeof(struct bcmstb_spi_priv),
};
static int cadence_spi_write_speed(struct udevice *bus, uint hz)
{
- struct cadence_spi_platdata *plat = bus->plat;
+ struct cadence_spi_plat *plat = bus->plat;
struct cadence_spi_priv *priv = dev_get_priv(bus);
cadence_qspi_apb_config_baudrate_div(priv->regbase,
static int cadence_spi_set_speed(struct udevice *bus, uint hz)
{
- struct cadence_spi_platdata *plat = bus->plat;
+ struct cadence_spi_plat *plat = bus->plat;
struct cadence_spi_priv *priv = dev_get_priv(bus);
int err;
static int cadence_spi_probe(struct udevice *bus)
{
- struct cadence_spi_platdata *plat = bus->plat;
+ struct cadence_spi_plat *plat = bus->plat;
struct cadence_spi_priv *priv = dev_get_priv(bus);
struct clk clk;
int ret;
static int cadence_spi_set_mode(struct udevice *bus, uint mode)
{
- struct cadence_spi_platdata *plat = bus->plat;
+ struct cadence_spi_plat *plat = bus->plat;
struct cadence_spi_priv *priv = dev_get_priv(bus);
/* Disable QSPI */
const struct spi_mem_op *op)
{
struct udevice *bus = spi->dev->parent;
- struct cadence_spi_platdata *plat = bus->plat;
+ struct cadence_spi_plat *plat = bus->plat;
struct cadence_spi_priv *priv = dev_get_priv(bus);
void *base = priv->regbase;
int err = 0;
static int cadence_spi_of_to_plat(struct udevice *bus)
{
- struct cadence_spi_platdata *plat = bus->plat;
+ struct cadence_spi_plat *plat = bus->plat;
ofnode subnode;
plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
.of_match = cadence_spi_ids,
.ops = &cadence_spi_ops,
.of_to_plat = cadence_spi_of_to_plat,
- .plat_auto = sizeof(struct cadence_spi_platdata),
+ .plat_auto = sizeof(struct cadence_spi_plat),
.priv_auto = sizeof(struct cadence_spi_priv),
.probe = cadence_spi_probe,
.remove = cadence_spi_remove,
#define CQSPI_DECODER_MAX_CS 16
#define CQSPI_READ_CAPTURE_MAX_DELAY 16
-struct cadence_spi_platdata {
+struct cadence_spi_plat {
unsigned int ref_clk_hz;
unsigned int max_hz;
void *regbase;
};
/* Functions call declaration */
-void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat);
+void cadence_qspi_apb_controller_init(struct cadence_spi_plat *plat);
void cadence_qspi_apb_controller_enable(void *reg_base_addr);
void cadence_qspi_apb_controller_disable(void *reg_base_addr);
void cadence_qspi_apb_dac_mode_enable(void *reg_base);
int cadence_qspi_apb_command_write(void *reg_base_addr,
const struct spi_mem_op *op);
-int cadence_qspi_apb_read_setup(struct cadence_spi_platdata *plat,
+int cadence_qspi_apb_read_setup(struct cadence_spi_plat *plat,
const struct spi_mem_op *op);
-int cadence_qspi_apb_read_execute(struct cadence_spi_platdata *plat,
+int cadence_qspi_apb_read_execute(struct cadence_spi_plat *plat,
const struct spi_mem_op *op);
-int cadence_qspi_apb_write_setup(struct cadence_spi_platdata *plat,
+int cadence_qspi_apb_write_setup(struct cadence_spi_plat *plat,
const struct spi_mem_op *op);
-int cadence_qspi_apb_write_execute(struct cadence_spi_platdata *plat,
+int cadence_qspi_apb_write_execute(struct cadence_spi_plat *plat,
const struct spi_mem_op *op);
void cadence_qspi_apb_chipselect(void *reg_base,
cadence_qspi_apb_controller_enable(reg_base);
}
-void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
+void cadence_qspi_apb_controller_init(struct cadence_spi_plat *plat)
{
unsigned reg;
}
/* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */
-int cadence_qspi_apb_read_setup(struct cadence_spi_platdata *plat,
+int cadence_qspi_apb_read_setup(struct cadence_spi_plat *plat,
const struct spi_mem_op *op)
{
unsigned int reg;
return 0;
}
-static u32 cadence_qspi_get_rd_sram_level(struct cadence_spi_platdata *plat)
+static u32 cadence_qspi_get_rd_sram_level(struct cadence_spi_plat *plat)
{
u32 reg = readl(plat->regbase + CQSPI_REG_SDRAMLEVEL);
reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
}
-static int cadence_qspi_wait_for_data(struct cadence_spi_platdata *plat)
+static int cadence_qspi_wait_for_data(struct cadence_spi_plat *plat)
{
unsigned int timeout = 10000;
u32 reg;
}
static int
-cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
+cadence_qspi_apb_indirect_read_execute(struct cadence_spi_plat *plat,
unsigned int n_rx, u8 *rxbuf)
{
unsigned int remaining = n_rx;
return ret;
}
-int cadence_qspi_apb_read_execute(struct cadence_spi_platdata *plat,
+int cadence_qspi_apb_read_execute(struct cadence_spi_plat *plat,
const struct spi_mem_op *op)
{
u64 from = op->addr.val;
}
/* Opcode + Address (3/4 bytes) */
-int cadence_qspi_apb_write_setup(struct cadence_spi_platdata *plat,
+int cadence_qspi_apb_write_setup(struct cadence_spi_plat *plat,
const struct spi_mem_op *op)
{
unsigned int reg;
}
static int
-cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
+cadence_qspi_apb_indirect_write_execute(struct cadence_spi_plat *plat,
unsigned int n_tx, const u8 *txbuf)
{
unsigned int page_size = plat->page_size;
return ret;
}
-int cadence_qspi_apb_write_execute(struct cadence_spi_platdata *plat,
+int cadence_qspi_apb_write_execute(struct cadence_spi_plat *plat,
const struct spi_mem_op *op)
{
u32 to = op->addr.val;
struct udevice *bus = dev->parent;
struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
struct dspi *dspi = cfspi->regs;
- struct dm_spi_slave_platdata *slave_plat =
+ struct dm_spi_slave_plat *slave_plat =
dev_get_parent_plat(dev);
if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
struct udevice *bus = dev->parent;
struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
struct dspi *dspi = cfspi->regs;
- struct dm_spi_slave_platdata *slave_plat =
+ struct dm_spi_slave_plat *slave_plat =
dev_get_parent_plat(dev);
/* Clear FIFO */
{
struct udevice *bus = dev_get_parent(dev);
struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
u8 *spi_rd = NULL, *spi_wr = NULL;
static u32 ctrl;
static int coldfire_spi_probe(struct udevice *bus)
{
- struct coldfire_spi_platdata *plat = dev_get_plat(bus);
+ struct coldfire_spi_plat *plat = dev_get_plat(bus);
struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
struct dspi *dspi = cfspi->regs;
int i;
static int coldfire_dspi_of_to_plat(struct udevice *bus)
{
fdt_addr_t addr;
- struct coldfire_spi_platdata *plat = bus->plat;
+ struct coldfire_spi_plat *plat = bus->plat;
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
int *ctar, len;
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.of_match = coldfire_spi_ids,
.of_to_plat = coldfire_dspi_of_to_plat,
- .plat_auto = sizeof(struct coldfire_spi_platdata),
+ .plat_auto = sizeof(struct coldfire_spi_plat),
#endif
.probe = coldfire_spi_probe,
.ops = &coldfire_spi_ops,
static int davinci_spi_claim_bus(struct udevice *dev)
{
- struct dm_spi_slave_platdata *slave_plat =
+ struct dm_spi_slave_plat *slave_plat =
dev_get_parent_plat(dev);
struct udevice *bus = dev->parent;
struct davinci_spi_slave *ds = dev_get_priv(bus);
const void *dout, void *din,
unsigned long flags)
{
- struct dm_spi_slave_platdata *slave =
+ struct dm_spi_slave_plat *slave =
dev_get_parent_plat(dev);
struct udevice *bus = dev->parent;
struct davinci_spi_slave *ds = dev_get_priv(bus);
static int davinci_spi_probe(struct udevice *bus)
{
struct davinci_spi_slave *ds = dev_get_priv(bus);
- struct davinci_spi_platdata *plat = bus->plat;
+ struct davinci_spi_plat *plat = bus->plat;
ds->regs = plat->regs;
ds->num_cs = plat->num_cs;
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
static int davinci_ofdata_to_platadata(struct udevice *bus)
{
- struct davinci_spi_platdata *plat = bus->plat;
+ struct davinci_spi_plat *plat = bus->plat;
fdt_addr_t addr;
addr = dev_read_addr(bus);
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.of_match = davinci_spi_ids,
.of_to_plat = davinci_ofdata_to_platadata,
- .plat_auto = sizeof(struct davinci_spi_platdata),
+ .plat_auto = sizeof(struct davinci_spi_plat),
#endif
.probe = davinci_spi_probe,
.ops = &davinci_spi_ops,
#define RX_TIMEOUT 1000 /* timeout in ms */
-struct dw_spi_platdata {
+struct dw_spi_plat {
s32 frequency; /* Default clock frequency, -1 for none */
void __iomem *regs;
};
static int dw_spi_of_to_plat(struct udevice *bus)
{
- struct dw_spi_platdata *plat = bus->plat;
+ struct dw_spi_plat *plat = bus->plat;
plat->regs = dev_read_addr_ptr(bus);
static int dw_spi_probe(struct udevice *bus)
{
- struct dw_spi_platdata *plat = dev_get_plat(bus);
+ struct dw_spi_plat *plat = dev_get_plat(bus);
struct dw_spi_priv *priv = dev_get_priv(bus);
int ret;
static int dw_spi_set_speed(struct udevice *bus, uint speed)
{
- struct dw_spi_platdata *plat = bus->plat;
+ struct dw_spi_plat *plat = bus->plat;
struct dw_spi_priv *priv = dev_get_priv(bus);
u16 clk_div;
.of_match = dw_spi_ids,
.ops = &dw_spi_ops,
.of_to_plat = dw_spi_of_to_plat,
- .plat_auto = sizeof(struct dw_spi_platdata),
+ .plat_auto = sizeof(struct dw_spi_plat),
.priv_auto = sizeof(struct dw_spi_priv),
.probe = dw_spi_probe,
.remove = dw_spi_remove,
DECLARE_GLOBAL_DATA_PTR;
-struct exynos_spi_platdata {
+struct exynos_spi_plat {
enum periph_id periph_id;
s32 frequency; /* Default clock frequency, -1 for none */
struct exynos_spi *regs;
static void spi_cs_activate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct exynos_spi_platdata *pdata = dev_get_plat(bus);
+ struct exynos_spi_plat *pdata = dev_get_plat(bus);
struct exynos_spi_priv *priv = dev_get_priv(bus);
/* If it's too soon to do another transaction, wait */
static void spi_cs_deactivate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct exynos_spi_platdata *pdata = dev_get_plat(bus);
+ struct exynos_spi_plat *pdata = dev_get_plat(bus);
struct exynos_spi_priv *priv = dev_get_priv(bus);
setbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT);
static int exynos_spi_of_to_plat(struct udevice *bus)
{
- struct exynos_spi_platdata *plat = bus->plat;
+ struct exynos_spi_plat *plat = bus->plat;
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
static int exynos_spi_probe(struct udevice *bus)
{
- struct exynos_spi_platdata *plat = dev_get_plat(bus);
+ struct exynos_spi_plat *plat = dev_get_plat(bus);
struct exynos_spi_priv *priv = dev_get_priv(bus);
priv->regs = plat->regs;
static int exynos_spi_set_speed(struct udevice *bus, uint speed)
{
- struct exynos_spi_platdata *plat = bus->plat;
+ struct exynos_spi_plat *plat = bus->plat;
struct exynos_spi_priv *priv = dev_get_priv(bus);
int ret;
.of_match = exynos_spi_ids,
.ops = &exynos_spi_ops,
.of_to_plat = exynos_spi_of_to_plat,
- .plat_auto = sizeof(struct exynos_spi_platdata),
+ .plat_auto = sizeof(struct exynos_spi_plat),
.priv_auto = sizeof(struct exynos_spi_priv),
.probe = exynos_spi_probe,
};
DECLARE_GLOBAL_DATA_PTR;
-/* fsl_dspi_platdata flags */
+/* fsl_dspi_plat flags */
#define DSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0)
/* idle data value */
DSPI_CTAR_DT(15))
/**
- * struct fsl_dspi_platdata - platform data for Freescale DSPI
+ * struct fsl_dspi_plat - platform data for Freescale DSPI
*
* @flags: Flags for DSPI DSPI_FLAG_...
* @speed_hz: Default SCK frequency
* @num_chipselect: Number of DSPI chipselect signals
* @regs_addr: Base address of DSPI registers
*/
-struct fsl_dspi_platdata {
+struct fsl_dspi_plat {
uint flags;
uint speed_hz;
uint num_chipselect;
static int fsl_dspi_child_pre_probe(struct udevice *dev)
{
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
struct fsl_dspi_priv *priv = dev_get_priv(dev->parent);
u32 cs_sck_delay = 0, sck_cs_delay = 0;
unsigned char pcssck = 0, cssck = 0;
static int fsl_dspi_probe(struct udevice *bus)
{
- struct fsl_dspi_platdata *plat = dev_get_plat(bus);
+ struct fsl_dspi_plat *plat = dev_get_plat(bus);
struct fsl_dspi_priv *priv = dev_get_priv(bus);
struct dm_spi_bus *dm_spi_bus;
uint mcr_cfg_val;
uint sr_val;
struct fsl_dspi_priv *priv;
struct udevice *bus = dev->parent;
- struct dm_spi_slave_platdata *slave_plat =
+ struct dm_spi_slave_plat *slave_plat =
dev_get_parent_plat(dev);
priv = dev_get_priv(bus);
{
struct udevice *bus = dev->parent;
struct fsl_dspi_priv *priv = dev_get_priv(bus);
- struct dm_spi_slave_platdata *slave_plat =
+ struct dm_spi_slave_plat *slave_plat =
dev_get_parent_plat(dev);
/* halt module */
static int fsl_dspi_of_to_plat(struct udevice *bus)
{
fdt_addr_t addr;
- struct fsl_dspi_platdata *plat = bus->plat;
+ struct fsl_dspi_plat *plat = bus->plat;
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
const void *dout, void *din, unsigned long flags)
{
struct fsl_dspi_priv *priv;
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
struct udevice *bus;
bus = dev->parent;
.of_match = fsl_dspi_ids,
.ops = &fsl_dspi_ops,
.of_to_plat = fsl_dspi_of_to_plat,
- .plat_auto = sizeof(struct fsl_dspi_platdata),
+ .plat_auto = sizeof(struct fsl_dspi_plat),
.priv_auto = sizeof(struct fsl_dspi_priv),
.probe = fsl_dspi_probe,
.child_pre_probe = fsl_dspi_child_pre_probe,
static int fsl_espi_child_pre_probe(struct udevice *dev)
{
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
struct udevice *bus = dev->parent;
struct fsl_spi_slave *fsl = dev_get_priv(bus);
static int fsl_espi_probe(struct udevice *bus)
{
- struct fsl_espi_platdata *plat = dev_get_plat(bus);
+ struct fsl_espi_plat *plat = dev_get_plat(bus);
struct fsl_spi_slave *fsl = dev_get_priv(bus);
fsl->espi = (ccsr_espi_t *)((u32)plat->regs_addr);
static int fsl_espi_of_to_plat(struct udevice *bus)
{
fdt_addr_t addr;
- struct fsl_espi_platdata *plat = bus->plat;
+ struct fsl_espi_plat *plat = bus->plat;
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
.of_to_plat = fsl_espi_of_to_plat,
#endif
.ops = &fsl_espi_ops,
- .plat_auto = sizeof(struct fsl_espi_platdata),
+ .plat_auto = sizeof(struct fsl_espi_plat),
.priv_auto = sizeof(struct fsl_spi_slave),
.probe = fsl_espi_probe,
.child_pre_probe = fsl_espi_child_pre_probe,
static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_slave *slave)
{
- struct dm_spi_slave_platdata *plat =
+ struct dm_spi_slave_plat *plat =
dev_get_parent_plat(slave->dev);
if (q->selected == plat->cs)
#define debug_trace(x, args...)
#endif
-struct ich_spi_platdata {
+struct ich_spi_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_intel_fast_spi dtplat;
#endif
return speed == 1;
}
-static void spi_lock_down(struct ich_spi_platdata *plat, void *sbase)
+static void spi_lock_down(struct ich_spi_plat *plat, void *sbase)
{
if (plat->ich_version == ICHV_7) {
struct ich7_spi_regs *ich7_spi = sbase;
}
}
-static bool spi_lock_status(struct ich_spi_platdata *plat, void *sbase)
+static bool spi_lock_status(struct ich_spi_plat *plat, void *sbase)
{
int lock = 0;
const struct spi_mem_op *op)
{
struct udevice *bus = dev_get_parent(slave->dev);
- struct ich_spi_platdata *plat = dev_get_plat(bus);
+ struct ich_spi_plat *plat = dev_get_plat(bus);
struct ich_spi_priv *ctlr = dev_get_priv(bus);
uint16_t control;
int16_t opcode_index;
static int ich_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
{
struct udevice *bus = dev_get_parent(slave->dev);
- struct ich_spi_platdata *plat = dev_get_plat(bus);
+ struct ich_spi_plat *plat = dev_get_plat(bus);
int ret;
bootstage_start(BOOTSTAGE_ID_ACCUM_SPI, "fast_spi");
pci_dev_t spi_bdf;
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
if (device_is_on_pci_bus(bus)) {
- struct pci_child_platdata *pplat;
+ struct pci_child_plat *pplat;
pplat = dev_get_parent_plat(bus);
spi_bdf = pplat->devfn;
offsetp);
}
#else
- struct ich_spi_platdata *plat = dev_get_plat(bus);
+ struct ich_spi_plat *plat = dev_get_plat(bus);
/*
* We cannot rely on plat->bdf being set up yet since this method can
static int ich_protect_lockdown(struct udevice *dev)
{
- struct ich_spi_platdata *plat = dev_get_plat(dev);
+ struct ich_spi_plat *plat = dev_get_plat(dev);
struct ich_spi_priv *priv = dev_get_priv(dev);
int ret = -ENOSYS;
}
static int ich_init_controller(struct udevice *dev,
- struct ich_spi_platdata *plat,
+ struct ich_spi_plat *plat,
struct ich_spi_priv *ctlr)
{
if (spl_phase() == PHASE_TPL) {
- struct ich_spi_platdata *plat = dev_get_plat(dev);
+ struct ich_spi_plat *plat = dev_get_plat(dev);
int ret;
ret = fast_spi_early_init(plat->bdf, plat->mmio_base);
static int ich_spi_probe(struct udevice *dev)
{
- struct ich_spi_platdata *plat = dev_get_plat(dev);
+ struct ich_spi_plat *plat = dev_get_plat(dev);
struct ich_spi_priv *priv = dev_get_priv(dev);
int ret;
static int ich_spi_child_pre_probe(struct udevice *dev)
{
struct udevice *bus = dev_get_parent(dev);
- struct ich_spi_platdata *plat = dev_get_plat(bus);
+ struct ich_spi_plat *plat = dev_get_plat(bus);
struct ich_spi_priv *priv = dev_get_priv(bus);
struct spi_slave *slave = dev_get_parent_priv(dev);
static int ich_spi_of_to_plat(struct udevice *dev)
{
- struct ich_spi_platdata *plat = dev_get_plat(dev);
+ struct ich_spi_plat *plat = dev_get_plat(dev);
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct ich_spi_priv *priv = dev_get_priv(dev);
.of_match = ich_spi_ids,
.ops = &ich_spi_ops,
.of_to_plat = ich_spi_of_to_plat,
- .plat_auto = sizeof(struct ich_spi_platdata),
+ .plat_auto = sizeof(struct ich_spi_plat),
.priv_auto = sizeof(struct ich_spi_priv),
.child_pre_probe = ich_spi_child_pre_probe,
.probe = ich_spi_probe,
bool is_errata_50mhz_ac;
};
-struct mvebu_spi_platdata {
+struct mvebu_spi_plat {
struct kwspi_registers *spireg;
bool is_errata_50mhz_ac;
};
static int mvebu_spi_set_speed(struct udevice *bus, uint hz)
{
- struct mvebu_spi_platdata *plat = dev_get_plat(bus);
+ struct mvebu_spi_plat *plat = dev_get_plat(bus);
struct kwspi_registers *reg = plat->spireg;
u32 data;
static void mvebu_spi_50mhz_ac_timing_erratum(struct udevice *bus, uint mode)
{
- struct mvebu_spi_platdata *plat = dev_get_plat(bus);
+ struct mvebu_spi_plat *plat = dev_get_plat(bus);
struct kwspi_registers *reg = plat->spireg;
u32 data;
static int mvebu_spi_set_mode(struct udevice *bus, uint mode)
{
- struct mvebu_spi_platdata *plat = dev_get_plat(bus);
+ struct mvebu_spi_plat *plat = dev_get_plat(bus);
struct kwspi_registers *reg = plat->spireg;
u32 data = readl(®->cfg);
const void *dout, void *din, unsigned long flags)
{
struct udevice *bus = dev->parent;
- struct mvebu_spi_platdata *plat = dev_get_plat(bus);
+ struct mvebu_spi_plat *plat = dev_get_plat(bus);
return _spi_xfer(plat->spireg, bitlen, dout, din, flags);
}
static int mvebu_spi_claim_bus(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct mvebu_spi_platdata *plat = dev_get_plat(bus);
+ struct mvebu_spi_plat *plat = dev_get_plat(bus);
/* Configure the chip-select in the CTRL register */
clrsetbits_le32(&plat->spireg->ctrl,
static int mvebu_spi_probe(struct udevice *bus)
{
- struct mvebu_spi_platdata *plat = dev_get_plat(bus);
+ struct mvebu_spi_plat *plat = dev_get_plat(bus);
struct kwspi_registers *reg = plat->spireg;
writel(KWSPI_SMEMRDY, ®->ctrl);
static int mvebu_spi_of_to_plat(struct udevice *bus)
{
- struct mvebu_spi_platdata *plat = dev_get_plat(bus);
+ struct mvebu_spi_plat *plat = dev_get_plat(bus);
const struct mvebu_spi_dev *drvdata =
(struct mvebu_spi_dev *)dev_get_driver_data(bus);
.of_match = mvebu_spi_ids,
.ops = &mvebu_spi_ops,
.of_to_plat = mvebu_spi_of_to_plat,
- .plat_auto = sizeof(struct mvebu_spi_platdata),
+ .plat_auto = sizeof(struct mvebu_spi_plat),
.priv_auto = sizeof(struct mvebu_spi_priv),
.probe = mvebu_spi_probe,
};
static void mpc8xxx_spi_cs_activate(struct udevice *dev)
{
struct mpc8xxx_priv *priv = dev_get_priv(dev->parent);
- struct dm_spi_slave_platdata *plat = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);
dm_gpio_set_value(&priv->gpios[plat->cs], 1);
}
static void mpc8xxx_spi_cs_deactivate(struct udevice *dev)
{
struct mpc8xxx_priv *priv = dev_get_priv(dev->parent);
- struct dm_spi_slave_platdata *plat = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);
dm_gpio_set_value(&priv->gpios[plat->cs], 0);
}
struct udevice *bus = dev->parent;
struct mpc8xxx_priv *priv = dev_get_priv(bus);
spi8xxx_t *spi = priv->spi;
- struct dm_spi_slave_platdata *plat = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);
u32 tmpdin = 0, tmpdout = 0, n;
const u8 *cout = dout;
u8 *cin = din;
const void *dout, void *din, unsigned long flags)
{
struct udevice *bus = dev_get_parent(dev);
- struct dm_spi_slave_platdata *plat = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);
struct mscc_bb_priv *priv = dev_get_priv(bus);
u32 i, count;
const u8 *txd = dout;
u32 din; /* 0x1060c */
};
-struct mvebu_spi_platdata {
+struct mvebu_spi_plat {
struct spi_reg *spireg;
struct clk clk;
struct gpio_desc cs_gpios[MAX_CS_COUNT];
};
-static void spi_cs_activate(struct mvebu_spi_platdata *plat, int cs)
+static void spi_cs_activate(struct mvebu_spi_plat *plat, int cs)
{
if (CONFIG_IS_ENABLED(DM_GPIO) && dm_gpio_is_valid(&plat->cs_gpios[cs]))
dm_gpio_set_value(&plat->cs_gpios[cs], 1);
setbits_le32(&plat->spireg->ctrl, MVEBU_SPI_A3700_SPI_EN_0 << cs);
}
-static void spi_cs_deactivate(struct mvebu_spi_platdata *plat, int cs)
+static void spi_cs_deactivate(struct mvebu_spi_plat *plat, int cs)
{
if (CONFIG_IS_ENABLED(DM_GPIO) && dm_gpio_is_valid(&plat->cs_gpios[cs]))
dm_gpio_set_value(&plat->cs_gpios[cs], 0);
const void *dout, void *din, unsigned long flags)
{
struct udevice *bus = dev->parent;
- struct mvebu_spi_platdata *plat = dev_get_plat(bus);
+ struct mvebu_spi_plat *plat = dev_get_plat(bus);
struct spi_reg *reg = plat->spireg;
unsigned int bytelen;
int ret;
static int mvebu_spi_set_speed(struct udevice *bus, uint hz)
{
- struct mvebu_spi_platdata *plat = dev_get_plat(bus);
+ struct mvebu_spi_plat *plat = dev_get_plat(bus);
struct spi_reg *reg = plat->spireg;
u32 data, prescale;
static int mvebu_spi_set_mode(struct udevice *bus, uint mode)
{
- struct mvebu_spi_platdata *plat = dev_get_plat(bus);
+ struct mvebu_spi_plat *plat = dev_get_plat(bus);
struct spi_reg *reg = plat->spireg;
/*
static int mvebu_spi_probe(struct udevice *bus)
{
- struct mvebu_spi_platdata *plat = dev_get_plat(bus);
+ struct mvebu_spi_plat *plat = dev_get_plat(bus);
struct spi_reg *reg = plat->spireg;
u32 data;
int ret;
static int mvebu_spi_of_to_plat(struct udevice *bus)
{
- struct mvebu_spi_platdata *plat = dev_get_plat(bus);
+ struct mvebu_spi_plat *plat = dev_get_plat(bus);
int ret;
plat->spireg = dev_read_addr_ptr(bus);
static int mvebu_spi_remove(struct udevice *bus)
{
- struct mvebu_spi_platdata *plat = dev_get_plat(bus);
+ struct mvebu_spi_plat *plat = dev_get_plat(bus);
clk_free(&plat->clk);
.of_match = mvebu_spi_ids,
.ops = &mvebu_spi_ops,
.of_to_plat = mvebu_spi_of_to_plat,
- .plat_auto = sizeof(struct mvebu_spi_platdata),
+ .plat_auto = sizeof(struct mvebu_spi_plat),
.probe = mvebu_spi_probe,
.remove = mvebu_spi_remove,
};
{
#if CONFIG_IS_ENABLED(DM_SPI)
struct udevice *dev = mxcs->dev;
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
u32 cs = slave_plat->cs;
{
#if CONFIG_IS_ENABLED(DM_SPI)
struct udevice *dev = mxcs->dev;
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
u32 cs = slave_plat->cs;
static int mxc_spi_claim_bus(struct udevice *dev)
{
struct mxc_spi_slave *mxcs = dev_get_plat(dev->parent);
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
mxcs->dev = dev;
#define MXS_SSP_IMX23_CLKID_SSP0 33
#define MXS_SSP_IMX28_CLKID_SSP0 46
-struct mxs_spi_platdata {
+struct mxs_spi_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_fsl_imx23_spi dtplat;
#endif
static int mxs_spi_probe(struct udevice *bus)
{
- struct mxs_spi_platdata *plat = dev_get_plat(bus);
+ struct mxs_spi_plat *plat = dev_get_plat(bus);
struct mxs_spi_priv *priv = dev_get_priv(bus);
int ret;
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
static int mxs_of_to_plat(struct udevice *bus)
{
- struct mxs_spi_platdata *plat = bus->plat;
+ struct mxs_spi_plat *plat = bus->plat;
u32 prop[2];
int ret;
.of_match = mxs_spi_ids,
.of_to_plat = mxs_of_to_plat,
#endif
- .plat_auto = sizeof(struct mxs_spi_platdata),
+ .plat_auto = sizeof(struct mxs_spi_plat),
.ops = &mxs_spi_ops,
.priv_auto = sizeof(struct mxs_spi_priv),
.probe = mxs_spi_probe,
{
struct nxp_fspi *f;
struct udevice *bus;
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
bus = dev->parent;
f = dev_get_priv(bus);
static u64 octeon_spi_set_mpicfg(struct udevice *dev)
{
- struct dm_spi_slave_platdata *slave = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *slave = dev_get_parent_plat(dev);
struct udevice *bus = dev_get_parent(dev);
struct octeon_spi *priv = dev_get_priv(bus);
u64 mpi_cfg;
{
struct udevice *bus = dev->parent;
struct omap3_spi_priv *priv = dev_get_priv(bus);
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
priv->cs = slave_plat->cs;
priv->freq = slave_plat->max_hz;
{
struct udevice *bus = dev->parent;
struct omap3_spi_priv *priv = dev_get_priv(bus);
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
priv->cs = slave_plat->cs;
priv->wordlen = wordlen;
const void *tx_buf, void *rx_buf,
unsigned long flags)
{
- struct dm_spi_slave_platdata *slave_plat;
+ struct dm_spi_slave_plat *slave_plat;
struct udevice *bus = slave->parent;
struct pic32_spi_priv *priv;
int len = bitlen / 8;
DECLARE_GLOBAL_DATA_PTR;
-struct rpc_spi_platdata {
+struct rpc_spi_plat {
fdt_addr_t regs;
fdt_addr_t extr;
s32 freq; /* Default clock freq, -1 for none */
static int rpc_spi_probe(struct udevice *dev)
{
- struct rpc_spi_platdata *plat = dev_get_plat(dev);
+ struct rpc_spi_plat *plat = dev_get_plat(dev);
struct rpc_spi_priv *priv = dev_get_priv(dev);
priv->regs = plat->regs;
static int rpc_spi_of_to_plat(struct udevice *bus)
{
- struct rpc_spi_platdata *plat = dev_get_plat(bus);
+ struct rpc_spi_plat *plat = dev_get_plat(bus);
plat->regs = dev_read_addr_index(bus, 0);
plat->extr = dev_read_addr_index(bus, 1);
.of_match = rpc_spi_ids,
.ops = &rpc_spi_ops,
.of_to_plat = rpc_spi_of_to_plat,
- .plat_auto = sizeof(struct rpc_spi_platdata),
+ .plat_auto = sizeof(struct rpc_spi_plat),
.priv_auto = sizeof(struct rpc_spi_priv),
.bind = rpc_spi_bind,
.probe = rpc_spi_probe,
bool master_manages_fifo;
};
-struct rockchip_spi_platdata {
+struct rockchip_spi_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_rockchip_rk3288_spi of_plat;
#endif
static void spi_cs_activate(struct udevice *dev, uint cs)
{
struct udevice *bus = dev->parent;
- struct rockchip_spi_platdata *plat = bus->plat;
+ struct rockchip_spi_plat *plat = bus->plat;
struct rockchip_spi_priv *priv = dev_get_priv(bus);
struct rockchip_spi *regs = priv->regs;
static void spi_cs_deactivate(struct udevice *dev, uint cs)
{
struct udevice *bus = dev->parent;
- struct rockchip_spi_platdata *plat = bus->plat;
+ struct rockchip_spi_plat *plat = bus->plat;
struct rockchip_spi_priv *priv = dev_get_priv(bus);
struct rockchip_spi *regs = priv->regs;
}
#if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int conv_of_platdata(struct udevice *dev)
+static int conv_of_plat(struct udevice *dev)
{
- struct rockchip_spi_platdata *plat = dev->plat;
+ struct rockchip_spi_plat *plat = dev->plat;
struct dtd_rockchip_rk3288_spi *dtplat = &plat->of_plat;
struct rockchip_spi_priv *priv = dev_get_priv(dev);
int ret;
static int rockchip_spi_of_to_plat(struct udevice *bus)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- struct rockchip_spi_platdata *plat = dev_get_plat(bus);
+ struct rockchip_spi_plat *plat = dev_get_plat(bus);
struct rockchip_spi_priv *priv = dev_get_priv(bus);
int ret;
static int rockchip_spi_probe(struct udevice *bus)
{
- struct rockchip_spi_platdata *plat = dev_get_plat(bus);
+ struct rockchip_spi_plat *plat = dev_get_plat(bus);
struct rockchip_spi_priv *priv = dev_get_priv(bus);
int ret;
debug("%s: probe\n", __func__);
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- ret = conv_of_platdata(bus);
+ ret = conv_of_plat(bus);
if (ret)
return ret;
#endif
struct udevice *bus = dev->parent;
struct rockchip_spi_priv *priv = dev_get_priv(bus);
struct rockchip_spi *regs = priv->regs;
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
int len = bitlen >> 3;
const u8 *out = dout;
u8 *in = din;
.of_match = rockchip_spi_ids,
.ops = &rockchip_spi_ops,
.of_to_plat = rockchip_spi_of_to_plat,
- .plat_auto = sizeof(struct rockchip_spi_platdata),
+ .plat_auto = sizeof(struct rockchip_spi_plat),
.priv_auto = sizeof(struct rockchip_spi_priv),
.probe = rockchip_spi_probe,
};
DECLARE_GLOBAL_DATA_PTR;
-struct soft_spi_platdata {
+struct soft_spi_plat {
struct gpio_desc cs;
struct gpio_desc sclk;
struct gpio_desc mosi;
static int soft_spi_scl(struct udevice *dev, int bit)
{
struct udevice *bus = dev_get_parent(dev);
- struct soft_spi_platdata *plat = dev_get_plat(bus);
+ struct soft_spi_plat *plat = dev_get_plat(bus);
dm_gpio_set_value(&plat->sclk, bit);
static int soft_spi_sda(struct udevice *dev, int bit)
{
struct udevice *bus = dev_get_parent(dev);
- struct soft_spi_platdata *plat = dev_get_plat(bus);
+ struct soft_spi_plat *plat = dev_get_plat(bus);
dm_gpio_set_value(&plat->mosi, bit);
{
struct udevice *bus = dev_get_parent(dev);
struct soft_spi_priv *priv = dev_get_priv(bus);
- struct soft_spi_platdata *plat = dev_get_plat(bus);
+ struct soft_spi_plat *plat = dev_get_plat(bus);
int cidle = !!(priv->mode & SPI_CPOL);
dm_gpio_set_value(&plat->cs, 0);
static int soft_spi_cs_deactivate(struct udevice *dev)
{
struct udevice *bus = dev_get_parent(dev);
- struct soft_spi_platdata *plat = dev_get_plat(bus);
+ struct soft_spi_plat *plat = dev_get_plat(bus);
dm_gpio_set_value(&plat->cs, 0);
{
struct udevice *bus = dev_get_parent(dev);
struct soft_spi_priv *priv = dev_get_priv(bus);
- struct soft_spi_platdata *plat = dev_get_plat(bus);
+ struct soft_spi_plat *plat = dev_get_plat(bus);
uchar tmpdin = 0;
uchar tmpdout = 0;
const u8 *txd = dout;
static int soft_spi_of_to_plat(struct udevice *dev)
{
- struct soft_spi_platdata *plat = dev->plat;
+ struct soft_spi_plat *plat = dev->plat;
const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
static int soft_spi_probe(struct udevice *dev)
{
struct spi_slave *slave = dev_get_parent_priv(dev);
- struct soft_spi_platdata *plat = dev->plat;
+ struct soft_spi_plat *plat = dev->plat;
int cs_flags, clk_flags;
int ret;
.of_match = soft_spi_ids,
.ops = &soft_spi_ops,
.of_to_plat = soft_spi_of_to_plat,
- .plat_auto = sizeof(struct soft_spi_platdata),
+ .plat_auto = sizeof(struct soft_spi_plat),
.priv_auto = sizeof(struct soft_spi_priv),
.probe = soft_spi_probe,
};
const void *dout, void *din, unsigned long flags)
{
struct udevice *bus = dev_get_parent(dev);
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
unsigned int len;
const u8 *txp = dout;
u8 *rxp = din;
};
static void sifive_spi_prep_device(struct sifive_spi *spi,
- struct dm_spi_slave_platdata *slave_plat)
+ struct dm_spi_slave_plat *slave_plat)
{
/* Update the chip select polarity */
if (slave_plat->mode & SPI_CS_HIGH)
}
static int sifive_spi_set_cs(struct sifive_spi *spi,
- struct dm_spi_slave_platdata *slave_plat)
+ struct dm_spi_slave_plat *slave_plat)
{
u32 cs_mode = SIFIVE_SPI_CSMODE_MODE_HOLD;
}
static void sifive_spi_prep_transfer(struct sifive_spi *spi,
- struct dm_spi_slave_platdata *slave_plat,
+ struct dm_spi_slave_plat *slave_plat,
u8 *rx_ptr)
{
u32 cr;
{
struct udevice *bus = dev->parent;
struct sifive_spi *spi = dev_get_priv(bus);
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
const u8 *tx_ptr = dout;
u8 *rx_ptr = din;
u32 remaining_len;
bool has_burst_ctl;
};
-struct sun4i_spi_platdata {
+struct sun4i_spi_plat {
struct sun4i_spi_variant *variant;
u32 base;
u32 max_hz;
{
struct udevice *bus = dev->parent;
struct sun4i_spi_priv *priv = dev_get_priv(bus);
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
u32 len = bitlen / 8;
u32 rx_fifocnt;
static int sun4i_spi_set_speed(struct udevice *dev, uint speed)
{
- struct sun4i_spi_platdata *plat = dev_get_plat(dev);
+ struct sun4i_spi_plat *plat = dev_get_plat(dev);
struct sun4i_spi_priv *priv = dev_get_priv(dev);
unsigned int div;
u32 reg;
static int sun4i_spi_probe(struct udevice *bus)
{
- struct sun4i_spi_platdata *plat = dev_get_plat(bus);
+ struct sun4i_spi_plat *plat = dev_get_plat(bus);
struct sun4i_spi_priv *priv = dev_get_priv(bus);
int ret;
static int sun4i_spi_of_to_plat(struct udevice *bus)
{
- struct sun4i_spi_platdata *plat = dev_get_plat(bus);
+ struct sun4i_spi_plat *plat = dev_get_plat(bus);
int node = dev_of_offset(bus);
plat->base = dev_read_addr(bus);
.of_match = sun4i_spi_ids,
.ops = &sun4i_spi_ops,
.of_to_plat = sun4i_spi_of_to_plat,
- .plat_auto = sizeof(struct sun4i_spi_platdata),
+ .plat_auto = sizeof(struct sun4i_spi_plat),
.priv_auto = sizeof(struct sun4i_spi_priv),
.probe = sun4i_spi_probe,
};
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
static int spi_child_post_bind(struct udevice *dev)
{
- struct dm_spi_slave_platdata *plat = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);
if (!dev_of_valid(dev))
return 0;
static int spi_child_pre_probe(struct udevice *dev)
{
- struct dm_spi_slave_platdata *plat = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);
struct spi_slave *slave = dev_get_parent_priv(dev);
/*
int spi_chip_select(struct udevice *dev)
{
- struct dm_spi_slave_platdata *plat = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);
return plat ? plat->cs : -ENOENT;
}
for (device_find_first_child(bus, &dev); dev;
device_find_next_child(&dev)) {
- struct dm_spi_slave_platdata *plat;
+ struct dm_spi_slave_plat *plat;
plat = dev_get_parent_plat(dev);
debug("%s: plat=%p, cs=%d\n", __func__, plat, plat->cs);
struct udevice **busp, struct spi_slave **devp)
{
struct udevice *bus, *dev;
- struct dm_spi_slave_platdata *plat;
+ struct dm_spi_slave_plat *plat;
struct spi_slave *slave;
bool created = false;
int ret;
slave->dev = NULL;
}
-int spi_slave_of_to_plat(struct udevice *dev,
- struct dm_spi_slave_platdata *plat)
+int spi_slave_of_to_plat(struct udevice *dev, struct dm_spi_slave_plat *plat)
{
int mode = 0;
int value;
.child_pre_probe = spi_child_pre_probe,
.per_device_auto = sizeof(struct dm_spi_bus),
.per_child_auto = sizeof(struct spi_slave),
- .per_child_plat_auto = sizeof(struct dm_spi_slave_platdata),
+ .per_child_plat_auto = sizeof(struct dm_spi_slave_plat),
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
.child_post_bind = spi_child_post_bind,
#endif
static int stm32_qspi_claim_bus(struct udevice *dev)
{
struct stm32_qspi_priv *priv = dev_get_priv(dev->parent);
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
int slave_cs = slave_plat->cs;
if (slave_cs >= STM32_QSPI_MAX_CHIP)
const void *dout, void *din, unsigned long flags)
{
struct udevice *bus = dev_get_parent(slave);
- struct dm_spi_slave_platdata *slave_plat;
+ struct dm_spi_slave_plat *slave_plat;
struct stm32_spi_priv *priv = dev_get_priv(bus);
u32 sr;
u32 ifcr = 0;
static int tegra114_spi_of_to_plat(struct udevice *bus)
{
- struct tegra_spi_platdata *plat = bus->plat;
+ struct tegra_spi_plat *plat = bus->plat;
plat->base = dev_read_addr(bus);
plat->periph_id = clock_decode_periph_id(bus);
static int tegra114_spi_probe(struct udevice *bus)
{
- struct tegra_spi_platdata *plat = dev_get_plat(bus);
+ struct tegra_spi_plat *plat = dev_get_plat(bus);
struct tegra114_spi_priv *priv = dev_get_priv(bus);
struct spi_regs *regs;
ulong rate;
static void spi_cs_activate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct tegra_spi_platdata *pdata = dev_get_plat(bus);
+ struct tegra_spi_plat *pdata = dev_get_plat(bus);
struct tegra114_spi_priv *priv = dev_get_priv(bus);
/* If it's too soon to do another transaction, wait */
static void spi_cs_deactivate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct tegra_spi_platdata *pdata = dev_get_plat(bus);
+ struct tegra_spi_plat *pdata = dev_get_plat(bus);
struct tegra114_spi_priv *priv = dev_get_priv(bus);
setbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL);
static int tegra114_spi_set_speed(struct udevice *bus, uint speed)
{
- struct tegra_spi_platdata *plat = bus->plat;
+ struct tegra_spi_plat *plat = bus->plat;
struct tegra114_spi_priv *priv = dev_get_priv(bus);
if (speed > plat->frequency)
.of_match = tegra114_spi_ids,
.ops = &tegra114_spi_ops,
.of_to_plat = tegra114_spi_of_to_plat,
- .plat_auto = sizeof(struct tegra_spi_platdata),
+ .plat_auto = sizeof(struct tegra_spi_plat),
.priv_auto = sizeof(struct tegra114_spi_priv),
.probe = tegra114_spi_probe,
};
static int tegra20_sflash_of_to_plat(struct udevice *bus)
{
- struct tegra_spi_platdata *plat = bus->plat;
+ struct tegra_spi_plat *plat = bus->plat;
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
static int tegra20_sflash_probe(struct udevice *bus)
{
- struct tegra_spi_platdata *plat = dev_get_plat(bus);
+ struct tegra_spi_plat *plat = dev_get_plat(bus);
struct tegra20_sflash_priv *priv = dev_get_priv(bus);
priv->regs = (struct spi_regs *)plat->base;
static void spi_cs_activate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct tegra_spi_platdata *pdata = dev_get_plat(bus);
+ struct tegra_spi_plat *pdata = dev_get_plat(bus);
struct tegra20_sflash_priv *priv = dev_get_priv(bus);
/* If it's too soon to do another transaction, wait */
static void spi_cs_deactivate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct tegra_spi_platdata *pdata = dev_get_plat(bus);
+ struct tegra_spi_plat *pdata = dev_get_plat(bus);
struct tegra20_sflash_priv *priv = dev_get_priv(bus);
/* CS is negated on Tegra, so drive a 0 to get a 1 */
static int tegra20_sflash_set_speed(struct udevice *bus, uint speed)
{
- struct tegra_spi_platdata *plat = bus->plat;
+ struct tegra_spi_plat *plat = bus->plat;
struct tegra20_sflash_priv *priv = dev_get_priv(bus);
if (speed > plat->frequency)
.of_match = tegra20_sflash_ids,
.ops = &tegra20_sflash_ops,
.of_to_plat = tegra20_sflash_of_to_plat,
- .plat_auto = sizeof(struct tegra_spi_platdata),
+ .plat_auto = sizeof(struct tegra_spi_plat),
.priv_auto = sizeof(struct tegra20_sflash_priv),
.probe = tegra20_sflash_probe,
};
static int tegra30_spi_of_to_plat(struct udevice *bus)
{
- struct tegra_spi_platdata *plat = bus->plat;
+ struct tegra_spi_plat *plat = bus->plat;
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
static int tegra30_spi_probe(struct udevice *bus)
{
- struct tegra_spi_platdata *plat = dev_get_plat(bus);
+ struct tegra_spi_plat *plat = dev_get_plat(bus);
struct tegra30_spi_priv *priv = dev_get_priv(bus);
priv->regs = (struct spi_regs *)plat->base;
static void spi_cs_activate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct tegra_spi_platdata *pdata = dev_get_plat(bus);
+ struct tegra_spi_plat *pdata = dev_get_plat(bus);
struct tegra30_spi_priv *priv = dev_get_priv(bus);
/* If it's too soon to do another transaction, wait */
static void spi_cs_deactivate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct tegra_spi_platdata *pdata = dev_get_plat(bus);
+ struct tegra_spi_plat *pdata = dev_get_plat(bus);
struct tegra30_spi_priv *priv = dev_get_priv(bus);
/* CS is negated on Tegra, so drive a 0 to get a 1 */
static int tegra30_spi_set_speed(struct udevice *bus, uint speed)
{
- struct tegra_spi_platdata *plat = bus->plat;
+ struct tegra_spi_plat *plat = bus->plat;
struct tegra30_spi_priv *priv = dev_get_priv(bus);
if (speed > plat->frequency)
.of_match = tegra30_spi_ids,
.ops = &tegra30_spi_ops,
.of_to_plat = tegra30_spi_of_to_plat,
- .plat_auto = sizeof(struct tegra_spi_platdata),
+ .plat_auto = sizeof(struct tegra_spi_plat),
.priv_auto = sizeof(struct tegra30_spi_priv),
.probe = tegra30_spi_probe,
};
static int tegra210_qspi_of_to_plat(struct udevice *bus)
{
- struct tegra_spi_platdata *plat = bus->plat;
+ struct tegra_spi_plat *plat = bus->plat;
plat->base = dev_read_addr(bus);
plat->periph_id = clock_decode_periph_id(bus);
static int tegra210_qspi_probe(struct udevice *bus)
{
- struct tegra_spi_platdata *plat = dev_get_plat(bus);
+ struct tegra_spi_plat *plat = dev_get_plat(bus);
struct tegra210_qspi_priv *priv = dev_get_priv(bus);
priv->regs = (struct qspi_regs *)plat->base;
static void spi_cs_activate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct tegra_spi_platdata *pdata = dev_get_plat(bus);
+ struct tegra_spi_plat *pdata = dev_get_plat(bus);
struct tegra210_qspi_priv *priv = dev_get_priv(bus);
/* If it's too soon to do another transaction, wait */
static void spi_cs_deactivate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct tegra_spi_platdata *pdata = dev_get_plat(bus);
+ struct tegra_spi_plat *pdata = dev_get_plat(bus);
struct tegra210_qspi_priv *priv = dev_get_priv(bus);
setbits_le32(&priv->regs->command1, QSPI_CMD1_CS_SW_VAL);
static int tegra210_qspi_set_speed(struct udevice *bus, uint speed)
{
- struct tegra_spi_platdata *plat = bus->plat;
+ struct tegra_spi_plat *plat = bus->plat;
struct tegra210_qspi_priv *priv = dev_get_priv(bus);
if (speed > plat->frequency)
.of_match = tegra210_qspi_ids,
.ops = &tegra210_qspi_ops,
.of_to_plat = tegra210_qspi_of_to_plat,
- .plat_auto = sizeof(struct tegra_spi_platdata),
+ .plat_auto = sizeof(struct tegra_spi_plat),
.priv_auto = sizeof(struct tegra210_qspi_priv),
.per_child_auto = sizeof(struct spi_slave),
.probe = tegra210_qspi_probe,
* (C) Copyright 2014 Google, Inc
*/
-struct tegra_spi_platdata {
+struct tegra_spi_plat {
enum periph_id periph_id;
int frequency; /* Default clock frequency, -1 for none */
ulong base;
static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
{
- struct dm_spi_slave_platdata *slave = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *slave = dev_get_parent_plat(dev);
struct ti_qspi_priv *priv;
struct udevice *bus;
uint words = bitlen >> 3; /* fixed 8-bit word length */
static int ti_qspi_exec_mem_op(struct spi_slave *slave,
const struct spi_mem_op *op)
{
- struct dm_spi_slave_platdata *slave_plat;
+ struct dm_spi_slave_plat *slave_plat;
struct ti_qspi_priv *priv;
struct udevice *bus;
u32 from = 0;
static int ti_qspi_claim_bus(struct udevice *dev)
{
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
struct ti_qspi_priv *priv;
struct udevice *bus;
static int ti_qspi_release_bus(struct udevice *dev)
{
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
struct ti_qspi_priv *priv;
struct udevice *bus;
#define SSI_CLK 50000000 /* internal I/O clock: 50MHz */
-struct uniphier_spi_platdata {
+struct uniphier_spi_plat {
void __iomem *base;
u32 frequency; /* input frequency */
u32 speed_hz;
static void spi_cs_activate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct uniphier_spi_platdata *plat = bus->plat;
+ struct uniphier_spi_plat *plat = bus->plat;
struct uniphier_spi_priv *priv = dev_get_priv(bus);
ulong delay_us; /* The delay completed so far */
u32 val;
static void spi_cs_deactivate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct uniphier_spi_platdata *plat = bus->plat;
+ struct uniphier_spi_plat *plat = bus->plat;
struct uniphier_spi_priv *priv = dev_get_priv(bus);
u32 val;
static int uniphier_spi_set_speed(struct udevice *bus, uint speed)
{
- struct uniphier_spi_platdata *plat = bus->plat;
+ struct uniphier_spi_plat *plat = bus->plat;
struct uniphier_spi_priv *priv = dev_get_priv(bus);
u32 val, ckdiv;
static int uniphier_spi_of_to_plat(struct udevice *bus)
{
- struct uniphier_spi_platdata *plat = bus->plat;
+ struct uniphier_spi_plat *plat = bus->plat;
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
static int uniphier_spi_probe(struct udevice *bus)
{
- struct uniphier_spi_platdata *plat = dev_get_plat(bus);
+ struct uniphier_spi_plat *plat = dev_get_plat(bus);
struct uniphier_spi_priv *priv = dev_get_priv(bus);
priv->base = plat->base;
.of_match = uniphier_spi_ids,
.ops = &uniphier_spi_ops,
.of_to_plat = uniphier_spi_of_to_plat,
- .plat_auto = sizeof(struct uniphier_spi_platdata),
+ .plat_auto = sizeof(struct uniphier_spi_plat),
.priv_auto = sizeof(struct uniphier_spi_priv),
.probe = uniphier_spi_probe,
};
struct udevice *bus = dev_get_parent(dev);
struct xilinx_spi_priv *priv = dev_get_priv(bus);
struct xilinx_spi_regs *regs = priv->regs;
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
const unsigned char *txp = dout;
unsigned char *rxp = din;
u32 reg;
struct udevice *bus = dev_get_parent(dev);
struct xilinx_spi_priv *priv = dev_get_priv(bus);
struct xilinx_spi_regs *regs = priv->regs;
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
/* assume spi core configured to do 8 bit transfers */
unsigned int bytes = bitlen / XILSPI_MAX_XFER_BITS;
const unsigned char *txp = dout;
};
/* zynq qspi platform data */
-struct zynq_qspi_platdata {
+struct zynq_qspi_plat {
struct zynq_qspi_regs *regs;
u32 frequency; /* input frequency */
u32 speed_hz;
static int zynq_qspi_of_to_plat(struct udevice *bus)
{
- struct zynq_qspi_platdata *plat = bus->plat;
+ struct zynq_qspi_plat *plat = bus->plat;
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
static int zynq_qspi_probe(struct udevice *bus)
{
- struct zynq_qspi_platdata *plat = dev_get_plat(bus);
+ struct zynq_qspi_plat *plat = dev_get_plat(bus);
struct zynq_qspi_priv *priv = dev_get_priv(bus);
struct clk clk;
unsigned long clock;
{
struct udevice *bus = dev->parent;
struct zynq_qspi_priv *priv = dev_get_priv(bus);
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
priv->cs = slave_plat->cs;
priv->tx_buf = dout;
static int zynq_qspi_set_speed(struct udevice *bus, uint speed)
{
- struct zynq_qspi_platdata *plat = bus->plat;
+ struct zynq_qspi_plat *plat = bus->plat;
struct zynq_qspi_priv *priv = dev_get_priv(bus);
struct zynq_qspi_regs *regs = priv->regs;
uint32_t confr;
.of_match = zynq_qspi_ids,
.ops = &zynq_qspi_ops,
.of_to_plat = zynq_qspi_of_to_plat,
- .plat_auto = sizeof(struct zynq_qspi_platdata),
+ .plat_auto = sizeof(struct zynq_qspi_plat),
.priv_auto = sizeof(struct zynq_qspi_priv),
.probe = zynq_qspi_probe,
};
/* zynq spi platform data */
-struct zynq_spi_platdata {
+struct zynq_spi_plat {
struct zynq_spi_regs *regs;
u32 frequency; /* input frequency */
u32 speed_hz;
static int zynq_spi_of_to_plat(struct udevice *bus)
{
- struct zynq_spi_platdata *plat = bus->plat;
+ struct zynq_spi_plat *plat = bus->plat;
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
static int zynq_spi_probe(struct udevice *bus)
{
- struct zynq_spi_platdata *plat = dev_get_plat(bus);
+ struct zynq_spi_plat *plat = dev_get_plat(bus);
struct zynq_spi_priv *priv = dev_get_priv(bus);
struct clk clk;
unsigned long clock;
static void spi_cs_activate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct zynq_spi_platdata *plat = bus->plat;
+ struct zynq_spi_plat *plat = bus->plat;
struct zynq_spi_priv *priv = dev_get_priv(bus);
struct zynq_spi_regs *regs = priv->regs;
u32 cr;
static void spi_cs_deactivate(struct udevice *dev)
{
struct udevice *bus = dev->parent;
- struct zynq_spi_platdata *plat = bus->plat;
+ struct zynq_spi_plat *plat = bus->plat;
struct zynq_spi_priv *priv = dev_get_priv(bus);
struct zynq_spi_regs *regs = priv->regs;
struct udevice *bus = dev->parent;
struct zynq_spi_priv *priv = dev_get_priv(bus);
struct zynq_spi_regs *regs = priv->regs;
- struct dm_spi_slave_platdata *slave_plat = dev_get_parent_plat(dev);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
u32 len = bitlen / 8;
u32 tx_len = len, rx_len = len, tx_tvl;
const u8 *tx_buf = dout;
static int zynq_spi_set_speed(struct udevice *bus, uint speed)
{
- struct zynq_spi_platdata *plat = bus->plat;
+ struct zynq_spi_plat *plat = bus->plat;
struct zynq_spi_priv *priv = dev_get_priv(bus);
struct zynq_spi_regs *regs = priv->regs;
uint32_t confr;
.of_match = zynq_spi_ids,
.ops = &zynq_spi_ops,
.of_to_plat = zynq_spi_of_to_plat,
- .plat_auto = sizeof(struct zynq_spi_platdata),
+ .plat_auto = sizeof(struct zynq_spi_plat),
.priv_auto = sizeof(struct zynq_spi_priv),
.probe = zynq_spi_probe,
};
DECLARE_GLOBAL_DATA_PTR;
-struct zynqmp_qspi_platdata {
+struct zynqmp_qspi_plat {
struct zynqmp_qspi_regs *regs;
struct zynqmp_qspi_dma_regs *dma_regs;
u32 frequency;
static int zynqmp_qspi_of_to_plat(struct udevice *bus)
{
- struct zynqmp_qspi_platdata *plat = bus->plat;
+ struct zynqmp_qspi_plat *plat = bus->plat;
debug("%s\n", __func__);
void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval)
{
- struct zynqmp_qspi_platdata *plat = bus->plat;
+ struct zynqmp_qspi_plat *plat = bus->plat;
struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
struct zynqmp_qspi_regs *regs = priv->regs;
u32 tapdlybypass = 0, lpbkdlyadj = 0, datadlyadj = 0, clk_rate;
static int zynqmp_qspi_set_speed(struct udevice *bus, uint speed)
{
- struct zynqmp_qspi_platdata *plat = bus->plat;
+ struct zynqmp_qspi_plat *plat = bus->plat;
struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
struct zynqmp_qspi_regs *regs = priv->regs;
u32 confr;
static int zynqmp_qspi_probe(struct udevice *bus)
{
- struct zynqmp_qspi_platdata *plat = dev_get_plat(bus);
+ struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
struct clk clk;
unsigned long clock;
.of_match = zynqmp_qspi_ids,
.ops = &zynqmp_qspi_ops,
.of_to_plat = zynqmp_qspi_of_to_plat,
- .plat_auto = sizeof(struct zynqmp_qspi_platdata),
+ .plat_auto = sizeof(struct zynqmp_qspi_plat),
.priv_auto = sizeof(struct zynqmp_qspi_priv),
.probe = zynqmp_qspi_probe,
};
#include <asm/io.h>
#include <asm/processor.h>
-struct x86_sysreset_platdata {
+struct x86_sysreset_plat {
struct udevice *pch;
};
*/
int pch_sysreset_power_off(struct udevice *dev)
{
- struct x86_sysreset_platdata *plat = dev_get_plat(dev);
+ struct x86_sysreset_plat *plat = dev_get_plat(dev);
struct pch_pmbase_info pm;
u32 reg32;
int ret;
static int x86_sysreset_probe(struct udevice *dev)
{
- struct x86_sysreset_platdata *plat = dev_get_plat(dev);
+ struct x86_sysreset_plat *plat = dev_get_plat(dev);
/* Locate the PCH if there is one. It isn't essential */
uclass_first_device(UCLASS_PCH, &plat->pch);
.of_match = x86_sysreset_ids,
.ops = &x86_sysreset_ops,
.probe = x86_sysreset_probe,
- .plat_auto = sizeof(struct x86_sysreset_platdata),
+ .plat_auto = sizeof(struct x86_sysreset_plat),
};
u32 int_mask; /* 0x38 */
};
-struct atftmr_timer_platdata {
+struct atftmr_timer_plat {
struct atftmr_timer_regs *regs;
};
static u64 atftmr_timer_get_count(struct udevice *dev)
{
- struct atftmr_timer_platdata *plat = dev->plat;
+ struct atftmr_timer_plat *plat = dev->plat;
struct atftmr_timer_regs *const regs = plat->regs;
u32 val;
val = readl(®s->t3_counter);
static int atftmr_timer_probe(struct udevice *dev)
{
- struct atftmr_timer_platdata *plat = dev->plat;
+ struct atftmr_timer_plat *plat = dev->plat;
struct atftmr_timer_regs *const regs = plat->regs;
u32 cr;
writel(0, ®s->t3_load);
static int atftme_timer_of_to_plat(struct udevice *dev)
{
- struct atftmr_timer_platdata *plat = dev_get_plat(dev);
+ struct atftmr_timer_plat *plat = dev_get_plat(dev);
plat->regs = map_physmem(dev_read_addr(dev),
sizeof(struct atftmr_timer_regs),
MAP_NOCACHE);
.id = UCLASS_TIMER,
.of_match = ag101p_timer_ids,
.of_to_plat = atftme_timer_of_to_plat,
- .plat_auto = sizeof(struct atftmr_timer_platdata),
+ .plat_auto = sizeof(struct atftmr_timer_plat),
.probe = atftmr_timer_probe,
.ops = &ag101p_timer_ops,
};
u32 snaph; /* Snapshot high */
};
-struct altera_timer_platdata {
+struct altera_timer_plat {
struct altera_timer_regs *regs;
};
static u64 altera_timer_get_count(struct udevice *dev)
{
- struct altera_timer_platdata *plat = dev->plat;
+ struct altera_timer_plat *plat = dev->plat;
struct altera_timer_regs *const regs = plat->regs;
u32 val;
static int altera_timer_probe(struct udevice *dev)
{
- struct altera_timer_platdata *plat = dev->plat;
+ struct altera_timer_plat *plat = dev->plat;
struct altera_timer_regs *const regs = plat->regs;
writel(0, ®s->status);
static int altera_timer_of_to_plat(struct udevice *dev)
{
- struct altera_timer_platdata *plat = dev_get_plat(dev);
+ struct altera_timer_plat *plat = dev_get_plat(dev);
plat->regs = map_physmem(dev_read_addr(dev),
sizeof(struct altera_timer_regs),
.id = UCLASS_TIMER,
.of_match = altera_timer_ids,
.of_to_plat = altera_timer_of_to_plat,
- .plat_auto = sizeof(struct altera_timer_platdata),
+ .plat_auto = sizeof(struct altera_timer_plat),
.probe = altera_timer_probe,
.ops = &altera_timer_ops,
};
u32 int_mask; /* 0x38 */
};
-struct atcpit_timer_platdata {
+struct atcpit_timer_plat {
u32 *regs;
};
static u64 atcpit_timer_get_count(struct udevice *dev)
{
- struct atcpit_timer_platdata *plat = dev_get_plat(dev);
+ struct atcpit_timer_plat *plat = dev_get_plat(dev);
u32 val;
val = ~(REG32_TMR(CH_CNT(1))+0xffffffff);
return timer_conv_64(val);
static int atcpit_timer_probe(struct udevice *dev)
{
- struct atcpit_timer_platdata *plat = dev_get_plat(dev);
+ struct atcpit_timer_plat *plat = dev_get_plat(dev);
REG32_TMR(CH_REL(1)) = 0xffffffff;
REG32_TMR(CH_CTL(1)) = APB_CLK|TMR_32;
REG32_TMR(CH_EN) |= CH_TMR_EN(1 , 0);
static int atcpit_timer_of_to_plat(struct udevice *dev)
{
- struct atcpit_timer_platdata *plat = dev_get_plat(dev);
+ struct atcpit_timer_plat *plat = dev_get_plat(dev);
plat->regs = map_physmem(dev_read_addr(dev), 0x100 , MAP_NOCACHE);
return 0;
}
.id = UCLASS_TIMER,
.of_match = atcpit_timer_ids,
.of_to_plat = atcpit_timer_of_to_plat,
- .plat_auto = sizeof(struct atcpit_timer_platdata),
+ .plat_auto = sizeof(struct atcpit_timer_plat),
.probe = atcpit_timer_probe,
.ops = &atcpit_timer_ops,
};
u32 value_image;
};
-struct atmel_pit_platdata {
+struct atmel_pit_plat {
struct atmel_pit_regs *regs;
};
static u64 atmel_pit_get_count(struct udevice *dev)
{
- struct atmel_pit_platdata *plat = dev_get_plat(dev);
+ struct atmel_pit_plat *plat = dev_get_plat(dev);
struct atmel_pit_regs *const regs = plat->regs;
u32 val = readl(®s->value_image);
static int atmel_pit_probe(struct udevice *dev)
{
- struct atmel_pit_platdata *plat = dev_get_plat(dev);
+ struct atmel_pit_plat *plat = dev_get_plat(dev);
struct atmel_pit_regs *const regs = plat->regs;
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct clk clk;
static int atmel_pit_of_to_plat(struct udevice *dev)
{
- struct atmel_pit_platdata *plat = dev_get_plat(dev);
+ struct atmel_pit_plat *plat = dev_get_plat(dev);
plat->regs = dev_read_addr_ptr(dev);
.id = UCLASS_TIMER,
.of_match = atmel_pit_ids,
.of_to_plat = atmel_pit_of_to_plat,
- .plat_auto = sizeof(struct atmel_pit_platdata),
+ .plat_auto = sizeof(struct atmel_pit_plat),
.probe = atmel_pit_probe,
.ops = &atmel_pit_ops,
};
int timer_timebase_fallback(struct udevice *dev)
{
struct udevice *cpu;
- struct cpu_platdata *cpu_plat;
+ struct cpu_plat *cpu_plat;
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
/* Did we get our clock rate from the device tree? */
int ufshcd_probe(struct udevice *ufs_dev, struct ufs_hba_ops *hba_ops)
{
struct ufs_hba *hba = dev_get_uclass_priv(ufs_dev);
- struct scsi_platdata *scsi_plat;
+ struct scsi_plat *scsi_plat;
struct udevice *scsi_dev;
int err;
/* We only support up to 8 */
#define SANDBOX_NUM_PORTS 4
-struct sandbox_hub_platdata {
- struct usb_dev_platdata plat;
+struct sandbox_hub_plat {
+ struct usb_dev_plat plat;
int port; /* Port number (numbered from 0) */
};
for (device_find_first_child(hub, &dev);
dev;
device_find_next_child(&dev)) {
- struct sandbox_hub_platdata *plat;
+ struct sandbox_hub_plat *plat;
plat = dev_get_parent_plat(dev);
if (plat->port == port) {
static int sandbox_child_post_bind(struct udevice *dev)
{
- struct sandbox_hub_platdata *plat = dev_get_parent_plat(dev);
- struct usb_emul_platdata *emul = dev_get_uclass_plat(dev);
+ struct sandbox_hub_plat *plat = dev_get_parent_plat(dev);
+ struct usb_emul_plat *emul = dev_get_uclass_plat(dev);
plat->port = dev_read_u32_default(dev, "reg", -1);
emul->port1 = plat->port + 1;
.bind = sandbox_hub_bind,
.ops = &sandbox_usb_hub_ops,
.priv_auto = sizeof(struct sandbox_hub_priv),
- .per_child_plat_auto = sizeof(struct sandbox_hub_platdata),
+ .per_child_plat_auto = sizeof(struct sandbox_hub_plat),
.child_post_bind = sandbox_child_post_bind,
};
return ptr;
}
-static int usb_emul_get_descriptor(struct usb_dev_platdata *plat, int value,
+static int usb_emul_get_descriptor(struct usb_dev_plat *plat, int value,
void *buffer, int length)
{
struct usb_generic_descriptor **ptr;
if (ret)
return ret;
uclass_foreach_dev(dev, uc) {
- struct usb_dev_platdata *udev = dev_get_parent_plat(dev);
+ struct usb_dev_plat *udev = dev_get_parent_plat(dev);
/*
* devnum is initialzied to zero at the beginning of the
* emulator device.
*/
if (!devnum) {
- struct usb_emul_platdata *plat;
+ struct usb_emul_plat *plat;
/*
* If the parent is sandbox USB controller, we are
int usb_emul_find_for_dev(struct udevice *dev, struct udevice **emulp)
{
- struct usb_dev_platdata *udev = dev_get_parent_plat(dev);
+ struct usb_dev_plat *udev = dev_get_parent_plat(dev);
return usb_emul_find_devnum(udev->devnum, 0, emulp);
}
struct devrequest *setup)
{
struct dm_usb_ops *ops = usb_get_emul_ops(emul);
- struct usb_dev_platdata *plat;
+ struct usb_dev_plat *plat;
int ret;
/* We permit getting the descriptor before we are probed */
int usb_emul_setup_device(struct udevice *dev, struct usb_string *strings,
void **desc_list)
{
- struct usb_dev_platdata *plat = dev_get_parent_plat(dev);
+ struct usb_dev_plat *plat = dev_get_parent_plat(dev);
struct usb_generic_descriptor **ptr;
struct usb_config_descriptor *cdesc;
int upto;
.id = UCLASS_USB_EMUL,
.name = "usb_emul",
.post_bind = dm_scan_fdt_dev,
- .per_device_plat_auto = sizeof(struct usb_emul_platdata),
+ .per_device_plat_auto = sizeof(struct usb_emul_plat),
.per_child_auto = sizeof(struct usb_device),
- .per_child_plat_auto = sizeof(struct usb_dev_platdata),
+ .per_child_plat_auto = sizeof(struct usb_dev_plat),
};
static int max3420_udc_probe(struct udevice *dev)
{
struct max3420_udc *udc = dev_get_priv(dev);
- struct dm_spi_slave_platdata *slave_pdata;
+ struct dm_spi_slave_plat *slave_pdata;
struct udevice *bus = dev->parent;
int busnum = bus->seq;
unsigned int cs;
DECLARE_GLOBAL_DATA_PTR;
/*
- * struct sti_dwc3_glue_platdata - dwc3 STi glue driver private structure
+ * struct sti_dwc3_glue_plat - dwc3 STi glue driver private structure
* @syscfg_base: addr for the glue syscfg
* @glue_base: addr for the glue registers
* @syscfg_offset: usb syscfg control offset
* @softreset_ctl: reset controller for softreset signal
* @mode: drd static host/device config
*/
-struct sti_dwc3_glue_platdata {
+struct sti_dwc3_glue_plat {
phys_addr_t syscfg_base;
phys_addr_t glue_base;
phys_addr_t syscfg_offset;
enum usb_dr_mode mode;
};
-static int sti_dwc3_glue_drd_init(struct sti_dwc3_glue_platdata *plat)
+static int sti_dwc3_glue_drd_init(struct sti_dwc3_glue_plat *plat)
{
unsigned long val;
return 0;
}
-static void sti_dwc3_glue_init(struct sti_dwc3_glue_platdata *plat)
+static void sti_dwc3_glue_init(struct sti_dwc3_glue_plat *plat)
{
unsigned long reg;
static int sti_dwc3_glue_of_to_plat(struct udevice *dev)
{
- struct sti_dwc3_glue_platdata *plat = dev_get_plat(dev);
+ struct sti_dwc3_glue_plat *plat = dev_get_plat(dev);
struct udevice *syscon;
struct regmap *regmap;
int ret;
static int sti_dwc3_glue_bind(struct udevice *dev)
{
- struct sti_dwc3_glue_platdata *plat = dev_get_plat(dev);
+ struct sti_dwc3_glue_plat *plat = dev_get_plat(dev);
ofnode node, dwc3_node;
/* Find snps,dwc3 node from subnode */
static int sti_dwc3_glue_probe(struct udevice *dev)
{
- struct sti_dwc3_glue_platdata *plat = dev_get_plat(dev);
+ struct sti_dwc3_glue_plat *plat = dev_get_plat(dev);
int ret;
/* deassert both powerdown and softreset */
static int sti_dwc3_glue_remove(struct udevice *dev)
{
- struct sti_dwc3_glue_platdata *plat = dev_get_plat(dev);
+ struct sti_dwc3_glue_plat *plat = dev_get_plat(dev);
int ret;
/* assert both powerdown and softreset */
.probe = sti_dwc3_glue_probe,
.remove = sti_dwc3_glue_remove,
.bind = sti_dwc3_glue_bind,
- .plat_auto = sizeof(struct sti_dwc3_glue_platdata),
+ .plat_auto = sizeof(struct sti_dwc3_glue_plat),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
.probe = ehci_atmel_probe,
.remove = ehci_deregister,
.ops = &ehci_usb_ops,
- .plat_auto = sizeof(struct usb_platdata),
+ .plat_auto = sizeof(struct usb_plat),
.priv_auto = sizeof(struct ehci_atmel_priv),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
/* Declare global data pointer */
DECLARE_GLOBAL_DATA_PTR;
-struct exynos_ehci_platdata {
- struct usb_platdata usb_plat;
+struct exynos_ehci_plat {
+ struct usb_plat usb_plat;
fdt_addr_t hcd_base;
fdt_addr_t phy_base;
struct gpio_desc vbus_gpio;
static int ehci_usb_of_to_plat(struct udevice *dev)
{
- struct exynos_ehci_platdata *plat = dev_get_plat(dev);
+ struct exynos_ehci_plat *plat = dev_get_plat(dev);
const void *blob = gd->fdt_blob;
unsigned int node;
int depth;
static int ehci_usb_probe(struct udevice *dev)
{
- struct exynos_ehci_platdata *plat = dev_get_plat(dev);
+ struct exynos_ehci_plat *plat = dev_get_plat(dev);
struct exynos_ehci *ctx = dev_get_priv(dev);
struct ehci_hcor *hcor;
.remove = ehci_usb_remove,
.ops = &ehci_usb_ops,
.priv_auto = sizeof(struct exynos_ehci),
- .plat_auto = sizeof(struct exynos_ehci_platdata),
+ .plat_auto = sizeof(struct exynos_ehci_plat),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
.probe = ehci_fsl_probe,
.remove = ehci_deregister,
.ops = &ehci_usb_ops,
- .plat_auto = sizeof(struct usb_platdata),
+ .plat_auto = sizeof(struct usb_plat),
.priv_auto = sizeof(struct ehci_fsl_priv),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
.probe = ehci_mvebu_probe,
.remove = ehci_deregister,
.ops = &ehci_usb_ops,
- .plat_auto = sizeof(struct usb_platdata),
+ .plat_auto = sizeof(struct usb_plat),
.priv_auto = sizeof(struct ehci_mvebu_priv),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
{
struct msm_ehci_priv *p = dev_get_priv(dev);
struct usb_ehci *ehci = p->ehci;
- struct usb_platdata *plat = dev_get_plat(dev);
+ struct usb_plat *plat = dev_get_plat(dev);
struct ehci_hccr *hccr;
struct ehci_hcor *hcor;
int ret;
.remove = ehci_usb_remove,
.ops = &ehci_usb_ops,
.priv_auto = sizeof(struct msm_ehci_priv),
- .plat_auto = sizeof(struct usb_platdata),
+ .plat_auto = sizeof(struct usb_plat),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
static int ehci_usb_of_to_plat(struct udevice *dev)
{
- struct usb_platdata *plat = dev_get_plat(dev);
+ struct usb_plat *plat = dev_get_plat(dev);
const char *mode;
mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "dr_mode", NULL);
static int ehci_usb_probe(struct udevice *dev)
{
- struct usb_platdata *plat = dev_get_plat(dev);
+ struct usb_plat *plat = dev_get_plat(dev);
struct usb_ehci *ehci = dev_read_addr_ptr(dev);
struct ehci_mx5_priv_data *priv = dev_get_priv(dev);
enum usb_init_type type = plat->init_type;
.probe = ehci_usb_probe,
.remove = ehci_deregister,
.ops = &ehci_usb_ops,
- .plat_auto = sizeof(struct usb_platdata),
+ .plat_auto = sizeof(struct usb_plat),
.priv_auto = sizeof(struct ehci_mx5_priv_data),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
static int ehci_usb_phy_mode(struct udevice *dev)
{
- struct usb_platdata *plat = dev_get_plat(dev);
+ struct usb_plat *plat = dev_get_plat(dev);
void *__iomem addr = dev_read_addr_ptr(dev);
void *__iomem phy_ctrl, *__iomem phy_status;
const void *blob = gd->fdt_blob;
static int ehci_usb_of_to_plat(struct udevice *dev)
{
- struct usb_platdata *plat = dev_get_plat(dev);
+ struct usb_plat *plat = dev_get_plat(dev);
enum usb_dr_mode dr_mode;
dr_mode = usb_get_dr_mode(dev->node);
static int ehci_usb_probe(struct udevice *dev)
{
- struct usb_platdata *plat = dev_get_plat(dev);
+ struct usb_plat *plat = dev_get_plat(dev);
struct usb_ehci *ehci = dev_read_addr_ptr(dev);
struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
enum usb_init_type type = plat->init_type;
.probe = ehci_usb_probe,
.remove = ehci_deregister,
.ops = &ehci_usb_ops,
- .plat_auto = sizeof(struct usb_platdata),
+ .plat_auto = sizeof(struct usb_plat),
.priv_auto = sizeof(struct ehci_mx6_priv_data),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
static int ehci_usb_of_to_plat(struct udevice *dev)
{
- struct usb_platdata *plat = dev_get_plat(dev);
+ struct usb_plat *plat = dev_get_plat(dev);
plat->init_type = USB_INIT_HOST;
static int omap_ehci_probe(struct udevice *dev)
{
- struct usb_platdata *plat = dev_get_plat(dev);
+ struct usb_plat *plat = dev_get_plat(dev);
struct ehci_omap_priv_data *priv = dev_get_priv(dev);
struct ehci_hccr *hccr;
struct ehci_hcor *hcor;
.of_match = omap_ehci_dt_ids,
.probe = omap_ehci_probe,
.of_to_plat = ehci_usb_of_to_plat,
- .plat_auto = sizeof(struct usb_platdata),
+ .plat_auto = sizeof(struct usb_plat),
.priv_auto = sizeof(struct ehci_omap_priv_data),
.remove = ehci_deregister,
.ops = &ehci_usb_ops,
.remove = ehci_pci_remove,
.of_match = ehci_pci_ids,
.ops = &ehci_usb_ops,
- .plat_auto = sizeof(struct usb_platdata),
+ .plat_auto = sizeof(struct usb_plat),
.priv_auto = sizeof(struct ehci_pci_priv),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
static int ehci_usb_probe(struct udevice *dev)
{
- struct usb_platdata *plat = dev_get_plat(dev);
+ struct usb_plat *plat = dev_get_plat(dev);
struct fdt_usb *priv = dev_get_priv(dev);
struct ehci_hccr *hccr;
struct ehci_hcor *hcor;
.probe = ehci_usb_probe,
.remove = ehci_deregister,
.ops = &ehci_usb_ops,
- .plat_auto = sizeof(struct usb_platdata),
+ .plat_auto = sizeof(struct usb_plat),
.priv_auto = sizeof(struct fdt_usb),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
static int ehci_usb_probe(struct udevice *dev)
{
- struct usb_platdata *plat = dev_get_plat(dev);
+ struct usb_plat *plat = dev_get_plat(dev);
struct ehci_vf_priv_data *priv = dev_get_priv(dev);
struct usb_ehci *ehci = priv->ehci;
struct ehci_hccr *hccr;
.remove = ehci_deregister,
.ops = &ehci_usb_ops,
.of_to_plat = vf_usb_of_to_plat,
- .plat_auto = sizeof(struct usb_platdata),
+ .plat_auto = sizeof(struct usb_plat),
.priv_auto = sizeof(struct ehci_vf_priv_data),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
static int ehci_zynq_probe(struct udevice *dev)
{
- struct usb_platdata *plat = dev_get_plat(dev);
+ struct usb_plat *plat = dev_get_plat(dev);
struct zynq_ehci_priv *priv = dev_get_priv(dev);
struct ehci_hccr *hccr;
struct ehci_hcor *hcor;
.probe = ehci_zynq_probe,
.remove = ehci_deregister,
.ops = &ehci_usb_ops,
- .plat_auto = sizeof(struct usb_platdata),
+ .plat_auto = sizeof(struct usb_plat),
.priv_auto = sizeof(struct zynq_ehci_priv),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
.remove = ohci_pci_remove,
.of_match = ohci_pci_ids,
.ops = &ohci_usb_ops,
- .plat_auto = sizeof(struct usb_platdata),
+ .plat_auto = sizeof(struct usb_plat),
.priv_auto = sizeof(ohci_t),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
int usb_setup_ehci_gadget(struct ehci_ctrl **ctlrp)
{
- struct usb_platdata *plat;
+ struct usb_plat *plat;
struct udevice *dev;
int ret;
const struct usb_device_id *id;
struct udevice *dev;
const struct driver *drv;
- struct usb_dev_platdata *plat;
+ struct usb_dev_plat *plat;
for (id = entry->match; id->match_flags; id++) {
if (!usb_match_one_id(desc, iface, id))
for (device_find_first_child(parent, &dev);
dev;
device_find_next_child(&dev)) {
- struct usb_dev_platdata *plat = dev_get_parent_plat(dev);
+ struct usb_dev_plat *plat = dev_get_parent_plat(dev);
/* If this device is already in use, skip it */
if (device_active(dev))
{
struct udevice *dev;
bool created = false;
- struct usb_dev_platdata *plat;
+ struct usb_dev_plat *plat;
struct usb_bus_priv *priv;
struct usb_device *parent_udev;
int ret;
static int usb_child_post_bind(struct udevice *dev)
{
- struct usb_dev_platdata *plat = dev_get_parent_plat(dev);
+ struct usb_dev_plat *plat = dev_get_parent_plat(dev);
int val;
if (!dev_of_valid(dev))
int usb_child_pre_probe(struct udevice *dev)
{
struct usb_device *udev = dev_get_parent_priv(dev);
- struct usb_dev_platdata *plat = dev_get_parent_plat(dev);
+ struct usb_dev_plat *plat = dev_get_parent_plat(dev);
int ret;
if (plat->udev) {
.per_device_auto = sizeof(struct usb_bus_priv),
.child_post_bind = usb_child_post_bind,
.child_pre_probe = usb_child_pre_probe,
- .per_child_plat_auto = sizeof(struct usb_dev_platdata),
+ .per_child_plat_auto = sizeof(struct usb_dev_plat),
};
UCLASS_DRIVER(usb_dev_generic) = {
#define USBAXI_SA_UA_MASK (USBAXI_UA_MASK | USBAXI_SA_MASK)
#define USBAXI_SA_UA_VAL (USBAXI_UA_VAL | USBAXI_SA_VAL)
-struct brcm_xhci_platdata {
+struct brcm_xhci_plat {
unsigned int arcache;
unsigned int awcache;
void __iomem *hc_base;
static int xhci_brcm_probe(struct udevice *dev)
{
- struct brcm_xhci_platdata *plat = dev_get_plat(dev);
+ struct brcm_xhci_plat *plat = dev_get_plat(dev);
struct xhci_hcor *hcor;
struct xhci_hccr *hcd;
int len, ret = 0;
static int xhci_brcm_deregister(struct udevice *dev)
{
- struct brcm_xhci_platdata *plat = dev_get_plat(dev);
+ struct brcm_xhci_plat *plat = dev_get_plat(dev);
/* Restore the default values for AXI read and write attributes */
writel(plat->awcache, plat->hc_base + DRD2U3H_XHC_REGS_AXIWRA);
.remove = xhci_brcm_deregister,
.ops = &xhci_usb_ops,
.of_match = xhci_brcm_ids,
- .plat_auto = sizeof(struct brcm_xhci_platdata),
+ .plat_auto = sizeof(struct brcm_xhci_plat),
.priv_auto = sizeof(struct xhci_ctrl),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#include <linux/usb/dwc3.h>
#include <linux/usb/otg.h>
-struct xhci_dwc3_platdata {
+struct xhci_dwc3_plat {
struct phy_bulk phys;
};
struct xhci_hccr *hccr;
struct dwc3 *dwc3_reg;
enum usb_dr_mode dr_mode;
- struct xhci_dwc3_platdata *plat = dev_get_plat(dev);
+ struct xhci_dwc3_plat *plat = dev_get_plat(dev);
const char *phy;
u32 reg;
int ret;
static int xhci_dwc3_remove(struct udevice *dev)
{
- struct xhci_dwc3_platdata *plat = dev_get_plat(dev);
+ struct xhci_dwc3_plat *plat = dev_get_plat(dev);
dwc3_shutdown_phy(dev, &plat->phys);
.remove = xhci_dwc3_remove,
.ops = &xhci_usb_ops,
.priv_auto = sizeof(struct xhci_ctrl),
- .plat_auto = sizeof(struct xhci_dwc3_platdata),
+ .plat_auto = sizeof(struct xhci_dwc3_plat),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#endif
/* Declare global data pointer */
DECLARE_GLOBAL_DATA_PTR;
-struct exynos_xhci_platdata {
+struct exynos_xhci_plat {
fdt_addr_t hcd_base;
fdt_addr_t phy_base;
struct gpio_desc vbus_gpio;
* for the usb controller.
*/
struct exynos_xhci {
- struct usb_platdata usb_plat;
+ struct usb_plat usb_plat;
struct xhci_ctrl ctrl;
struct exynos_usb3_phy *usb3_phy;
struct xhci_hccr *hcd;
static int xhci_usb_of_to_plat(struct udevice *dev)
{
- struct exynos_xhci_platdata *plat = dev_get_plat(dev);
+ struct exynos_xhci_plat *plat = dev_get_plat(dev);
const void *blob = gd->fdt_blob;
unsigned int node;
int depth;
static int xhci_usb_probe(struct udevice *dev)
{
- struct exynos_xhci_platdata *plat = dev_get_plat(dev);
+ struct exynos_xhci_plat *plat = dev_get_plat(dev);
struct exynos_xhci *ctx = dev_get_priv(dev);
struct xhci_hcor *hcor;
int ret;
.probe = xhci_usb_probe,
.remove = xhci_usb_remove,
.ops = &xhci_usb_ops,
- .plat_auto = sizeof(struct exynos_xhci_platdata),
+ .plat_auto = sizeof(struct exynos_xhci_plat),
.priv_auto = sizeof(struct exynos_xhci),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
.probe = xhci_fsl_probe,
.remove = xhci_fsl_remove,
.ops = &xhci_usb_ops,
- .plat_auto = sizeof(struct usb_platdata),
+ .plat_auto = sizeof(struct usb_plat),
.priv_auto = sizeof(struct xhci_fsl_priv),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#include <usb/xhci.h>
-struct mvebu_xhci_platdata {
+struct mvebu_xhci_plat {
fdt_addr_t hcd_base;
};
*/
struct mvebu_xhci {
struct xhci_ctrl ctrl; /* Needs to come first in this struct! */
- struct usb_platdata usb_plat;
+ struct usb_plat usb_plat;
struct xhci_hccr *hcd;
};
static int xhci_usb_probe(struct udevice *dev)
{
- struct mvebu_xhci_platdata *plat = dev_get_plat(dev);
+ struct mvebu_xhci_plat *plat = dev_get_plat(dev);
struct mvebu_xhci *ctx = dev_get_priv(dev);
struct xhci_hcor *hcor;
int len, ret;
static int xhci_usb_of_to_plat(struct udevice *dev)
{
- struct mvebu_xhci_platdata *plat = dev_get_plat(dev);
+ struct mvebu_xhci_plat *plat = dev_get_plat(dev);
/*
* Get the base address for XHCI controller from the device node
.probe = xhci_usb_probe,
.remove = xhci_deregister,
.ops = &xhci_usb_ops,
- .plat_auto = sizeof(struct mvebu_xhci_platdata),
+ .plat_auto = sizeof(struct mvebu_xhci_plat),
.priv_auto = sizeof(struct mvebu_xhci),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
.remove = xhci_deregister,
.of_match = xhci_pci_ids,
.ops = &xhci_usb_ops,
- .plat_auto = sizeof(struct usb_platdata),
+ .plat_auto = sizeof(struct usb_plat),
.priv_auto = sizeof(struct xhci_ctrl),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#define RCAR_USB3_DL_CTRL_FW_SUCCESS BIT(4)
#define RCAR_USB3_DL_CTRL_FW_SET_DATA0 BIT(8)
-struct rcar_xhci_platdata {
+struct rcar_xhci_plat {
fdt_addr_t hcd_base;
struct clk clk;
};
*/
struct rcar_xhci {
struct xhci_ctrl ctrl; /* Needs to come first in this struct! */
- struct usb_platdata usb_plat;
+ struct usb_plat usb_plat;
struct xhci_hccr *hcd;
};
static int xhci_rcar_probe(struct udevice *dev)
{
- struct rcar_xhci_platdata *plat = dev_get_plat(dev);
+ struct rcar_xhci_plat *plat = dev_get_plat(dev);
struct rcar_xhci *ctx = dev_get_priv(dev);
struct xhci_hcor *hcor;
int len, ret;
static int xhci_rcar_deregister(struct udevice *dev)
{
int ret;
- struct rcar_xhci_platdata *plat = dev_get_plat(dev);
+ struct rcar_xhci_plat *plat = dev_get_plat(dev);
ret = xhci_deregister(dev);
static int xhci_rcar_of_to_plat(struct udevice *dev)
{
- struct rcar_xhci_platdata *plat = dev_get_plat(dev);
+ struct rcar_xhci_plat *plat = dev_get_plat(dev);
plat->hcd_base = dev_read_addr(dev);
if (plat->hcd_base == FDT_ADDR_T_NONE) {
.ops = &xhci_usb_ops,
.of_match = xhci_rcar_ids,
.of_to_plat = xhci_rcar_of_to_plat,
- .plat_auto = sizeof(struct rcar_xhci_platdata),
+ .plat_auto = sizeof(struct rcar_xhci_plat),
.priv_auto = sizeof(struct rcar_xhci),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
.disable = da8xx_musb_disable,
};
-struct da8xx_musb_platdata {
+struct da8xx_musb_plat {
void *base;
void *ctrl_mod_base;
struct musb_hdrc_platform_data plat;
static int da8xx_musb_of_to_plat(struct udevice *dev)
{
- struct da8xx_musb_platdata *plat = dev_get_plat(dev);
+ struct da8xx_musb_plat *plat = dev_get_plat(dev);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
static int da8xx_musb_probe(struct udevice *dev)
{
struct musb_host_data *host = dev_get_priv(dev);
- struct da8xx_musb_platdata *plat = dev_get_plat(dev);
+ struct da8xx_musb_plat *plat = dev_get_plat(dev);
struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
struct omap_musb_board_data *otg_board_data;
int ret;
.probe = da8xx_musb_probe,
.remove = da8xx_musb_remove,
.ops = &musb_usb_ops,
- .plat_auto = sizeof(struct da8xx_musb_platdata),
+ .plat_auto = sizeof(struct da8xx_musb_plat),
.priv_auto = sizeof(struct musb_host_data),
};
#ifdef CONFIG_USB_MUSB_HOST
.ops = &musb_usb_ops,
#endif
- .plat_auto = sizeof(struct usb_platdata),
+ .plat_auto = sizeof(struct usb_plat),
.priv_auto = sizeof(struct mtk_musb_glue),
};
#if CONFIG_IS_ENABLED(DM_USB)
-struct omap2430_musb_platdata {
+struct omap2430_musb_plat {
void *base;
void *ctrl_mod_base;
struct musb_hdrc_platform_data plat;
static int omap2430_musb_of_to_plat(struct udevice *dev)
{
- struct omap2430_musb_platdata *plat = dev_get_plat(dev);
+ struct omap2430_musb_plat *plat = dev_get_plat(dev);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
#else
struct musb *musbp;
#endif
- struct omap2430_musb_platdata *plat = dev_get_plat(dev);
+ struct omap2430_musb_plat *plat = dev_get_plat(dev);
struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
struct omap_musb_board_data *otg_board_data;
int ret = 0;
#ifdef CONFIG_USB_MUSB_HOST
.ops = &musb_usb_ops,
#endif
- .plat_auto = sizeof(struct omap2430_musb_platdata),
+ .plat_auto = sizeof(struct omap2430_musb_plat),
.priv_auto = sizeof(struct musb_host_data),
};
#ifdef CONFIG_USB_MUSB_HOST
.ops = &musb_usb_ops,
#endif
- .plat_auto = sizeof(struct usb_platdata),
+ .plat_auto = sizeof(struct usb_plat),
.priv_auto = sizeof(struct pic32_musb_data),
};
#ifdef CONFIG_USB_MUSB_HOST
.ops = &musb_usb_ops,
#endif
- .plat_auto = sizeof(struct usb_platdata),
+ .plat_auto = sizeof(struct usb_plat),
.priv_auto = sizeof(struct sunxi_glue),
};
static void ti_musb_set_phy_power(struct udevice *dev, u8 on)
{
- struct ti_musb_platdata *plat = dev_get_plat(dev);
+ struct ti_musb_plat *plat = dev_get_plat(dev);
if (!plat->ctrl_mod_base)
return;
static int ti_musb_of_to_plat(struct udevice *dev)
{
- struct ti_musb_platdata *plat = dev_get_plat(dev);
+ struct ti_musb_plat *plat = dev_get_plat(dev);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
int phys;
static int ti_musb_host_probe(struct udevice *dev)
{
struct musb_host_data *host = dev_get_priv(dev);
- struct ti_musb_platdata *plat = dev_get_plat(dev);
+ struct ti_musb_plat *plat = dev_get_plat(dev);
struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
int ret;
#if CONFIG_IS_ENABLED(OF_CONTROL)
static int ti_musb_host_of_to_plat(struct udevice *dev)
{
- struct ti_musb_platdata *plat = dev_get_plat(dev);
+ struct ti_musb_plat *plat = dev_get_plat(dev);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
int ret;
.probe = ti_musb_host_probe,
.remove = ti_musb_host_remove,
.ops = &musb_usb_ops,
- .plat_auto = sizeof(struct ti_musb_platdata),
+ .plat_auto = sizeof(struct ti_musb_plat),
.priv_auto = sizeof(struct musb_host_data),
};
#if CONFIG_IS_ENABLED(OF_CONTROL)
static int ti_musb_peripheral_of_to_plat(struct udevice *dev)
{
- struct ti_musb_platdata *plat = dev_get_plat(dev);
+ struct ti_musb_plat *plat = dev_get_plat(dev);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
int ret;
static int ti_musb_peripheral_probe(struct udevice *dev)
{
struct ti_musb_peripheral *priv = dev_get_priv(dev);
- struct ti_musb_platdata *plat = dev_get_plat(dev);
+ struct ti_musb_plat *plat = dev_get_plat(dev);
int ret;
priv->periph = musb_init_controller(&plat->plat,
.probe = ti_musb_peripheral_probe,
.remove = ti_musb_peripheral_remove,
.ops = &musb_usb_ops,
- .plat_auto = sizeof(struct ti_musb_platdata),
+ .plat_auto = sizeof(struct ti_musb_plat),
.priv_auto = sizeof(struct ti_musb_peripheral),
.flags = DM_FLAG_PRE_RELOC,
};
static int am335x_fb_remove(struct udevice *dev)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
uc_plat->base -= 0x20;
uc_plat->size += 0x20;
static int am335x_fb_probe(struct udevice *dev)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct am335x_fb_priv *priv = dev_get_priv(dev);
struct am335x_lcdhw *regs = priv->regs;
static int am335x_fb_bind(struct udevice *dev)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
uc_plat->size = ((LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
(1 << LCD_MAX_LOG2_BPP)) >> 3) + 0x20;
static void atmel_hlcdc_init(struct udevice *dev)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
struct atmel_hlcd_regs *regs = priv->regs;
struct display_timing *timing = &priv->timing;
static int atmel_hlcdc_bind(struct udevice *dev)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
(1 << LCD_MAX_LOG2_BPP) / 8;
#ifdef CONFIG_DM_VIDEO
static int atmel_fb_lcd_probe(struct udevice *dev)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct atmel_fb_priv *priv = dev_get_priv(dev);
struct display_timing *timing = &priv->timing;
static int atmel_fb_of_to_plat(struct udevice *dev)
{
- struct atmel_lcd_platdata *plat = dev_get_plat(dev);
+ struct atmel_lcd_plat *plat = dev_get_plat(dev);
struct atmel_fb_priv *priv = dev_get_priv(dev);
struct display_timing *timing = &priv->timing;
const void *blob = gd->fdt_blob;
static int atmel_fb_lcd_bind(struct udevice *dev)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
(1 << VIDEO_BPP16) / 8;
.bind = atmel_fb_lcd_bind,
.of_to_plat = atmel_fb_of_to_plat,
.probe = atmel_fb_lcd_probe,
- .plat_auto = sizeof(struct atmel_lcd_platdata),
+ .plat_auto = sizeof(struct atmel_lcd_plat),
.priv_auto = sizeof(struct atmel_fb_priv),
};
#endif
static int bcm2835_video_probe(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
int ret;
int w, h, pitch;
static int broadwell_igd_probe(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
bool is_broadwell;
ulong fbbase;
static int broadwell_igd_bind(struct udevice *dev)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
/* Set the maximum supported resolution */
uc_plat->size = 2560 * 1600 * 4;
static int coreboot_video_probe(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct cb_framebuffer *fb = lib_sysinfo.framebuffer;
struct vesa_mode_info *vesa = &mode_info.vesa;
static int efi_video_probe(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct vesa_mode_info *vesa = &mode_info.vesa;
int ret;
void exynos_fimd_lcd_init(struct udevice *dev)
{
struct exynos_fb_priv *priv = dev_get_priv(dev);
- struct video_uc_platdata *plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct exynos_fb *reg = priv->reg;
unsigned int cfg = 0, rgb_mode;
unsigned int offset;
static int exynos_fb_bind(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
/* This is the maximum panel size we expect to see */
plat->size = 1920 * 1080 * 2;
static int fsl_dcu_video_probe(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct fb_info fbinfo = { 0 };
unsigned int win_x;
static int fsl_dcu_video_bind(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
unsigned int win_x;
unsigned int win_y;
unsigned int depth = 0, freq = 0;
static int mxcfb_map_video_memory(struct fb_info *fbi)
{
struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
- struct video_uc_platdata *plat = dev_get_uclass_plat(mxc_fbi->udev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(mxc_fbi->udev);
if (fbi->fix.smem_len < fbi->var.yres_virtual * fbi->fix.line_length) {
fbi->fix.smem_len = fbi->var.yres_virtual *
static int ipuv3_video_probe(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
#if defined(CONFIG_DISPLAY)
struct udevice *disp_dev;
static int ipuv3_video_bind(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
(1 << VIDEO_BPP32) / 8;
static int bd82x6x_video_probe(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
ulong fbbase;
void *gtt_bar;
int ret, rev;
static int bd82x6x_video_bind(struct udevice *dev)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
/* Set the maximum supported resolution */
uc_plat->size = 2560 * 1600 * 4;
static int malidp_probe(struct udevice *dev)
{
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
- struct video_uc_platdata *uc_plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
ofnode framebuffer = ofnode_find_subnode(dev_ofnode(dev), "framebuffer");
struct malidp_priv *priv = dev_get_priv(dev);
struct display_timing timings;
static int malidp_bind(struct udevice *dev)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
/* choose max possible size: 2K x 2K, XRGB888 framebuffer */
uc_plat->size = 4 * 2048 * 2048;
void meson_vpu_setup_plane(struct udevice *dev, bool is_interlaced)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct meson_vpu_priv *priv = dev_get_priv(dev);
u32 osd1_ctrl_stat;
static int meson_vpu_setup_mode(struct udevice *dev, struct udevice *disp)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct display_timing timing;
bool is_cvbs = false;
static int meson_vpu_bind(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
plat->size = VPU_MAX_WIDTH * VPU_MAX_HEIGHT *
(1 << VPU_MAX_LOG2_BPP) / 8;
static int mvebu_video_probe(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct mvebu_video_priv *priv = dev_get_priv(dev);
struct mvebu_lcd_info lcd_info;
static int mvebu_video_bind(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
(1 << LCD_MAX_LOG2_BPP) / 8;
static int mxs_video_probe(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct display_timing timings;
static int mxs_video_bind(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct display_timing timings;
u32 bpp = 0;
u32 bytes_pp = 0;
static int mxs_video_remove(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
mxs_remove_common(plat->base);
static void nx_display_parse_dp_planes(ofnode node,
struct nx_display_dev *dp,
- struct video_uc_platdata *plat)
+ struct video_uc_plat *plat)
{
const char *name;
ofnode subnode;
static int nx_display_parse_dt(struct udevice *dev,
struct nx_display_dev *dp,
- struct video_uc_platdata *plat)
+ struct video_uc_plat *plat)
{
const char *name, *dtype;
int ret = 0;
struct nx_display_dev *dp;
int i, ret;
int node = 0;
- struct video_uc_platdata *plat = NULL;
+ struct video_uc_plat *plat = NULL;
struct udevice *dev;
static int nx_display_probe(struct udevice *dev)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
- struct nx_display_platdata *plat = dev_get_plat(dev);
+ struct nx_display_plat *plat = dev_get_plat(dev);
static GraphicDevice *graphic_device;
char addr[64];
return -EINVAL;
if (!uc_plat) {
- debug("%s(): video_uc_platdata *plat == NULL --> return -EINVAL\n",
+ debug("%s(): video_uc_plat *plat == NULL --> return -EINVAL\n",
__func__);
return -EINVAL;
}
}
if (!plat) {
- debug("%s(): nx_display_platdata *plat == NULL --> return -EINVAL\n",
+ debug("%s(): nx_display_plat *plat == NULL --> return -EINVAL\n",
__func__);
return -EINVAL;
}
static int nx_display_bind(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
debug("%s()\n", __func__);
.name = "nexell-display",
.id = UCLASS_VIDEO,
.of_match = nx_display_ids,
- .plat_auto = sizeof(struct nx_display_platdata),
+ .plat_auto = sizeof(struct nx_display_plat),
.bind = nx_display_bind,
.probe = nx_display_probe,
.priv_auto = sizeof(struct nx_display_dev),
int rk_vop_probe(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct rk_vop_priv *priv = dev_get_priv(dev);
int ret = 0;
ofnode port, node;
int rk_vop_bind(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
plat->size = 4 * (CONFIG_VIDEO_ROCKCHIP_MAX_XRES *
CONFIG_VIDEO_ROCKCHIP_MAX_YRES);
static int sandbox_sdl_probe(struct udevice *dev)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
struct sandbox_sdl_plat *plat = dev_get_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct sandbox_state *state = state_get_current();
static int sandbox_sdl_bind(struct udevice *dev)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
struct sandbox_sdl_plat *plat = dev_get_plat(dev);
int ret = 0;
static int simple_video_probe(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
const void *blob = gd->fdt_blob;
const int node = dev_of_offset(dev);
static int stm32_ltdc_probe(struct udevice *dev)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct stm32_ltdc_priv *priv = dev_get_priv(dev);
struct udevice *bridge = NULL;
static int stm32_ltdc_bind(struct udevice *dev)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
uc_plat->size = CONFIG_VIDEO_STM32_MAX_XRES *
CONFIG_VIDEO_STM32_MAX_YRES *
static int sunxi_de2_probe(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct udevice *disp;
int ret;
static int sunxi_de2_bind(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
(1 << LCD_MAX_LOG2_BPP) / 8;
{
struct udevice *de2, *hdmi, *lcd;
struct video_priv *de2_priv;
- struct video_uc_platdata *de2_plat;
+ struct video_uc_plat *de2_plat;
int mux;
int offset, ret;
u64 start, size;
static int tegra_lcd_probe(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct tegra_lcd_priv *priv = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
static int tegra_lcd_bind(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
int rgb;
static int tegra124_lcd_probe(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
ulong start;
int ret;
static int tegra124_lcd_bind(struct udevice *dev)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
(1 << VIDEO_BPP16) / 8;
static int vesa_video_probe(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
ulong fbbase;
int ret;
static int vesa_video_bind(struct udevice *dev)
{
- struct video_uc_platdata *uc_plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
/* Set the maximum supported resolution */
uc_plat->size = 2560 * 1600 * 4;
* Theory of operation:
*
* Before relocation each device is bound. The driver for each device must
- * set the @align and @size values in struct video_uc_platdata. This
+ * set the @align and @size values in struct video_uc_plat. This
* information represents the requires size and alignment of the frame buffer
* for the device. The values can be an over-estimate but cannot be too
* small. The actual values will be suppled (in the same manner) by the bind()
static ulong alloc_fb(struct udevice *dev, ulong *addrp)
{
- struct video_uc_platdata *plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
ulong base, align, size;
if (!plat->size)
/* Set up the display ready for use */
static int video_post_probe(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_plat(dev);
+ struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct video_priv *priv = dev_get_uclass_priv(dev);
char name[30], drv[15], *str;
const char *drv_name = drv;
.pre_remove = video_pre_remove,
.priv_auto = sizeof(struct video_uc_priv),
.per_device_auto = sizeof(struct video_priv),
- .per_device_plat_auto = sizeof(struct video_uc_platdata),
+ .per_device_plat_auto = sizeof(struct video_uc_plat),
};
static int virtio_pci_probe(struct udevice *udev)
{
- struct pci_child_platdata *pplat = dev_get_parent_plat(udev);
+ struct pci_child_plat *pplat = dev_get_parent_plat(udev);
struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev);
struct virtio_pci_priv *priv = dev_get_priv(udev);
u16 subvendor, subdevice;
static int virtio_pci_probe(struct udevice *udev)
{
- struct pci_child_platdata *pplat = dev_get_parent_plat(udev);
+ struct pci_child_plat *pplat = dev_get_parent_plat(udev);
struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev);
struct virtio_pci_priv *priv = dev_get_priv(udev);
u16 subvendor;
u32 tbr; /* 0x8 */
};
-struct xlnx_wdt_platdata {
+struct xlnx_wdt_plat {
bool enable_once;
struct watchdog_regs *regs;
};
static int xlnx_wdt_reset(struct udevice *dev)
{
u32 reg;
- struct xlnx_wdt_platdata *plat = dev_get_plat(dev);
+ struct xlnx_wdt_plat *plat = dev_get_plat(dev);
debug("%s ", __func__);
static int xlnx_wdt_stop(struct udevice *dev)
{
u32 reg;
- struct xlnx_wdt_platdata *plat = dev_get_plat(dev);
+ struct xlnx_wdt_plat *plat = dev_get_plat(dev);
if (plat->enable_once) {
debug("Can't stop Xilinx watchdog.\n");
static int xlnx_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
{
- struct xlnx_wdt_platdata *plat = dev_get_plat(dev);
+ struct xlnx_wdt_plat *plat = dev_get_plat(dev);
debug("%s:\n", __func__);
static int xlnx_wdt_of_to_plat(struct udevice *dev)
{
- struct xlnx_wdt_platdata *plat = dev_get_plat(dev);
+ struct xlnx_wdt_plat *plat = dev_get_plat(dev);
plat->regs = (struct watchdog_regs *)dev_read_addr(dev);
if (IS_ERR(plat->regs))
.id = UCLASS_WDT,
.of_match = xlnx_wdt_ids,
.probe = xlnx_wdt_probe,
- .plat_auto = sizeof(struct xlnx_wdt_platdata),
+ .plat_auto = sizeof(struct xlnx_wdt_plat),
.of_to_plat = xlnx_wdt_of_to_plat,
.ops = &xlnx_wdt_ops,
};
struct clk clk;
};
-struct xlnx_wwdt_platdata {
+struct xlnx_wwdt_plat {
bool enable_once;
};
static int xlnx_wwdt_probe(struct udevice *dev)
{
int ret;
- struct xlnx_wwdt_platdata *plat = dev_get_plat(dev);
+ struct xlnx_wwdt_plat *plat = dev_get_plat(dev);
struct xlnx_wwdt_priv *wdt = dev_get_priv(dev);
dev_dbg(dev, "%s: Probing wdt%u\n", __func__, dev->seq);
static int xlnx_wwdt_of_to_plat(struct udevice *dev)
{
- struct xlnx_wwdt_platdata *plat = dev_get_plat(dev);
+ struct xlnx_wwdt_plat *plat = dev_get_plat(dev);
plat->enable_once = dev_read_u32_default(dev, "xlnx,wdt-enable-once",
0);
.of_match = xlnx_wwdt_ids,
.probe = xlnx_wwdt_probe,
.priv_auto = sizeof(struct xlnx_wwdt_priv),
- .plat_auto = sizeof(struct xlnx_wwdt_platdata),
+ .plat_auto = sizeof(struct xlnx_wwdt_plat),
.of_to_plat = xlnx_wwdt_of_to_plat,
.ops = &xlnx_wwdt_ops,
};
u8 *bounce_buffer;
};
-struct blkfront_platdata {
+struct blkfront_plat {
unsigned int devid;
};
static int pvblock_blk_probe(struct udevice *udev)
{
struct blkfront_dev *blk_dev = dev_get_priv(udev);
- struct blkfront_platdata *plat = dev_get_plat(udev);
+ struct blkfront_plat *plat = dev_get_plat(udev);
struct blk_desc *desc = dev_get_uclass_plat(udev);
int ret, devid;
{
struct driver_info info;
struct udevice *udev;
- struct blkfront_platdata *plat;
+ struct blkfront_plat *plat;
int ret;
debug("New " DRV_NAME_BLK ", device ID %d\n", devid);
- plat = malloc(sizeof(struct blkfront_platdata));
+ plat = malloc(sizeof(struct blkfront_plat));
if (!plat) {
printf("Failed to allocate platform data\n");
return -ENOMEM;
#define _ATMEL_LCD_H_
/**
- * struct atmel_lcd_platdata - platform data for Atmel LCDs with driver model
+ * struct atmel_lcd_plat - platform data for Atmel LCDs with driver model
*
* @timing_index: Index of LCD timing to use in device tree node
*/
-struct atmel_lcd_platdata {
+struct atmel_lcd_plat {
int timing_index;
};
#define __CPU_H
/**
- * struct cpu_platdata - platform data for a CPU
+ * struct cpu_plat - platform data for a CPU
* @cpu_id: Platform-specific way of identifying the CPU.
* @ucode_version: Microcode version, if CPU_FEAT_UCODE is set
* @device_id: Driver-defined device identifier
* This can be accessed with dev_get_parent_plat() for any UCLASS_CPU
* device.
*/
-struct cpu_platdata {
+struct cpu_plat {
int cpu_id;
int ucode_version;
ulong device_id;
#ifndef __fsl_espi_h
#define __fsl_espi_h
-struct fsl_espi_platdata {
+struct fsl_espi_plat {
uint flags;
uint speed_hz;
uint num_chipselect;
#define _LPC32XX_HSUART_PLAT_H
/**
- * struct lpc32xx_hsuart_platdata - NXP LPC32xx HSUART platform data
+ * struct lpc32xx_hsuart_plat - NXP LPC32xx HSUART platform data
*
* @base: Base register address
*/
-struct lpc32xx_hsuart_platdata {
+struct lpc32xx_hsuart_plat {
unsigned long base;
};
#include <mmc.h>
/*
- * struct pxa_mmc_platdata - information about a PXA MMC controller
+ * struct pxa_mmc_plat - information about a PXA MMC controller
*
* @base: MMC controller base register address
*/
*
* @base: Register base address
*/
-struct bcm283x_mu_serial_platdata {
+struct bcm283x_mu_serial_plat {
unsigned long base;
unsigned int clock;
bool skip_init;
#define __serial_coldfire_h
/*
- * struct coldfire_serial_platdata - information about a coldfire port
+ * struct coldfire_serial_plat - information about a coldfire port
*
* @base: Uart port base register address
* @port: Uart port index, for cpu with pinmux for uart / gpio
* baudrtatre: Uart port baudrate
*/
-struct coldfire_serial_platdata {
+struct coldfire_serial_plat {
unsigned long base;
int port;
int baudrate;
#define __serial_mxc_h
/* Information about a serial port */
-struct mxc_serial_platdata {
+struct mxc_serial_plat {
struct mxc_uart *reg; /* address of registers in physical memory */
bool use_dte;
};
* @skip_init: Don't attempt to change port configuration (also means @clock
* is ignored)
*/
-struct pl01x_serial_platdata {
+struct pl01x_serial_plat {
unsigned long base;
enum pl01x_type type;
unsigned int clock;
#endif
/*
- * struct pxa_serial_platdata - information about a PXA port
+ * struct pxa_serial_plat - information about a PXA port
*
* @base: Uart port base register address
* @port: Uart port index, for cpu with pinmux for uart / gpio
* baudrtatre: Uart port baudrate
*/
-struct pxa_serial_platdata {
+struct pxa_serial_plat {
struct pxa_uart_regs *base;
int port;
int baudrate;
* @clk_mode: Clock mode, set internal (INT) or external (EXT)
* @type: Type of SCIF
*/
-struct sh_serial_platdata {
+struct sh_serial_plat {
unsigned long base;
unsigned int clk;
enum sh_clk_mode clk_mode;
#define MAX_CTAR_FIELDS 8
/*
- * struct coldfire_spi_platdata - information about a coldfire spi module
+ * struct coldfire_spi_plat - information about a coldfire spi module
*
* @regs_addr: base address for module registers
* @speed_hz: default SCK frequency
* @mode: default SPI mode
* @num_cs: number of DSPI chipselect signals
*/
-struct coldfire_spi_platdata {
+struct coldfire_spi_plat {
fdt_addr_t regs_addr;
uint speed_hz;
uint mode;
#ifndef __spi_davinci_h
#define __spi_davinci_h
-struct davinci_spi_platdata {
+struct davinci_spi_plat {
struct davinci_spi_regs *regs;
u8 num_cs; /* total no. of CS available */
};
void dm_fixup_for_gd_move(struct global_data *new_gd);
/**
- * dm_scan_platdata() - Scan all platform data and bind drivers
+ * dm_scan_plat() - Scan all platform data and bind drivers
*
* This scans all available plat and creates drivers for each
*
* flag. If false bind all drivers.
* @return 0 if OK, -ve on error
*/
-int dm_scan_platdata(bool pre_reloc_only);
+int dm_scan_plat(bool pre_reloc_only);
/**
* dm_scan_fdt() - Scan the device tree and bind drivers
* @mtdpart: MTD partition for ubi partition.
* @ubivol: UBI volume-name for ubifsmount.
*/
-struct device_platdata {
+struct device_plat {
struct phandle_part phandlepart;
char *mtdpart;
char *ubivol;
};
/**
- * struct ns16550_platdata - information about a NS16550 port
+ * struct ns16550_plat - information about a NS16550 port
*
* @base: Base register address
* @reg_width: IO accesses size of registers (in bytes, 1 or 4)
* @flags: A few flags (enum ns16550_flags)
* @bdf: PCI slot/function (pci_dev_t)
*/
-struct ns16550_platdata {
+struct ns16550_plat {
unsigned long base;
int reg_width;
int reg_shift;
UART_REG(ssr); /* 11*/
#endif
#ifdef CONFIG_DM_SERIAL
- struct ns16550_platdata *plat;
+ struct ns16550_plat *plat;
#endif
};
#define PCH_P2SB_HBDF 0x70
/**
- * struct p2sb_child_platdata - Information about each child of a p2sb device
+ * struct p2sb_child_plat - Information about each child of a p2sb device
*
* @pid: Port ID for this child
*/
-struct p2sb_child_platdata {
+struct p2sb_child_plat {
uint pid;
};
#ifdef CONFIG_DM_PCI
/**
- * struct pci_child_platdata - information stored about each PCI device
+ * struct pci_child_plat - information stored about each PCI device
*
* Every device on a PCI bus has this per-child data.
*
* @pfdev: Handle to Physical Function device
* @virtid: Virtual Function Index
*/
-struct pci_child_platdata {
+struct pci_child_plat {
int devfn;
unsigned short vendor;
unsigned short device;
*/
int pmc_global_reset_set_enable(struct udevice *dev, bool enable);
-int pmc_ofdata_to_uc_platdata(struct udevice *dev);
+int pmc_ofdata_to_uc_plat(struct udevice *dev);
int pmc_disable_tco_base(ulong tco_base);
int regmap_init_mem(ofnode node, struct regmap **mapp);
/**
- * regmap_init_mem_platdata() - Set up a new memory register map for
+ * regmap_init_mem_plat() - Set up a new memory register map for
* of-platdata
*
* @dev: Device that uses this map
* Use regmap_uninit() to free it.
*
*/
-int regmap_init_mem_platdata(struct udevice *dev, fdt_val_t *reg, int count,
- struct regmap **mapp);
+int regmap_init_mem_plat(struct udevice *dev, fdt_val_t *reg, int count,
+ struct regmap **mapp);
int regmap_init_mem_index(ofnode node, struct regmap **mapp, int index);
#define SCSI_WRITE_SAME 0x41 /* Write Same (O) */
/**
- * struct scsi_platdata - stores information about SCSI controller
+ * struct scsi_plat - stores information about SCSI controller
*
* @base: Controller base address
* @max_lun: Maximum number of logical units
* @max_id: Maximum number of target ids
* @max_bytes_per_req: Maximum number of bytes per read/write request
*/
-struct scsi_platdata {
+struct scsi_plat {
unsigned long base;
unsigned long max_lun;
unsigned long max_id;
};
/**
- * struct dm_spi_platdata - platform data for all SPI slaves
+ * struct dm_spi_plat - platform data for all SPI slaves
*
* This describes a SPI slave, a child device of the SPI bus. To obtain this
* struct from a spi_slave, use dev_get_parent_plat(dev) or
* @max_hz: Maximum bus speed that this slave can tolerate
* @mode: SPI mode to use for this device (see SPI mode flags)
*/
-struct dm_spi_slave_platdata {
+struct dm_spi_slave_plat {
unsigned int cs;
uint max_hz;
uint mode;
* @node: Node offset to read from
* @plat: Place to put the decoded information
*/
-int spi_slave_of_to_plat(struct udevice *dev,
- struct dm_spi_slave_platdata *plat);
+int spi_slave_of_to_plat(struct udevice *dev, struct dm_spi_slave_plat *plat);
/**
* spi_cs_info() - Check information on a chip select
*
* Update: 64-bit is now supported and we have an education crisis.
*/
-struct syscon_base_platdata {
+struct syscon_base_plat {
fdt_val_t reg[2];
};
#endif
#if CONFIG_IS_ENABLED(DM_USB)
/**
- * struct usb_platdata - Platform data about a USB controller
+ * struct usb_plat - Platform data about a USB controller
*
* Given a USB controller (UCLASS_USB) dev this is dev_get_plat(dev)
*/
-struct usb_platdata {
+struct usb_plat {
enum usb_init_type init_type;
};
/**
- * struct usb_dev_platdata - Platform data about a USB device
+ * struct usb_dev_plat - Platform data about a USB device
*
* Given a USB device dev this structure is dev_get_parent_plat(dev).
* This is used by sandbox to provide emulation data also.
* @strings: List of descriptor strings (for sandbox emulation purposes)
* @desc_list: List of descriptors (for sandbox emulation purposes)
*/
-struct usb_dev_platdata {
+struct usb_dev_plat {
struct usb_device_id id;
int devnum;
/*
};
/**
- * struct usb_emul_platdata - platform data about the USB emulator
+ * struct usb_emul_plat - platform data about the USB emulator
*
* Given a USB emulator (UCLASS_USB_EMUL) 'dev', this is
* dev_get_uclass_plat(dev).
*
* @port1: USB emulator device port number on the parent hub
*/
-struct usb_emul_platdata {
+struct usb_emul_plat {
int port1; /* Port number (numbered from 1) */
};
extern struct vbe_mode_info mode_info;
struct video_priv;
-struct video_uc_platdata;
+struct video_uc_plat;
int vbe_setup_video_priv(struct vesa_mode_info *vesa,
struct video_priv *uc_priv,
- struct video_uc_platdata *plat);
+ struct video_uc_plat *plat);
int vbe_setup_video(struct udevice *dev, int (*int15_handler)(void));
#endif
struct udevice;
/**
- * struct video_uc_platdata - uclass platform data for a video device
+ * struct video_uc_plat - uclass platform data for a video device
*
* This holds information that the uclass needs to know about each device. It
* is accessed using dev_get_uclass_plat(dev). See 'Theory of operation' at
* @copy_base: Base address of a hardware copy of the frame buffer. See
* CONFIG_VIDEO_COPY.
*/
-struct video_uc_platdata {
+struct video_uc_plat {
uint align;
uint size;
ulong base;
* @fb: Frame buffer
* @fb_size: Frame buffer size
* @copy_fb: Copy of the frame buffer to keep up to date; see struct
- * video_uc_platdata
+ * video_uc_plat
* @line_length: Length of each frame buffer line, in bytes. This can be
* set by the driver, but if not, the uclass will set it after
* probing
static int acpi_device_set_spi(const struct udevice *dev, struct acpi_spi *spi,
const char *scope)
{
- struct dm_spi_slave_platdata *plat;
+ struct dm_spi_slave_plat *plat;
struct spi_slave *slave = dev_get_parent_priv(dev);
plat = dev_get_parent_plat(slave->dev);
* handle handle of the controller on which this driver is installed
* io block io protocol proxied by this driver
*/
-struct efi_blk_platdata {
+struct efi_blk_plat {
efi_handle_t handle;
struct efi_block_io *io;
};
static ulong efi_bl_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
void *buffer)
{
- struct efi_blk_platdata *plat = dev_get_plat(dev);
+ struct efi_blk_plat *plat = dev_get_plat(dev);
struct efi_block_io *io = plat->io;
efi_status_t ret;
static ulong efi_bl_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
const void *buffer)
{
- struct efi_blk_platdata *plat = dev_get_plat(dev);
+ struct efi_blk_plat *plat = dev_get_plat(dev);
struct efi_block_io *io = plat->io;
efi_status_t ret;
struct efi_object *obj = efi_search_obj(handle);
struct efi_block_io *io = interface;
int disks;
- struct efi_blk_platdata *plat;
+ struct efi_blk_plat *plat;
EFI_PRINT("%s: handle %p, interface %p\n", __func__, handle, io);
.name = "efi_blk",
.id = UCLASS_BLK,
.ops = &efi_blk_ops,
- .plat_auto = sizeof(struct efi_blk_platdata),
+ .plat_auto = sizeof(struct efi_blk_plat),
};
/* EFI driver operators */
uclass_find_first_device(UCLASS_CPU, &cpu);
if (cpu) {
- struct cpu_platdata *plat = dev_get_parent_plat(cpu);
+ struct cpu_plat *plat = dev_get_parent_plat(cpu);
if (plat->family)
processor_family = plat->family;
#define BUF_SIZE 4096
/**
- * struct testacpi_platdata - Platform data for the test ACPI device
+ * struct testacpi_plat - Platform data for the test ACPI device
*
* @no_name: true to emit an empty ACPI name from testacpi_get_name()
* @return_error: true to return an error instead of a name
*/
-struct testacpi_platdata {
+struct testacpi_plat {
bool return_error;
bool no_name;
};
static int testacpi_get_name(const struct udevice *dev, char *out_name)
{
- struct testacpi_platdata *plat = dev_get_plat(dev);
+ struct testacpi_plat *plat = dev_get_plat(dev);
if (plat->return_error)
return -EINVAL;
.of_match = testacpi_ids,
.id = UCLASS_TEST_ACPI,
.bind = dm_scan_fdt_dev,
- .plat_auto = sizeof(struct testacpi_platdata),
+ .plat_auto = sizeof(struct testacpi_plat),
ACPI_OPS_PTR(&testacpi_ops)
};
/* Test acpi_device_path() */
static int dm_test_acpi_device_path(struct unit_test_state *uts)
{
- struct testacpi_platdata *plat;
+ struct testacpi_plat *plat;
char buf[ACPI_PATH_MAX];
struct udevice *dev, *child;
ut_asserteq(0, list_count_items(&gd->dm_root->child_head));
ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_POST_BIND]);
- ut_assertok(dm_scan_platdata(false));
+ ut_assertok(dm_scan_plat(false));
/* We should have our test class now at least, plus more children */
ut_assert(1 < list_count_items(&gd->uclass_root));
DM_TEST(dm_test_autoprobe, UT_TESTF_SCAN_PDATA);
/* Check that we see the correct plat in each device */
-static int dm_test_platdata(struct unit_test_state *uts)
+static int dm_test_plat(struct unit_test_state *uts)
{
const struct dm_test_pdata *pdata;
struct udevice *dev;
return 0;
}
-DM_TEST(dm_test_platdata, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_plat, UT_TESTF_SCAN_PDATA);
/* Test that we can bind, probe, remove, unbind a driver */
static int dm_test_lifecycle(struct unit_test_state *uts)
dm_leak_check_start(uts);
- ut_assertok(dm_scan_platdata(false));
+ ut_assertok(dm_scan_plat(false));
ut_assertok(dm_scan_fdt(false));
/* Scanning the uclass is enough to probe all the devices */
#include <test/ut.h>
/* Test that we can find a device using of-platdata */
-static int dm_test_of_platdata_base(struct unit_test_state *uts)
+static int dm_test_of_plat_base(struct unit_test_state *uts)
{
struct udevice *dev;
return 0;
}
-DM_TEST(dm_test_of_platdata_base, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_of_plat_base, UT_TESTF_SCAN_PDATA);
/* Test that we can read properties from a device */
-static int dm_test_of_platdata_props(struct unit_test_state *uts)
+static int dm_test_of_plat_props(struct unit_test_state *uts)
{
struct dtd_sandbox_spl_test *plat;
struct udevice *dev;
return 0;
}
-DM_TEST(dm_test_of_platdata_props, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_of_plat_props, UT_TESTF_SCAN_PDATA);
/*
* find_driver_info - recursively find the driver_info for a device
}
/* Check that every device is recorded in its driver_info struct */
-static int dm_test_of_platdata_dev(struct unit_test_state *uts)
+static int dm_test_of_plat_dev(struct unit_test_state *uts)
{
const struct driver_info *info =
ll_entry_start(struct driver_info, driver_info);
return 0;
}
-DM_TEST(dm_test_of_platdata_dev, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_of_plat_dev, UT_TESTF_SCAN_PDATA);
/* Test handling of phandles that point to other devices */
-static int dm_test_of_platdata_phandle(struct unit_test_state *uts)
+static int dm_test_of_plat_phandle(struct unit_test_state *uts)
{
struct dtd_sandbox_clk_test *plat;
struct udevice *dev, *clk;
return 0;
}
-DM_TEST(dm_test_of_platdata_phandle, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_of_plat_phandle, UT_TESTF_SCAN_PDATA);
#if CONFIG_IS_ENABLED(OF_PLATDATA_PARENT)
/* Test that device parents are correctly set up */
-static int dm_test_of_platdata_parent(struct unit_test_state *uts)
+static int dm_test_of_plat_parent(struct unit_test_state *uts)
{
struct udevice *rtc, *i2c;
return 0;
}
-DM_TEST(dm_test_of_platdata_parent, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_of_plat_parent, UT_TESTF_SCAN_PDATA);
#endif
uts->start = mallinfo();
if (test->flags & UT_TESTF_SCAN_PDATA)
- ut_assertok(dm_scan_platdata(false));
+ ut_assertok(dm_scan_plat(false));
if (test->flags & UT_TESTF_PROBE_TEST)
ut_assertok(do_autoprobe(uts));
if (!CONFIG_IS_ENABLED(OF_PLATDATA) &&
gd_set_of_root(uts->of_root);
gd->dm_root = NULL;
ut_assertok(dm_init(CONFIG_IS_ENABLED(OF_LIVE)));
- dm_scan_platdata(false);
+ dm_scan_plat(false);
if (!CONFIG_IS_ENABLED(OF_PLATDATA))
dm_scan_fdt(false);
projects / u-boot.git / commitdiff
