riscv: do not blindly modify the mstatus CSR

The mstatus CSR includes WPRI (writes preserve values, reads ignore
values) fields and must therefore not be set to zero without preserving
these fields. It is not apparent why mstatus is set to zero here since
it is not required for U-Boot to run. Remove it.

This instruction and others encode zero as an immediate.  RISC-V has the
zero register for this purpose. Replace the immediates with the zero
register.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index c313477ae072d82251025c87a581a9745b1591a1..b01ea6e224082ebd477a893f774fe50b50a4cf94 100644 (file)
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -38,8 +38,9 @@ _start:
        SREG    a2, 0(t0)
        la      t0, trap_entry
        csrw    mtvec, t0
-       csrwi   mstatus, 0
-       csrwi   mie, 0
+
+       /* mask all interrupts */
+       csrw    mie, zero
 
 /*
  * Set stackpointer in internal/ex RAM to call board_init_f
@@ -160,11 +161,10 @@ clear_bss:
        add     t0, t0, t6              /* t0 <- rel __bss_start in RAM */
        la      t1, __bss_end           /* t1 <- rel __bss_end in FLASH */
        add     t1, t1, t6              /* t1 <- rel __bss_end in RAM */
-       li      t2, 0x00000000          /* clear */
        beq     t0, t1, call_board_init_r
 
 clbss_l:
-       SREG    t2, 0(t0)               /* clear loop... */
+       SREG    zero, 0(t0)             /* clear loop... */
        addi    t0, t0, REGBYTES
        bne     t0, t1, clbss_l