x86: acpi: Add DPTF asl files

Add common DPTF (Intel Dynamic Performance and Thermal Framework) files,
taken from coreboot.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/include/asm/acpi/dptf/charger.asl b/arch/x86/include/asm/acpi/dptf/charger.asl
new file mode 100644 (file)
index 0000000..7f4a7ec
--- /dev/null
+++ b/arch/x86/include/asm/acpi/dptf/charger.asl
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2016 Intel Corporation.
+ */
+
+Device (TCHG)
+{
+       Name (_HID, "INT3403")
+       Name (_UID, 0)
+       Name (PTYP, 0x0B)
+       Name (_STR, Unicode("Battery Charger"))
+
+       Method (_STA)
+       {
+               If (LEqual (\DPTE, One)) {
+                       Return (0xF)
+               } Else {
+                       Return (0x0)
+               }
+       }
+
+       /* Return charger performance states defined by mainboard */
+       Method (PPSS)
+       {
+               Return (\_SB.CHPS)
+       }
+
+       /* Return maximum charger current limit */
+       Method (PPPC)
+       {
+               /* Convert size of PPSS table to index */
+               Store (SizeOf (\_SB.CHPS), Local0)
+               Decrement (Local0)
+
+               /* Check if charging is disabled (AC removed) */
+               If (LEqual (\_SB.PCI0.LPCB.EC0.ACEX, Zero)) {
+                       /* Return last power state */
+                       Return (Local0)
+               } Else {
+                       /* Return highest power state */
+                       Return (0)
+               }
+
+               Return (0)
+       }
+
+       /* Set charger current limit */
+       Method (SPPC, 1)
+       {
+               /* Retrieve Control (index 4) for specified PPSS level */
+               Store (DeRefOf (Index (DeRefOf (Index
+                       (\_SB.CHPS, ToInteger (Arg0))), 4)), Local0)
+
+               /* Pass Control value to EC to limit charging */
+               \_SB.PCI0.LPCB.EC0.CHGS (Local0)
+       }
+
+       /* Initialize charger participant */
+       Method (INIT)
+       {
+               /* Disable charge limit */
+               \_SB.PCI0.LPCB.EC0.CHGD ()
+       }
+}

diff --git a/arch/x86/include/asm/acpi/dptf/cpu.asl b/arch/x86/include/asm/acpi/dptf/cpu.asl
new file mode 100644 (file)
index 0000000..f77d353
--- /dev/null
+++ b/arch/x86/include/asm/acpi/dptf/cpu.asl
@@ -0,0 +1,186 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2016 Intel Corporation.
+ */
+
+External (\_PR.CP00._PSS, PkgObj)
+External (\_PR.CP00._TSS, PkgObj)
+External (\_PR.CP00._TPC, MethodObj)
+External (\_PR.CP00._PTC, PkgObj)
+External (\_PR.CP00._TSD, PkgObj)
+External (\_SB.MPDL, IntObj)
+
+Device (DPTF_CPU_DEVICE)
+{
+       Name(_ADR, DPTF_CPU_ADDR)
+
+       Method (_STA)
+       {
+               If (LEqual (\DPTE, One)) {
+                       Return (0xF)
+               } Else {
+                       Return (0x0)
+               }
+       }
+
+       /*
+        * Processor Throttling Controls
+        */
+
+       Method (_TSS)
+       {
+               If (CondRefOf (\_PR.CP00._TSS)) {
+                       Return (\_PR.CP00._TSS)
+               } Else {
+                       Return (Package ()
+                       {
+                               Package () { 0, 0, 0, 0, 0 }
+                       })
+               }
+       }
+
+       Method (_TPC)
+       {
+               If (CondRefOf (\_PR.CP00._TPC)) {
+                       Return (\_PR.CP00._TPC)
+               } Else {
+                       Return (0)
+               }
+       }
+
+       Method (_PTC)
+       {
+               If (CondRefOf (\_PR.CP00._PTC)) {
+                       Return (\_PR.CP00._PTC)
+               } Else {
+                       Return (Package ()
+                       {
+                               Buffer () { 0 },
+                               Buffer () { 0 }
+                       })
+               }
+       }
+
+       Method (_TSD)
+       {
+               If (CondRefOf (\_PR.CP00._TSD)) {
+                       Return (\_PR.CP00._TSD)
+               } Else {
+                       Return (Package ()
+                       {
+                               Package () { 5, 0, 0, 0, 0 }
+                       })
+               }
+       }
+
+       Method (_TDL)
+       {
+               If (CondRefOf (\_PR.CP00._TSS)) {
+                       Store (SizeOf (\_PR.CP00._TSS), Local0)
+                       Decrement (Local0)
+                       Return (Local0)
+               } Else {
+                       Return (0)
+               }
+       }
+
+       /*
+        * Processor Performance Control
+        */
+
+       Method (_PPC)
+       {
+               Return (0)
+       }
+
+       Method (SPPC, 1)
+       {
+               Store (Arg0, \PPCM)
+
+               /* Notify OS to re-read _PPC limit on each CPU */
+               \PPCN ()
+       }
+
+       Method (_PSS)
+       {
+               If (CondRefOf (\_PR.CP00._PSS)) {
+                       Return (\_PR.CP00._PSS)
+               } Else {
+                       Return (Package ()
+                       {
+                               Package () { 0, 0, 0, 0, 0, 0 }
+                       })
+               }
+       }
+
+
+       Method (_PDL)
+       {
+               /* Check for mainboard specific _PDL override */
+               If (CondRefOf (\_SB.MPDL)) {
+                       Return (\_SB.MPDL)
+               } ElseIf (CondRefOf (\_PR.CP00._PSS)) {
+                       Store (SizeOf (\_PR.CP00._PSS), Local0)
+                       Decrement (Local0)
+                       Return (Local0)
+               } Else {
+                       Return (0)
+               }
+       }
+
+       /* Return PPCC table defined by mainboard */
+       Method (PPCC)
+       {
+               Return (\_SB.MPPC)
+       }
+
+#ifdef DPTF_CPU_CRITICAL
+       Method (_CRT)
+       {
+               Return (\_SB.DPTF.CTOK (DPTF_CPU_CRITICAL))
+       }
+#endif
+
+#ifdef DPTF_CPU_PASSIVE
+       Method (_PSV)
+       {
+               Return (\_SB.DPTF.CTOK (DPTF_CPU_PASSIVE))
+       }
+#endif
+
+#ifdef DPTF_CPU_ACTIVE_AC0
+       Method (_AC0)
+       {
+               Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC0))
+       }
+#endif
+
+#ifdef DPTF_CPU_ACTIVE_AC1
+       Method (_AC1)
+       {
+               Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC1))
+       }
+#endif
+
+#ifdef DPTF_CPU_ACTIVE_AC2
+       Method (_AC2)
+       {
+               Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC2))
+       }
+#endif
+
+#ifdef DPTF_CPU_ACTIVE_AC3
+       Method (_AC3)
+       {
+               Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC3))
+       }
+#endif
+
+#ifdef DPTF_CPU_ACTIVE_AC4
+       Method (_AC4)
+       {
+               Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC4))
+       }
+#endif
+}

diff --git a/arch/x86/include/asm/acpi/dptf/dptf.asl b/arch/x86/include/asm/acpi/dptf/dptf.asl
new file mode 100644 (file)
index 0000000..5f958d2
--- /dev/null
+++ b/arch/x86/include/asm/acpi/dptf/dptf.asl
@@ -0,0 +1,121 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2016 Intel Corporation.
+ */
+
+Device (DPTF)
+{
+       Name (_HID, EISAID ("INT3400"))
+       Name (_UID, 0)
+
+       Name (IDSP, Package()
+       {
+               /* DPPM Passive Policy 1.0 */
+               ToUUID ("42A441D6-AE6A-462B-A84B-4A8CE79027D3"),
+
+               /* DPPM Critical Policy */
+               ToUUID ("97C68AE7-15FA-499c-B8C9-5DA81D606E0A"),
+
+               /* DPPM Cooling Policy */
+               ToUUID ("16CAF1B7-DD38-40ED-B1C1-1B8A1913D531"),
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+               /* DPPM Active Policy */
+               ToUUID ("3A95C389-E4B8-4629-A526-C52C88626BAE"),
+#endif
+       })
+
+       Method (_STA)
+       {
+               If (LEqual (\DPTE, One)) {
+                       Return (0xF)
+               } Else {
+                       Return (0x0)
+               }
+       }
+
+       /*
+        * Arg0: Buffer containing UUID
+        * Arg1: Integer containing Revision ID of buffer format
+        * Arg2: Integer containing count of entries in Arg3
+        * Arg3: Buffer containing list of DWORD capabilities
+        * Return: Buffer containing list of DWORD capabilities
+        */
+       Method (_OSC, 4, Serialized)
+       {
+               /* Check for Passive Policy UUID */
+               If (LEqual (DeRefOf (Index (IDSP, 0)), Arg0)) {
+                       /* Initialize Thermal Devices */
+                       ^TINI ()
+
+#ifdef DPTF_ENABLE_CHARGER
+                       /* Initialize Charger Device */
+                       ^TCHG.INIT ()
+#endif
+               }
+
+               Return (Arg3)
+       }
+
+       /* Priority based _TRT */
+       Name (TRTR, 1)
+
+       Method (_TRT)
+       {
+               Return (\_SB.DTRT)
+       }
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+       /* _ART : Active Cooling Relationship Table */
+       Method (_ART)
+       {
+               Return (\_SB.DART)
+       }
+#endif
+
+       /* Convert from Degrees C to 1/10 Kelvin for ACPI */
+       Method (CTOK, 1) {
+               /* 10th of Degrees C */
+               Multiply (Arg0, 10, Local0)
+
+               /* Convert to Kelvin */
+               Add (Local0, 2732, Local0)
+
+               Return (Local0)
+       }
+
+       /* Convert from 1/10 Kelvin to Degrees C for ACPI */
+       Method (KTOC, 1) {
+               If (LLessEqual (Arg0, 2732)) {
+                       Return (0)
+               }
+
+               /* Convert to Celsius */
+               Subtract (Arg0, 2732, Local0)
+
+               /* Convert from 10th of degrees */
+               Divide (Local0, 10,, Local0)
+
+               Return (Local0)
+       }
+
+       /* Include Thermal Participants */
+       #include "thermal.asl"
+
+#ifdef DPTF_ENABLE_CHARGER
+       /* Include Charger Participant */
+       #include "charger.asl"
+#endif
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+       /* Include Fan Participant */
+       #include "fan.asl"
+#endif
+
+}
+
+Scope (\_SB.PCI0)
+{
+       #include "cpu.asl"
+}

diff --git a/arch/x86/include/asm/acpi/dptf/fan.asl b/arch/x86/include/asm/acpi/dptf/fan.asl
new file mode 100644 (file)
index 0000000..aa4aa12
--- /dev/null
+++ b/arch/x86/include/asm/acpi/dptf/fan.asl
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Intel Corporation.
+ */
+
+Device (TFN1)
+{
+       Name (_HID, "INT3404")
+       Name (_UID, 0)
+       Name (_STR, Unicode("Fan Control"))
+
+       /* _FIF: Fan Information */
+       Name (_FIF, Package ()
+       {
+               0,      // Revision
+               1,      // Fine Grained Control
+               2,      // Step Size
+               0       // No Low Speed Notification
+       })
+
+       /* Return Fan Performance States defined by mainboard */
+       Method (_FPS)
+       {
+               Return (\_SB.DFPS)
+       }
+
+       Name (TFST, Package ()
+       {
+               0,      // Revision
+               0x00,   // Control
+               0x00    // Speed
+       })
+
+       /* _FST: Fan current Status */
+       Method (_FST, 0, Serialized,,PkgObj)
+       {
+               /* Fill in TFST with current control. */
+               Store (\_SB.PCI0.LPCB.EC0.FAND, Index (TFST, 1))
+               Return (TFST)
+       }
+
+       /* _FSL: Fan Speed Level */
+       Method (_FSL, 1, Serialized)
+       {
+               Store (Arg0, \_SB.PCI0.LPCB.EC0.FAND)
+       }
+
+       Method (_STA)
+       {
+               If (LEqual (\DPTE, One))
+               {
+                       Return (0xF)
+               } Else {
+                       Return (0x0)
+               }
+       }
+}

diff --git a/arch/x86/include/asm/acpi/dptf/thermal.asl b/arch/x86/include/asm/acpi/dptf/thermal.asl
new file mode 100644 (file)
index 0000000..4c3c8db
--- /dev/null
+++ b/arch/x86/include/asm/acpi/dptf/thermal.asl
@@ -0,0 +1,521 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2016 Intel Corporation.
+ */
+
+/* Thermal Threshold Event Handler */
+#define HAVE_THERM_EVENT_HANDLER
+Method (TEVT, 1, NotSerialized)
+{
+       Store (ToInteger (Arg0), Local0)
+
+#ifdef DPTF_TSR0_SENSOR_ID
+       If (LEqual (Local0, DPTF_TSR0_SENSOR_ID)) {
+               Notify (^TSR0, 0x90)
+       }
+#endif
+#ifdef DPTF_TSR1_SENSOR_ID
+       If (LEqual (Local0, DPTF_TSR1_SENSOR_ID)) {
+               Notify (^TSR1, 0x90)
+       }
+#endif
+#ifdef DPTF_TSR2_SENSOR_ID
+       If (LEqual (Local0, DPTF_TSR2_SENSOR_ID)) {
+               Notify (^TSR2, 0x90)
+       }
+#endif
+#ifdef DPTF_TSR3_SENSOR_ID
+       If (LEqual (Local0, DPTF_TSR3_SENSOR_ID)) {
+               Notify (^TSR3, 0x90)
+       }
+#endif
+}
+
+/* Thermal device initialization - Disable Aux Trip Points */
+Method (TINI)
+{
+#ifdef DPTF_TSR0_SENSOR_ID
+       ^TSR0.PATD ()
+#endif
+#ifdef DPTF_TSR1_SENSOR_ID
+       ^TSR1.PATD ()
+#endif
+#ifdef DPTF_TSR2_SENSOR_ID
+       ^TSR2.PATD ()
+#endif
+#ifdef DPTF_TSR3_SENSOR_ID
+       ^TSR3.PATD ()
+#endif
+}
+
+/* Thermal Trip Points Change Event Handler */
+Method (TPET)
+{
+#ifdef DPTF_TSR0_SENSOR_ID
+       Notify (^TSR0, 0x81)
+#endif
+#ifdef DPTF_TSR1_SENSOR_ID
+       Notify (^TSR1, 0x81)
+#endif
+#ifdef DPTF_TSR2_SENSOR_ID
+       Notify (^TSR2, 0x81)
+#endif
+#ifdef DPTF_TSR3_SENSOR_ID
+       Notify (^TSR3, 0x81)
+#endif
+}
+
+/*
+ * Method to return trip temperature value depending upon the device mode.
+ * Arg0 --> Value to return when device is in tablet mode
+ * Arg1 --> Value to return when device is not in tablet mode.
+ */
+Method (DTRP, 2, Serialized)
+{
+#ifdef EC_ENABLE_MULTIPLE_DPTF_PROFILES
+       If (LEqual (\_SB.PCI0.LPCB.EC0.RCDP, One)) {
+               Return (CTOK (Arg0))
+       } Else {
+#endif
+               Return (CTOK (Arg1))
+#ifdef EC_ENABLE_MULTIPLE_DPTF_PROFILES
+       }
+#endif
+}
+
+#ifdef DPTF_TSR0_SENSOR_ID
+
+#ifndef DPTF_TSR0_TABLET_PASSIVE
+#define DPTF_TSR0_TABLET_PASSIVE DPTF_TSR0_PASSIVE
+#endif
+#ifndef DPTF_TSR0_TABLET_CRITICAL
+#define DPTF_TSR0_TABLET_CRITICAL DPTF_TSR0_CRITICAL
+#endif
+
+Device (TSR0)
+{
+       Name (_HID, EISAID ("INT3403"))
+       Name (_UID, 1)
+       Name (PTYP, 0x03)
+       Name (TMPI, DPTF_TSR0_SENSOR_ID)
+       Name (_STR, Unicode (DPTF_TSR0_SENSOR_NAME))
+       Name (GTSH, 20) /* 2 degree hysteresis */
+
+       Method (_STA)
+       {
+               If (LEqual (\DPTE, One)) {
+                       Return (0xF)
+               } Else {
+                       Return (0x0)
+               }
+       }
+
+       Method (_TMP, 0, Serialized)
+       {
+               Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI))
+       }
+
+       Method (_PSV)
+       {
+               Return (DTRP (DPTF_TSR0_TABLET_PASSIVE, DPTF_TSR0_PASSIVE))
+       }
+
+       Method (_CRT)
+       {
+               Return (DTRP (DPTF_TSR0_TABLET_CRITICAL, DPTF_TSR0_CRITICAL))
+       }
+
+       Name (PATC, 2)
+
+       /* Set Aux Trip Point */
+       Method (PAT0, 1, Serialized)
+       {
+               \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0)
+       }
+
+       /* Set Aux Trip Point */
+       Method (PAT1, 1, Serialized)
+       {
+               \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0)
+       }
+
+       /* Disable Aux Trip Point */
+       Method (PATD, 0, Serialized)
+       {
+               \_SB.PCI0.LPCB.EC0.PATD (TMPI)
+       }
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+#ifdef DPTF_TSR0_ACTIVE_AC0
+       Method (_AC0)
+       {
+               Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC0))
+       }
+#endif
+#ifdef DPTF_TSR0_ACTIVE_AC1
+       Method (_AC1)
+       {
+               Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC1))
+       }
+#endif
+#ifdef DPTF_TSR0_ACTIVE_AC2
+       Method (_AC2)
+       {
+               Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC2))
+       }
+#endif
+#ifdef DPTF_TSR0_ACTIVE_AC3
+       Method (_AC3)
+       {
+               Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC3))
+       }
+#endif
+#ifdef DPTF_TSR0_ACTIVE_AC4
+       Method (_AC4)
+       {
+               Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC4))
+       }
+#endif
+#ifdef DPTF_TSR0_ACTIVE_AC5
+       Method (_AC5)
+       {
+               Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC5))
+       }
+#endif
+#ifdef DPTF_TSR0_ACTIVE_AC6
+       Method (_AC6)
+       {
+               Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC6))
+       }
+#endif
+#endif
+}
+#endif
+
+#ifdef DPTF_TSR1_SENSOR_ID
+
+#ifndef DPTF_TSR1_TABLET_PASSIVE
+#define DPTF_TSR1_TABLET_PASSIVE DPTF_TSR1_PASSIVE
+#endif
+#ifndef DPTF_TSR1_TABLET_CRITICAL
+#define DPTF_TSR1_TABLET_CRITICAL DPTF_TSR1_CRITICAL
+#endif
+
+Device (TSR1)
+{
+       Name (_HID, EISAID ("INT3403"))
+       Name (_UID, 2)
+       Name (PTYP, 0x03)
+       Name (TMPI, DPTF_TSR1_SENSOR_ID)
+       Name (_STR, Unicode (DPTF_TSR1_SENSOR_NAME))
+       Name (GTSH, 20) /* 2 degree hysteresis */
+
+       Method (_STA)
+       {
+               If (LEqual (\DPTE, One)) {
+                       Return (0xF)
+               } Else {
+                       Return (0x0)
+               }
+       }
+
+       Method (_TMP, 0, Serialized)
+       {
+               Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI))
+       }
+
+       Method (_PSV)
+       {
+               Return (DTRP (DPTF_TSR1_TABLET_PASSIVE, DPTF_TSR1_PASSIVE))
+       }
+
+       Method (_CRT)
+       {
+               Return (DTRP (DPTF_TSR1_TABLET_CRITICAL, DPTF_TSR1_CRITICAL))
+       }
+
+       Name (PATC, 2)
+
+       /* Set Aux Trip Point */
+       Method (PAT0, 1, Serialized)
+       {
+               \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0)
+       }
+
+       /* Set Aux Trip Point */
+       Method (PAT1, 1, Serialized)
+       {
+               \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0)
+       }
+
+       /* Disable Aux Trip Point */
+       Method (PATD, 0, Serialized)
+       {
+               \_SB.PCI0.LPCB.EC0.PATD (TMPI)
+       }
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+#ifdef DPTF_TSR1_ACTIVE_AC0
+       Method (_AC0)
+       {
+               Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC0))
+       }
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC1
+       Method (_AC1)
+       {
+               Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC1))
+       }
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC2
+       Method (_AC2)
+       {
+               Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC2))
+       }
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC3
+       Method (_AC3)
+       {
+               Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC3))
+       }
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC4
+       Method (_AC4)
+       {
+               Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC4))
+       }
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC5
+       Method (_AC5)
+       {
+               Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC5))
+       }
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC6
+       Method (_AC6)
+       {
+               Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC6))
+       }
+#endif
+#endif
+}
+#endif
+
+#ifdef DPTF_TSR2_SENSOR_ID
+
+#ifndef DPTF_TSR2_TABLET_PASSIVE
+#define DPTF_TSR2_TABLET_PASSIVE DPTF_TSR2_PASSIVE
+#endif
+#ifndef DPTF_TSR2_TABLET_CRITICAL
+#define DPTF_TSR2_TABLET_CRITICAL DPTF_TSR2_CRITICAL
+#endif
+
+Device (TSR2)
+{
+       Name (_HID, EISAID ("INT3403"))
+       Name (_UID, 3)
+       Name (PTYP, 0x03)
+       Name (TMPI, DPTF_TSR2_SENSOR_ID)
+       Name (_STR, Unicode (DPTF_TSR2_SENSOR_NAME))
+       Name (GTSH, 20) /* 2 degree hysteresis */
+
+       Method (_STA)
+       {
+               If (LEqual (\DPTE, One)) {
+                       Return (0xF)
+               } Else {
+                       Return (0x0)
+               }
+       }
+
+       Method (_TMP, 0, Serialized)
+       {
+               Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI))
+       }
+
+       Method (_PSV)
+       {
+               Return (DTRP (DPTF_TSR2_TABLET_PASSIVE, DPTF_TSR2_PASSIVE))
+       }
+
+       Method (_CRT)
+       {
+               Return (DTRP (DPTF_TSR2_TABLET_CRITICAL, DPTF_TSR2_CRITICAL))
+       }
+
+       Name (PATC, 2)
+
+       /* Set Aux Trip Point */
+       Method (PAT0, 1, Serialized)
+       {
+               \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0)
+       }
+
+       /* Set Aux Trip Point */
+       Method (PAT1, 1, Serialized)
+       {
+               \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0)
+       }
+
+       /* Disable Aux Trip Point */
+       Method (PATD, 0, Serialized)
+       {
+               \_SB.PCI0.LPCB.EC0.PATD (TMPI)
+       }
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+#ifdef DPTF_TSR2_ACTIVE_AC0
+       Method (_AC0)
+       {
+               Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC0))
+       }
+#endif
+#ifdef DPTF_TSR2_ACTIVE_AC1
+       Method (_AC1)
+       {
+               Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC1))
+       }
+#endif
+#ifdef DPTF_TSR2_ACTIVE_AC2
+       Method (_AC2)
+       {
+               Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC2))
+       }
+#endif
+#ifdef DPTF_TSR2_ACTIVE_AC3
+       Method (_AC3)
+       {
+               Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC3))
+       }
+#endif
+#ifdef DPTF_TSR2_ACTIVE_AC4
+       Method (_AC4)
+       {
+               Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC4))
+       }
+#endif
+#ifdef DPTF_TSR2_ACTIVE_AC5
+       Method (_AC5)
+       {
+               Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC5))
+       }
+#endif
+#ifdef DPTF_TSR2_ACTIVE_AC6
+       Method (_AC6)
+       {
+               Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC6))
+       }
+#endif
+#endif
+}
+#endif
+
+#ifdef DPTF_TSR3_SENSOR_ID
+
+#ifndef DPTF_TSR3_TABLET_PASSIVE
+#define DPTF_TSR3_TABLET_PASSIVE DPTF_TSR3_PASSIVE
+#endif
+#ifndef DPTF_TSR3_TABLET_CRITICAL
+#define DPTF_TSR3_TABLET_CRITICAL DPTF_TSR3_CRITICAL
+#endif
+
+Device (TSR3)
+{
+       Name (_HID, EISAID ("INT3403"))
+       Name (_UID, 4)
+       Name (PTYP, 0x03)
+       Name (TMPI, DPTF_TSR3_SENSOR_ID)
+       Name (_STR, Unicode (DPTF_TSR3_SENSOR_NAME))
+       Name (GTSH, 20) /* 2 degree hysteresis */
+
+       Method (_STA)
+       {
+               If (LEqual (\DPTE, One)) {
+                       Return (0xF)
+               } Else {
+                       Return (0x0)
+               }
+       }
+
+       Method (_TMP, 0, Serialized)
+       {
+               Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI))
+       }
+
+       Method (_PSV)
+       {
+               Return (DTRP (DPTF_TSR3_TABLET_PASSIVE, DPTF_TSR3_PASSIVE))
+       }
+
+       Method (_CRT)
+       {
+               Return (DTRP (DPTF_TSR3_TABLET_CRITICAL, DPTF_TSR3_CRITICAL))
+       }
+
+       Name (PATC, 2)
+
+       /* Set Aux Trip Point */
+       Method (PAT0, 1, Serialized)
+       {
+               \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0)
+       }
+
+       /* Set Aux Trip Point */
+       Method (PAT1, 1, Serialized)
+       {
+               \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0)
+       }
+
+       /* Disable Aux Trip Point */
+       Method (PATD, 0, Serialized)
+       {
+               \_SB.PCI0.LPCB.EC0.PATD (TMPI)
+       }
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+#ifdef DPTF_TSR3_ACTIVE_AC0
+       Method (_AC0)
+       {
+               Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC0))
+       }
+#endif
+#ifdef DPTF_TSR3_ACTIVE_AC1
+       Method (_AC1)
+       {
+               Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC1))
+       }
+#endif
+#ifdef DPTF_TSR3_ACTIVE_AC2
+       Method (_AC2)
+       {
+               Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC2))
+       }
+#endif
+#ifdef DPTF_TSR3_ACTIVE_AC3
+       Method (_AC3)
+       {
+               Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC3))
+       }
+#endif
+#ifdef DPTF_TSR3_ACTIVE_AC4
+       Method (_AC4)
+       {
+               Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC4))
+       }
+#endif
+#ifdef DPTF_TSR3_ACTIVE_AC5
+       Method (_AC5)
+       {
+               Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC5))
+       }
+#endif
+#ifdef DPTF_TSR3_ACTIVE_AC6
+       Method (_AC6)
+       {
+               Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC6))
+       }
+#endif
+#endif
+}
+#endif