rockchip: Ensure memory size is available in RK3399 SPL

At present gd->ram_size is 0 in SPL, meaning that it is not possible to
enable the cache. Correct this by always populating the RAM size
correctly.

This increases code size by about 500 bytes in SPL, since it must call
the rather large rockchip_sdram_size() function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>

diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index ef9a1824b2b338862266e0abc66da816bcc1bb64..58f3745ffa5f12b7550d6ab16dc3e0334aa27d71 100644 (file)
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -3142,19 +3142,25 @@ static int rk3399_dmc_init(struct udevice *dev)
 
 static int rk3399_dmc_probe(struct udevice *dev)
 {
+       struct dram_info *priv = dev_get_priv(dev);
+
 #if defined(CONFIG_TPL_BUILD) || \
        (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
        if (rk3399_dmc_init(dev))
                return 0;
-#else
-       struct dram_info *priv = dev_get_priv(dev);
-
-       priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
-       debug("%s: pmugrf = %p\n", __func__, priv->pmugrf);
-       priv->info.base = CFG_SYS_SDRAM_BASE;
-       priv->info.size =
-               rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2);
 #endif
+       /*
+        * There is no point in checking the SDRAM size in TPL as it is not
+        * used, so avoid the code size increment.
+        */
+       if (!IS_ENABLED(CONFIG_TPL_BUILD)) {
+               priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
+               debug("%s: pmugrf = %p\n", __func__, priv->pmugrf);
+               priv->info.base = CFG_SYS_SDRAM_BASE;
+               priv->info.size = rockchip_sdram_size(
+                       (phys_addr_t)&priv->pmugrf->os_reg2);
+       }
+
        return 0;
 }