From f589f8cca64bddb59fe2409c10ab14529ab47a40 Mon Sep 17 00:00:00 2001 From: Simon Glass <sjg@chromium.org> Date: Thu, 5 May 2016 07:28:10 -0600 Subject: [PATCH] net: macb: Flush correct cache portion when sending MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit The end address of the cache flush must be cache-line-aligned since otherwise (at least on ARM926-EJS) the request is ignored. When the cache is enabled this means that packets are not sent. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Andreas BieÃmann <andreas@biessmann.org> --- drivers/net/macb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 8be62afbf9..84bae37f37 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -280,7 +280,7 @@ static int _macb_send(struct macb_device *macb, const char *name, void *packet, barrier(); macb_flush_ring_desc(macb, TX); /* Do we need check paddr and length is dcache line aligned? */ - flush_dcache_range(paddr, paddr + length); + flush_dcache_range(paddr, paddr + ALIGN(length, ARCH_DMA_MINALIGN)); macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART)); /* -- 2.39.5