From 786a08e0dd3d0505e10cc93622ce5db696c627e9 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Mon, 6 Jul 2015 16:31:33 +0800
Subject: [PATCH] x86: Move VGA option rom macros to Kconfig
Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig
and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on
HAVE_VGA_BIOS. The new names are consistent with other x86 binary
blob options like HAVE_FSP/FSP_FILE/FSP_ADDR.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
---
Makefile | 4 ++--
arch/x86/Kconfig | 22 ++++++++++++++++++++++
configs/chromebook_link_defconfig | 1 +
configs/chromebox_panther_defconfig | 1 +
configs/minnowmax_defconfig | 1 +
doc/README.x86 | 2 +-
drivers/pci/pci_rom.c | 4 ++--
include/configs/minnowmax.h | 3 ---
include/configs/x86-chromebook.h | 3 ---
9 files changed, 30 insertions(+), 11 deletions(-)
diff --git a/Makefile b/Makefile
index a7dce06408..b6f83a5530 100644
--- a/Makefile
+++ b/Makefile
@@ -1035,8 +1035,8 @@ ifneq ($(CONFIG_HAVE_CMC),)
IFDTOOL_FLAGS += -w $(CONFIG_CMC_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_CMC_FILE)
endif
-ifneq ($(CONFIG_X86_OPTION_ROM_ADDR),)
-IFDTOOL_FLAGS += -w $(CONFIG_X86_OPTION_ROM_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_X86_OPTION_ROM_FILE)
+ifneq ($(CONFIG_HAVE_VGA_BIOS),)
+IFDTOOL_FLAGS += -w $(CONFIG_VGA_BIOS_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_VGA_BIOS_FILE)
endif
quiet_cmd_ifdtool = IFDTOOL $@
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index b52a80e1c2..8381a3be6e 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -287,6 +287,28 @@ config TSC_FREQ_IN_MHZ
help
The running frequency in MHz of Time-Stamp Counter (TSC).
+config HAVE_VGA_BIOS
+ bool "Add a VGA BIOS image"
+ help
+ Select this option if you have a VGA BIOS image that you would
+ like to add to your ROM.
+
+config VGA_BIOS_FILE
+ string "VGA BIOS image filename"
+ depends on HAVE_VGA_BIOS
+ default "vga.bin"
+ help
+ The filename of the VGA BIOS image in the board directory.
+
+config VGA_BIOS_ADDR
+ hex "VGA BIOS image location"
+ depends on HAVE_VGA_BIOS
+ default 0xfff90000
+ help
+ The location of VGA BIOS image in the SPI flash. For example, base
+ address of 0xfff90000 indicates that the image will be put at offset
+ 0x90000 from the beginning of a 1MB flash device.
+
menu "System tables"
config GENERATE_PIRQ_TABLE
diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig
index 018fe91e89..9931d65dc2 100644
--- a/configs/chromebook_link_defconfig
+++ b/configs/chromebook_link_defconfig
@@ -3,6 +3,7 @@ CONFIG_VENDOR_GOOGLE=y
CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
CONFIG_TARGET_CHROMEBOOK_LINK=y
CONFIG_HAVE_MRC=y
+CONFIG_HAVE_VGA_BIOS=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig
index 2ac23ed97f..b3a5f28be9 100644
--- a/configs/chromebox_panther_defconfig
+++ b/configs/chromebox_panther_defconfig
@@ -3,6 +3,7 @@ CONFIG_VENDOR_GOOGLE=y
CONFIG_DEFAULT_DEVICE_TREE="chromebox_panther"
CONFIG_TARGET_CHROMEBOX_PANTHER=y
CONFIG_HAVE_MRC=y
+CONFIG_HAVE_VGA_BIOS=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig
index e0a9216d89..b5788052c7 100644
--- a/configs/minnowmax_defconfig
+++ b/configs/minnowmax_defconfig
@@ -3,6 +3,7 @@ CONFIG_VENDOR_INTEL=y
CONFIG_DEFAULT_DEVICE_TREE="minnowmax"
CONFIG_TARGET_MINNOWMAX=y
CONFIG_HAVE_INTEL_ME=y
+CONFIG_HAVE_VGA_BIOS=y
CONFIG_SMP=y
CONFIG_GENERATE_SFI_TABLE=y
CONFIG_CMD_CPU=y
diff --git a/doc/README.x86 b/doc/README.x86
index 49d6e83046..7f3914fee1 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -79,7 +79,7 @@ Find the following files:
* ./northbridge/intel/sandybridge/systemagent-r6.bin
The 3rd one should be renamed to mrc.bin.
-As for the video ROM, you can get it here [3].
+As for the video ROM, you can get it here [3] and rename it to vga.bin.
Make sure all these binary blobs are put in the board directory.
Now you can build U-Boot and obtain u-boot.rom:
diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
index 0a644a9bc5..dd7fd953ca 100644
--- a/drivers/pci/pci_rom.c
+++ b/drivers/pci/pci_rom.c
@@ -79,8 +79,8 @@ static int pci_rom_probe(pci_dev_t dev, uint class,
if (vendev != mapped_vendev)
debug("Device ID mapped to %#08x\n", mapped_vendev);
-#ifdef CONFIG_X86_OPTION_ROM_ADDR
- rom_address = CONFIG_X86_OPTION_ROM_ADDR;
+#ifdef CONFIG_VGA_BIOS_ADDR
+ rom_address = CONFIG_VGA_BIOS_ADDR;
#else
if (pciauto_setup_rom(pci_bus_to_hose(PCI_BUS(dev)), dev)) {
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index 547765d137..8ee84a604c 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -52,9 +52,6 @@
#undef CONFIG_USB_MAX_CONTROLLER_COUNT
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_X86_OPTION_ROM_FILE vga.bin
-#define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000
-
#define VIDEO_IO_OFFSET 0
#define CONFIG_X86EMU_RAW_IO
#define CONFIG_VGA_AS_SINGLE_DEVICE
diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h
index e0e7fca9f8..408cbb1957 100644
--- a/include/configs/x86-chromebook.h
+++ b/include/configs/x86-chromebook.h
@@ -26,9 +26,6 @@
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}, \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI}
-#define CONFIG_X86_OPTION_ROM_FILE pci8086,0166.bin
-#define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000
-
#define CONFIG_PCI_MEM_BUS 0xe0000000
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE 0x10000000
--
2.39.5