From 1bf9e01b8f82c442029607ab953c6a0d099c7d68 Mon Sep 17 00:00:00 2001
From: Milan Obuch <u-boot@dino.sk>
Date: Sun, 19 Jan 2020 22:32:19 -0300
Subject: [PATCH] arm: zynq: zybo z7: fix SPL uart init bitrate
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The board uses 100 MHz clock for UART bitrate generator,
but is configured as 50 MHz on defconfig.

This produces wrong console output.
The first message, "Debug uart enabled" is received as:
"ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½b"

Fix the issue by configuring the correct clock for the
UART baudrate generator

Signed-off-by: Milan Obuch <u-boot@dino.sk>
Signed-off-by: Luis Araneda <luaraneda@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
 configs/zynq_zybo_z7_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/zynq_zybo_z7_defconfig b/configs/zynq_zybo_z7_defconfig
index 12e1367e97..1dee757062 100644
--- a/configs/zynq_zybo_z7_defconfig
+++ b/configs/zynq_zybo_z7_defconfig
@@ -6,7 +6,7 @@ CONFIG_DM_GPIO=y
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_SPL=y
 CONFIG_DEBUG_UART_BASE=0xe0001000
-CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_DEBUG_UART_CLOCK=100000000
 CONFIG_DEBUG_UART=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
-- 
2.39.5