From: Jonas Karlman Date: Mon, 22 Apr 2024 06:28:39 +0000 (+0000) Subject: clk: rockchip: rk3588: Add REF_CLK_USB3OTGx support X-Git-Url: http://git.dujemihanovic.xyz/%22http:/www.sics.se/static/%7B%7B?a=commitdiff_plain;h=80274d1b642bbe2fc6f58552fe3d76bfe65ba084;p=u-boot.git clk: rockchip: rk3588: Add REF_CLK_USB3OTGx support The REF_CLK_USB3OTGx clocks is used as reference clock for USB3 block. Add simple support to get rate of REF_CLK_USB3OTGx clocks to fix reference clock period configuration. Signed-off-by: Jonas Karlman Reviewed-by: Quentin Schulz Acked-by: Sean Anderson Reviewed-by: Kever Yang --- diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c index 8f33843179..4c611a3904 100644 --- a/drivers/clk/rockchip/clk_rk3588.c +++ b/drivers/clk/rockchip/clk_rk3588.c @@ -1569,6 +1569,9 @@ static ulong rk3588_clk_get_rate(struct clk *clk) case DCLK_DECOM: rate = rk3588_mmc_get_clk(priv, clk->id); break; + case REF_CLK_USB3OTG0: + case REF_CLK_USB3OTG1: + case REF_CLK_USB3OTG2: case TMCLK_EMMC: case TCLK_WDT0: rate = OSC_HZ; @@ -1734,6 +1737,9 @@ static ulong rk3588_clk_set_rate(struct clk *clk, ulong rate) case DCLK_DECOM: ret = rk3588_mmc_set_clk(priv, clk->id, rate); break; + case REF_CLK_USB3OTG0: + case REF_CLK_USB3OTG1: + case REF_CLK_USB3OTG2: case TMCLK_EMMC: case TCLK_WDT0: ret = OSC_HZ;