From: Stefan Roese <sr@denx.de>
Date: Sun, 18 Nov 2007 13:44:44 +0000 (+0100)
Subject: ppc4xx: Correct 405EX PCIe UTL register mapping
X-Git-Tag: v2025.01-rc5-pxa1908~22626^2~70
X-Git-Url: http://git.dujemihanovic.xyz/%22http:/www.sics.se/static/%7B%7B?a=commitdiff_plain;h=653811a3c2b35856bf12e196dcc8c4694e28e420;p=u-boot.git

ppc4xx: Correct 405EX PCIe UTL register mapping

Map 4k mem space for UTL registers for each port.

Signed-off-by: Stefan Roese <sr@denx.de>
---

diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c
index cafd933890..3af9862bff 100644
--- a/cpu/ppc4xx/4xx_pcie.c
+++ b/cpu/ppc4xx/4xx_pcie.c
@@ -412,14 +412,14 @@ static void ppc4xx_setup_utl(u32 port)
 	case 0:
 		mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x00000000);
 		mtdcr(DCRN_PEGPL_REGBAL(PCIE0), CFG_PCIE0_UTLBASE);
-		mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0xfffffc01); /* 4k region, valid */
+		mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* 4k region, valid */
 		mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0);
 		break;
 
 	case 1:
 		mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x00000000);
 		mtdcr(DCRN_PEGPL_REGBAL(PCIE1), CFG_PCIE1_UTLBASE);
-		mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0xfffffc01); /* 4k region, valid */
+		mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* 4k region, valid */
 		mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0);
 
 		break;
@@ -554,7 +554,7 @@ int __ppc4xx_init_pcie_port_hw(int port, int rootport)
 #endif /* CONFIG_405EX */
 
 int ppc4xx_init_pcie_port_hw(int port, int rootport)
-	__attribute__((weak, alias("__ppc4xx_init_pcie_port_hw")));
+__attribute__((weak, alias("__ppc4xx_init_pcie_port_hw")));
 
 /*
  * We map PCI Express configuration access into the 512MB regions