From: Tom Rini Date: Wed, 5 Apr 2023 23:48:55 +0000 (-0400) Subject: armv7: Use isb/dsb directly in start.S X-Git-Url: http://git.dujemihanovic.xyz/%22http:/www.sics.se/static/%7B%7B%20.Permalink%20%7D%7D?a=commitdiff_plain;h=b5fc9f99d0d5324b6159b3a1da7bb679cf5fc901;p=u-boot.git armv7: Use isb/dsb directly in start.S Toolchains which do not directly support using "isb" and "dsb" directly are no longer functionally supported in U-Boot. Furthermore, clang has for a long time warned about using the alternate form that we were. Update the code. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 7d7aac021e..69e281b086 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -134,8 +134,8 @@ ENTRY(c_runtime_cpu_setup) */ #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) mcr p15, 0, r0, c7, c5, 0 @ invalidate icache - mcr p15, 0, r0, c7, c10, 4 @ DSB - mcr p15, 0, r0, c7, c5, 4 @ ISB + dsb + isb #endif bx lr @@ -188,8 +188,8 @@ ENTRY(cpu_init_cp15) mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs mcr p15, 0, r0, c7, c5, 0 @ invalidate icache mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array - mcr p15, 0, r0, c7, c10, 4 @ DSB - mcr p15, 0, r0, c7, c5, 4 @ ISB + dsb + isb /* * disable MMU stuff and caches