Dave Gerlach [Tue, 16 May 2023 04:54:37 +0000 (10:24 +0530)]
arm: mach-k3: Increase SYSFW max image size
When booting with HS silicon, the system firmware image is 278270, which
is slightly larger than currently allocated amount.
This can cause unexpected behavior if this overlap interferes with other
things in memory, so increase this with a slightly margin added as well
to avoid any boot issues that can appear after system firmware gets
loaded.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com> Reviewed-by: Dhruva Gole <d-gole@ti.com>
Manorit Chawdhry [Tue, 16 May 2023 04:54:36 +0000 (10:24 +0530)]
Kconfig: j721e: Change K3_MCU_SCRATCHPAD_BASE to non firewalled region
In non-combined boot flow for K3, all the firewalls are locked by default
until sysfw comes up. Rom configures some of the firewall for its usage
along with the SRAM for R5 but the PSRAM region is still locked.
The K3 MCU Scratchpad for j721e was set to a PSRAM region triggering the
firewall exception before sysfw came up. The exception started happening
after adding multi dtb support that accesses the scratchpad for reading
EEPROM contents.
The commit changes R5 MCU scratchpad for j721e to an SRAM region.
Manorit Chawdhry [Tue, 16 May 2023 04:54:35 +0000 (10:24 +0530)]
configs: j721e: Merge the HS and non-HS defconfigs
K3 devices have runtime type board detection. Make the default defconfig
include the secure configuration. Then remove the HS specific config.
Non-HS devices will continue to boot due to runtime device type detection.
If TI_SECURE_DEV_PKG is not set the build will emit warnings, for non-HS
devices these can be ignored.
Reviewed-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Acked-by: Andrew Davis <afd@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Andrew Davis [Tue, 16 May 2023 04:54:34 +0000 (10:24 +0530)]
arm: k3: config.mk: Add missing dependencies on tispl.bin HS
When building for secure devices using non-buildman based image generation
the signed tispl.bin file is called tispl.bin_HS. Also build the unsigned
tispl.bin file as expected.
Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Peng Fan [Fri, 28 Apr 2023 04:08:46 +0000 (12:08 +0800)]
imx9: imx93_evk: update ddr timing file
Update DDR timing file generated by DDR Config Tool
1. Dynamic refresh rate is set by default
2. The 3rd freq will be 625MTS based on power and performance better than 100MTS.
Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Fri, 28 Apr 2023 04:08:45 +0000 (12:08 +0800)]
imx9: Calculate DDR size from DDRC setting
To avoid using static setting for ECC enabled DDR size, switch
to calculate DDR size from DDRC setting
Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Jacky Bai [Fri, 28 Apr 2023 04:08:43 +0000 (12:08 +0800)]
ddr: imx93: update the ddr init to support mult setpoints
Update the DDR init flow for multi-setpoint support on i.MX93. A new
fsp_cfg struct need to be added in the timing file to store the diff
part of the DDRC and DRAM MR register for each setpoint.
Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Jacky Bai [Fri, 28 Apr 2023 04:08:41 +0000 (12:08 +0800)]
ddr: imx9: Change the saved ddr data base to 0x2051c000
change the ddr saved info to the last 16KB of the OCRAM.
Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Fri, 28 Apr 2023 04:08:39 +0000 (12:08 +0800)]
ddr: imx9: Add workaround for DDRPHY rank-to-rank errata
According to DDRPHY errata, the Rank-to-Rank Spacing and tphy_rdcsgap
specification does not include the Critical Delay Difference (CDD) to
properly define the required rank-to-rank read command spacing after
executing PHY training firmware.
Following the errata workaround, at the end of data training, we get
all CDD values through the MessageBlock, then re-configure the DDRC
timing of WWT/WRT/RRT/RWT with comparing MAX CDD values.
Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Fri, 28 Apr 2023 04:08:36 +0000 (12:08 +0800)]
imx9: allow to bootaux Mcore with input address
Currently bootaux only supports to boot M33 core from TCM. Since ATF
has changed to use x2 parameter for M33 image address, update the
bootaux command to use input address, so we can support boot from
any possilbe address like TCM, DDR, Flexspi NOR.
Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Fri, 28 Apr 2023 04:08:35 +0000 (12:08 +0800)]
imx9: imx93_evk: add low drive mode support on 11x11 EVK
Add a static u-boot config for i.MX93 low drive mode support. When
low drive mode is enabled, VDD_SOC is set to 0.75V. Bus clocks,
A55 core clock (900Mhz), DDR clock (1866MTS), and some peripherals
clocks (USDHC/FLEXSPI/PDM/DISP_PIX/CAM_PIX) must decrease to meet
max frequencies in low drive mode.
Also set standby voltage for buck1
Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Fri, 28 Apr 2023 04:08:32 +0000 (12:08 +0800)]
imx9: add i.MX93 variants support
According to datasheet, iMX93 has fused parts with CORE1 or NPU or
both disabled. So update code to support it, the kernel device tree
runtime update will be added in future patches.
Peng Fan [Fri, 28 Apr 2023 04:08:31 +0000 (12:08 +0800)]
imx9: clock: config arm alt root to 500mhz
Config the A55 alt root clock to 500MHz(LD mode frequency)
by default. Normally, this clock root is only used as an
intermediate clock soure for A55 core/dsu when change the
ARM PLL frequency.
Peng Fan [Fri, 28 Apr 2023 04:08:20 +0000 (12:08 +0800)]
imx9: cut off OPTEE memory region from U-Boot
OPTEE memory region is set secure access only in ATF with configuration
to TRDC, and need to remove it from U-Boot, otherwise U-Boot and Kernel
may crash when accessing the memory
Peng Fan [Fri, 28 Apr 2023 04:08:09 +0000 (12:08 +0800)]
imx: move imx8 sci header file to include/firmware/imx
Move imx8 sci header file to include/firmware/imx, then we could
use build macro to reuse some i.MX8 drivers for i.MX9, such as
drivers/cpu/imx8_cpu.c.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Stefano Babic <sbabic@denx.de>
Ye Li [Fri, 28 Apr 2023 04:08:07 +0000 (12:08 +0800)]
thermal: imx_tmu: Update TMU driver to support iMX93
The TMU used on iMX93 is IP revision 2.1 which is different with previous
revision used on iMX8MQ. So add a new FLAG V4 for this revision to
distinguish the operations.
Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
CPU: Freescale i.MX7D rev1.0 1000 MHz (running at 792 MHz)
CPU: Commercial temperature grade (0C to 95C) at 35C
Reset cause: POR
Model: Freescale i.MX7 SabreSD Board
Board: i.MX7D SABRESD in non-secure mode
DRAM: 1 GiB
Core: 100 devices, 19 uclasses, devicetree: separate
PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x10
MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... Card did not respond to voltage
select! : -110
*** Warning - No block device, using default environment
The reason of the problem, as explained by Ye Li:
"When UHS is enabled in defconfig, the usdhc1 node in imx7d-sdb.dts does
not configure pad for VSELECT, also the data pad should be set to
100Mhz/200Mhz pin states."
Apply these changes into u-boot.dtsi for now. When these changes
reach the Linux mainline imx7d-sdb, they can be dropped from u-boot.dtsi.
This fixes UHS mode on the imx7d-sdb board.
Suggested-by: Ye Li <ye.li@nxp.com> Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Marek Vasut [Tue, 4 Apr 2023 19:25:10 +0000 (21:25 +0200)]
thermal: imx_tmu: Move architecture code into driver
Stop polluting the architecture directory with driver specific code,
move it into driver where it should be. Split the code slightly so
the MX8MM/MX8MN fuse readout and programming and MX8MP fuse readout
and programming are in their separate functions, and called in case
of matching SoC.
Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
Fedor Ross [Thu, 14 Apr 2022 16:36:23 +0000 (18:36 +0200)]
ARM: imx: Fix parsing of ROM log event IDs on iMX8M
It seems like the ROM log events for the iMX8M are not fully covered by
AN12853 i.MX ROMs Log Events, Rev. 0, May 2020. On iMX8M the ROM event
ID 0x82 seems to use parameter0 which stops the parsing because the end
of list is detected too early.
This patch adds ROM event ID 0x82 and skips the next word if ID 0x82 is
parsed.
Fixes: a5ee05cf71 ("ARM: imx: Pick correct eMMC boot partition from ROM log") Signed-off-by: Fedor Ross <fedor.ross@ifm.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tom Rini [Fri, 19 May 2023 14:13:33 +0000 (10:13 -0400)]
Merge tag 'u-boot-rockchip-20230519' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
rk3588 driver:
- Sync the reset driver with kernel code;
- Enable pcie controller and phy support;
- Enable USB controller and phy support;
Board level dts and config update:
- boost eMMC performance for some of rk3399 boards;
- boot from SPI NOR flash for rk356x boards;
- Other board level updates;
Jonas Karlman [Thu, 18 May 2023 15:39:30 +0000 (15:39 +0000)]
rockchip: rk3588-rock-5b: Enable boot from SPI NOR flash
Add sfc and flash node to device tree and config options to enable
support for booting from SPI NOR flash on Radxa ROCK 5 Model B.
Similar to RK3568 the BootRom in RK3588 can read all data and look for
idbloader at 0x8000, same as on SD and eMMC.
Use the rksd format and modify the mkimage offset to generate a bootable
u-boot-rockchip-spi.bin that can be written to 0x0 of SPI NOR flash. The
FIT image is loaded from 0x60000.
=> sf probe
SF: Detected mx25u12835f with page size 256 Bytes, erase size 4 KiB, total 16 MiB
=> load mmc 1:1 10000000 u-boot-rockchip-spi.bin 1492992 bytes read in 129 ms (11 MiB/s)
The BROM_BOOTSOURCE_ID value read back when booting from SPI flash does
not match the expected value of 3 (SPINOR) used by other SoCs. Instead a
value of 6 is read back, add a new enum value to handle this new
bootsource id.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com>
Wadim Egorov [Tue, 13 Dec 2022 10:38:09 +0000 (11:38 +0100)]
configs: phycore-rk3288: Enable CONFIG_LTO
The phycore-rk3288 SPL binary is reaching the limits of 32KB very often.
Enable CONFIG_LTO to reduce the size of the SPL and make the board more
future proof for changes increasing the SPL size.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Wed, 17 May 2023 18:26:38 +0000 (18:26 +0000)]
rockchip: rk3588-evb: Update defconfig
Update defconfig for rk3588-evb with new defaults.
Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM.
Extend SPL_MAX_SIZE to 0x40000, SPL is loaded to 0x0 and TF-A is loaded
to 0x40000, use the space in between as SPL_MAX_SIZE.
Add config options to include useful gpio and regulator cmd.
Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is
set based on cpuid read from OTP.
Remove CONFIG_DEBUG_UART_ANNOUNCE=y to remove debug messages.
Add CONFIG_SYS_NS16550_MEM32=y to use 32bit access of serial register.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Wed, 17 May 2023 18:26:35 +0000 (18:26 +0000)]
rockchip: rk3568-rock-3a: Enable boot from SPI NOR flash
Add sfc and flash node to device tree and config options to enable
support for booting from SPI NOR flash on Radxa ROCK 3 Model A.
Unlike prior generation SoCs the BootRom in RK3568 can read all data and
look for idbloader at 0x8000, same as on SD and eMMC.
Use the rksd format and modify the mkimage offset to generate a bootable
u-boot-rockchip-spi.bin that can be written to 0x0 of SPI NOR flash. The
FIT image is loaded from 0x60000.
=> sf probe
SF: Detected mx25u12835f with page size 256 Bytes, erase size 4 KiB, total 16 MiB
=> load mmc 1:1 10000000 u-boot-rockchip-spi.bin 1384448 bytes read in 119 ms (11.1 MiB/s)
Jonas Karlman [Wed, 17 May 2023 18:26:34 +0000 (18:26 +0000)]
rockchip: rk3568-rock-3a: Update defconfig
Update defconfig for rk3568-rock-3a with new defaults.
Remove the SPL_ROCKCHIP_BACK_TO_BROM=y option, SPL is expected to load
next stage from a FIT image and then jump to next stage not back to
BootRom.
Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM.
Extend SPL_MAX_SIZE to 0x40000, SPL is loaded to 0x0 and TF-A is loaded
to 0x40000, use the space in between as SPL_MAX_SIZE.
Add config option to include useful gpio cmd.
Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is
set based on cpuid read from OTP.
Filter out assigned-clock props with CONFIG_OF_SPL_REMOVE_PROPS,
U-Boot proper will read and configure assigned-clock props.
Remove the CONFIG_SPL_PMIC_RK8XX=y option, the pmic is not used in SPL.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Wed, 17 May 2023 18:26:32 +0000 (18:26 +0000)]
rockchip: rk3568-evb: Update defconfig
Update defconfig for rk3568-evb with new defaults.
Remove the SPL_ROCKCHIP_BACK_TO_BROM=y option, SPL is expected to load
next stage from a FIT image and then jump to next stage not back to
BootRom.
Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM.
Extend SPL_MAX_SIZE to 0x40000, SPL is loaded to 0x0 and TF-A is loaded
to 0x40000, use the space in between as SPL_MAX_SIZE.
Add config options to include useful gpio, i2c, pmic and regulator cmd.
Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is
set based on cpuid read from OTP.
Filter out assigned-clock props with CONFIG_OF_SPL_REMOVE_PROPS,
U-Boot proper will read and configure assigned-clock props.
Add config options to enable support for the RK809 PMIC.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Wed, 17 May 2023 18:26:30 +0000 (18:26 +0000)]
rockchip: rk3566-radxa-cm3-io: Update defconfig
Update defconfig for rk3566-radxa-cm3-io with new defaults. Also add
missing supported mmc modes to sdhci node.
Remove the SPL_ROCKCHIP_BACK_TO_BROM=y option, SPL is expected to load
next stage from a FIT image and then jump to next stage not back to
BootRom.
Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM.
Extend SPL_MAX_SIZE to 0x40000, SPL is loaded to 0x0 and TF-A is loaded
to 0x40000, use the space in between as SPL_MAX_SIZE.
Add config option to include useful gpio cmd.
Remove the CONFIG_NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is
set based on cpuid read from OTP.
Filter out assigned-clock props with CONFIG_OF_SPL_REMOVE_PROPS,
U-Boot proper will read and configure assigned-clock props.
Add CONFIG_SYS_NS16550_MEM32=y to use 32bit access of serial register.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
ARM: dts: rockchip: rock5b: enable pcie2x1l2 and associated combphy
Enable the PCIe 2x1l 2 device and associated combphy.
On this bus, the Rock5B has an Ethernet transceiver connected.
Signed-off-by: Christopher Obbard <chris.obbard@collabora.com>
[eugen.hristev@collabora.com: minor tweaks] Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
[jonas@kwiboo.se: add PCIe pins] Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Joseph Chen [Wed, 17 May 2023 10:01:00 +0000 (13:01 +0300)]
ARM: dts: rockchip: rk3588s-u-boot: add pcie2x1l2 with PHY
Add the node for PCIe 2x1l 2 device together with the corresponding
combphy.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
[eugen.hristev@collabora.com: moved to -u-boot.dtsi, minor
adaptations] Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
[jonas@kwiboo.se: adapt to kernel node] Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Enable CONFIG_ROCKCHIP_SPI_IMAGE to build u-boot-rockchip-spi.bin.
Define CONFIG_SYS_SPI_U_BOOT_OFFS to write u-boot.itb at the expected
offset. Enable CONFIG_LTO to reduce size of SPL so that the mkimage
output fit before the 0x60000 offset in u-boot-rockchip-spi.bin.
=> sf probe
SF: Detected gd25q128 with page size 256 Bytes, erase size 4 KiB, total 16 MiB
=> load mmc 1:1 10000000 u-boot-rockchip-spi.bin 1442304 bytes read in 27 ms (50.9 MiB/s)
=> sf update $fileaddr 0 $filesize
device 0 offset 0x0, size 0x160200 1421824 bytes written, 20480 bytes skipped in 9.501s, speed 155432 B/s
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sat, 6 May 2023 17:41:11 +0000 (17:41 +0000)]
mmc: rockchip_sdhci: Disable DMA mode using a device tree property
Loading part of TF-A into SRAM from eMMC using DMA fails on RK3399
similar to other Rockchip SoCs. Checksum validation fails with:
## Checking hash(es) for Image atf-2 ... sha256 error!
Bad hash value for 'hash' hash node in 'atf-2' image node
spl_load_simple_fit: can't load image loadables index 1 (ret = -1)
mmc_load_image_raw_sector: mmc block read error
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
Add a device tree property, u-boot,spl-fifo-mode, to control when the
rockchip_sdhci driver should disable the use of DMA and fallback on PIO
mode. Same device tree property is used by the rockchip_dw_mmc driver.
In commit 2cc6cde647e2 ("mmc: rockchip_sdhci: Limit number of blocks
read in a single command") the DMA mode was disabled using a CONFIG
option on RK3588. Revert that and instead disable DMA using the device
tree property for all RK3588 boards, also apply similar workaround for
all RK3399 boards.
Fixes: 2cc6cde647e2 ("mmc: rockchip_sdhci: Limit number of blocks read in a single command") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Quentin Schulz <foss+uboot@0leil.net> # RK3399 Puma, RK3588 Tiger
Jonas Karlman [Sat, 6 May 2023 17:41:09 +0000 (17:41 +0000)]
mmc: rockchip_sdhci: Skip blocks read workaround on RK3399
The workaround to limit number of blocks to read in a single command
should only be applied to RK3568 and RK3588. Change to be more strict
when to apply the workaround.
Fixes: 2cc6cde647e2 ("mmc: rockchip_sdhci: Limit number of blocks read in a single command") Suggested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Quentin Schulz <foss+uboot@0leil.net> # RK3399 Puma, RK3588 Tiger
Jon Lin [Thu, 27 Apr 2023 07:35:35 +0000 (10:35 +0300)]
phy: rockchip: naneng-combphy: Support rk3588
Add support for rk3588 phy variant.
The PHY clock is fixed at 100MHz.
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
[kever.yang@rock-chips.com: update pcie pll parameters] Co-developed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
[eugen.hristev@collabora.com: squashed, tidy up] Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jon Lin [Thu, 27 Apr 2023 07:35:33 +0000 (10:35 +0300)]
pci: pcie_dw_rockchip: Support max_link_speed dts property
Add support for max_link_speed specified in the PCI DT binding.
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
[eugen.hristev@collabora.com: port to latest API, set default correctly,
align to 80 chars] Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
[jonas@kwiboo.se: switch to dev_read_u32_default] Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Eugen Hristev [Mon, 15 May 2023 10:55:04 +0000 (13:55 +0300)]
reset: rockchip: implement rk3588 lookup table
The current DT bindings for the rk3588 clock use a different ID than the
one that is supposed to be written to the hardware registers.
Thus, we cannot use directly the id provided in the phandle, but rather
use a lookup table to correctly setup the hardware.
This approach has been implemented already in Linux, by commit : f1c506d152ff ("clk: rockchip: add clock controller for the RK3588")
Hence, implement a similar approach using the lookup table, and adapt
the existing reset driver to work with SoCs using lookup table.
The file rst-rk3588.c has been copied as much as possible from Linux.
Adapt the clk rk3588 driver as well to bind the reset driver with the
lookup table.
Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Jonas Karlman [Mon, 15 May 2023 09:59:50 +0000 (12:59 +0300)]
phy: Keep balance of counts when ops is missing
Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Fixes: 226fce6108fe ("phy: Track power-on and init counts in uclass") Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Eugen Hristev [Mon, 15 May 2023 09:59:49 +0000 (12:59 +0300)]
phy: rockchip-inno-usb2: add initial support for rk3588 PHY
Add initial support for the rk3588 PHY variant.
The lookup for the host-port reg inside the struct now does a do {} while()
instead of a while() {} in order to allow a first check for reg == 0.
Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Co-developed-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Eugen Hristev [Mon, 15 May 2023 09:59:48 +0000 (12:59 +0300)]
phy: remove phy-supply related code
phy-supply is now handled at uclass level. Remove it from the drivers that
implement it at the driver level.
Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Suggested-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Eugen Hristev [Mon, 15 May 2023 09:59:47 +0000 (12:59 +0300)]
phy: add support for phy-supply
Some phys require a phy-supply property that is a phandle to a regulator
that needs to be enabled for phy operations.
Implement basic supply lookup, enable and disabling, if DM_REGULATOR is
available.
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
[jonas@kwiboo.se:
use regulator_set_enable_if_allowed and disable if power_on ops fails] Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Eugen Hristev [Mon, 15 May 2023 09:59:45 +0000 (12:59 +0300)]
ARM: dts: rockchip: rk3588-rock-5b-u-boot: add USB 2.0 host
Add USB 2.0 host nodes and PHYs.
Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Co-developed-by: William Wu <william.wu@rock-chips.com> Signed-off-by: William Wu <william.wu@rock-chips.com> Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Tom Rini [Tue, 16 May 2023 15:23:30 +0000 (11:23 -0400)]
Merge tag 'efi-2023-07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request efi-2023-07-rc3
Documentation:
* update the description of signature algorithms
UEFI:
* fix unaligned access to GUID in HII database protocol
* fix launching EFI binaries loaded via semihosting
* fix filling of file path in loaded image protocol for non-block devices
Tom Rini [Tue, 16 May 2023 15:16:42 +0000 (11:16 -0400)]
Merge branch '2023-05-15-assorted-bugfixes'
- Merge in a long-standing fix for some exynos platforms, correct a
Kconfig description, fix some env issues, fix an issue in
devfdt_get_addr_size_index_ptr and look for "panel-timings" not
"panel-timing" per upstream binding.
drivers: core: ofnode: fix typo in panel timing decode
In case where a single timing resolution is implemented in the
device-tree, the property is named "panel-timing", as specify
in Linux kernel binding file:
# Display Timings
panel-timing:
description:
Most display panels are restricted to a single resolution and
require specific display timings. The panel-timing subnode expresses those
timings.
$ref: panel-timing.yaml#
display-timings:
description:
Some display panels support several resolutions with different timings.
The display-timings bindings supports specifying several timings and
optionally specifying which is the native mode.
$ref: display-timings.yaml#
Christophe Leroy [Thu, 11 May 2023 06:16:49 +0000 (08:16 +0200)]
envtools lack extra settings since commit 86b9c3e4e4 ("env: Allow U-Boot scripts to be placed in
After converting my targets from CFG_EXTRA_ENV_SETTINGS to
CONFIG_EXTRA_ENV_TEXT as suggested by Tom, I discovered that
fw_setenv doesn't set the entire defaut environment anymore.
I tried to fix it with the below patch, but it fails qemu-x86 CI test,
see https://source.denx.de/u-boot/custodians/u-boot-mpc8xx/-/pipelines/16326
That's the only CI test that fails AFAICS.
Could you help with a solution ? This needs to be fixed.
After converting some targets from CFG_EXTRA_ENV_SETTINGS to
CONFIG_EXTRA_ENV_TEXT, default environment embedded in
fw_env tool missed all extra settings.
Commit 86b9c3e4e4 ("env: Allow U-Boot scripts to be placed in
a .env file") restricted the inclusion of the content of that
file to builds without USE_HOSTCC.
But as mentionned in commit 79fc0c5f49 ("tools/env: cross-compile
fw_printenv without setting HOSTCC"), HOSTCC and USE_HOSTCC are
kept for code re-use.
Remove the restricting so that settings included in a .env
file are also added to fw_env tool.
Fixes: 86b9c3e4e4 ("env: Allow U-Boot scripts to be placed in a .env file") Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Commit 4a3ea75de4c5 ("Revert "mmc: sdhci: set to INT_DATA_END when
there are data"") reverted the alternative fix that was added for
Exynos 4 devices, causing an error when trying to boot from an sdcard:
<...>
Loading Environment from MMC... sdhci_send_command: Timeout for status update!
mmc fail to send stop cmd
<...>
Re-add the quirk to allow booting from sdcards again.
projects / u-boot.git / log