From: Nikhil M Jain <n-jain1@ti.com>
Date: Tue, 18 Jul 2023 08:57:35 +0000 (+0530)
Subject: doc: board: ti: am62x_sk: Add A53 SPL DDR layout
X-Git-Tag: v2025.01-rc5-pxa1908~929^2~1
X-Git-Url: http://git.dujemihanovic.xyz/%22http:/kyber.dk/phpMyBuilder/static/%7B%7B%20%28.OutputFormats.Get?a=commitdiff_plain;h=a72532fa194ed31b559bdd8b287854df0a4903f8;p=u-boot.git

doc: board: ti: am62x_sk: Add A53 SPL DDR layout

To understand usage of DDR in A53 SPL stage, add a table showing region
and space used by major components of SPL.

Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
---

diff --git a/doc/board/ti/am62x_sk.rst b/doc/board/ti/am62x_sk.rst
index 27d7b527c6..8642bdf16d 100644
--- a/doc/board/ti/am62x_sk.rst
+++ b/doc/board/ti/am62x_sk.rst
@@ -230,6 +230,63 @@ Image formats:
                 | +-------------------+ |
                 +-----------------------+
 
+A53 SPL DDR Memory Layout
+-------------------------
+
+This provides an overview memory usage in A53 SPL stage.
+
+.. list-table::
+   :widths: 16 16 16
+   :header-rows: 1
+
+   * - Region
+     - Start Address
+     - End Address
+
+   * - EMPTY
+     - 0x80000000
+     - 0x80080000
+
+   * - TEXT BASE
+     - 0x80080000
+     - 0x800d8000
+
+   * - EMPTY
+     - 0x800d8000
+     - 0x80200000
+
+   * - BMP IMAGE
+     - 0x80200000
+     - 0x80b77660
+
+   * - STACK
+     - 0x80b77660
+     - 0x80b77e60
+
+   * - GD
+     - 0x80b77e60
+     - 0x80b78000
+
+   * - MALLOC
+     - 0x80b78000
+     - 0x80b80000
+
+   * - EMPTY
+     - 0x80b80000
+     - 0x80c80000
+
+   * - BSS
+     - 0x80c80000
+     - 0x80d00000
+
+   * - BLOBS
+     - 0x80d00000
+     - 0x80d00400
+
+   * - EMPTY
+     - 0x80d00400
+     - 0x81000000
+
 Switch Setting for Boot Mode
 ----------------------------