From ef3f364a750363f0197a71b43e66680b7820d8ea Mon Sep 17 00:00:00 2001 From: Laurentiu Tudor <laurentiu.tudor@nxp.com> Date: Tue, 30 Jul 2019 17:29:55 +0300 Subject: [PATCH] armv8: fsl-layerscape: add missing sec jr base address defines MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Add defines for all the SEC job rings base addresses. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia GeantÄ <horia.geanta@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> --- arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index ee9b33becf..7cd5333ff4 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -89,10 +89,18 @@ /* SEC */ #define CONFIG_SYS_FSL_SEC_OFFSET 0x07000000ull #define CONFIG_SYS_FSL_JR0_OFFSET 0x07010000ull +#define FSL_SEC_JR0_OFFSET CONFIG_SYS_FSL_JR0_OFFSET +#define FSL_SEC_JR1_OFFSET 0x07020000ull +#define FSL_SEC_JR2_OFFSET 0x07030000ull +#define FSL_SEC_JR3_OFFSET 0x07040000ull #define CONFIG_SYS_FSL_SEC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) #define CONFIG_SYS_FSL_JR0_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) +#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET) +#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET) +#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET) +#define FSL_SEC_JR3_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR3_OFFSET) #ifdef CONFIG_TFABOOT #ifdef CONFIG_NXP_LSCH3_2 -- 2.39.5