From 80a34e4008f022a78409657d2b0a5020a472db2e Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Mon, 6 Mar 2023 15:53:50 +0100
Subject: [PATCH] net: fec_mxc: Add ref clock setup support for i.MX8M
Mini/Nano/Plus
The FEC ref clock frequency on i.MX8M Mini/Nano/Plus was so far configured
via ad-hoc board code. Replace that with DM clock clk_set_rate() instead.
This way, the driver claims all its required clock and sets the ref clock
rate, without any need of architecture specific register fiddling.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/net/fec_mxc.c | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 1a6c18a441..7a8577158a 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -1196,6 +1196,33 @@ static void fec_gpio_reset(struct fec_priv *priv)
}
#endif
+static int fecmxc_set_ref_clk(struct clk *clk_ref, phy_interface_t interface)
+{
+ unsigned int freq;
+ int ret;
+
+ if (!CONFIG_IS_ENABLED(CLK_CCF))
+ return 0;
+
+ if (interface == PHY_INTERFACE_MODE_MII)
+ freq = 25000000;
+ else if (interface == PHY_INTERFACE_MODE_RMII)
+ freq = 50000000;
+ else if (interface == PHY_INTERFACE_MODE_RGMII ||
+ interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ interface == PHY_INTERFACE_MODE_RGMII_RXID ||
+ interface == PHY_INTERFACE_MODE_RGMII_TXID)
+ freq = 125000000;
+ else
+ return -EINVAL;
+
+ ret = clk_set_rate(clk_ref, freq);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
static int fecmxc_probe(struct udevice *dev)
{
bool dm_mii_bus = true;
@@ -1253,6 +1280,11 @@ static int fecmxc_probe(struct udevice *dev)
ret = clk_get_by_name(dev, "enet_clk_ref", &priv->clk_ref);
if (!ret) {
+ ret = fecmxc_set_ref_clk(&priv->clk_ref,
+ pdata->phy_interface);
+ if (ret)
+ return ret;
+
ret = clk_enable(&priv->clk_ref);
if (ret)
return ret;
--
2.39.5