From 47bf9c71ae838305a3ea3161af8d14e6f3fc2c82 Mon Sep 17 00:00:00 2001 From: TsiChung Liew <Tsi-Chung.Liew@freescale.com> Date: Wed, 9 Jul 2008 16:20:23 -0500 Subject: [PATCH] ColdFire: Fix FB CS not setup properly for Mcf5282 Remove all CFG_CSn_RO in cpu/mcf52x2/cpu_init.c. If CFG_CSn_RO is defined as 0, the chipselect will not be assigned. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com> --- cpu/mcf52x2/cpu_init.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c index 207a37e7d5..344bceeda1 100644 --- a/cpu/mcf52x2/cpu_init.c +++ b/cpu/mcf52x2/cpu_init.c @@ -419,8 +419,7 @@ void cpu_init_f(void) else is doing it! */ #if defined(CFG_CS0_BASE) & defined(CFG_CS0_SIZE) & \ - defined(CFG_CS0_WIDTH) & defined(CFG_CS0_RO) & \ - defined(CFG_CS0_WS) + defined(CFG_CS0_WIDTH) & defined(CFG_CS0_WS) MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF; @@ -447,8 +446,7 @@ void cpu_init_f(void) #endif #if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \ - defined(CFG_CS1_WIDTH) & defined(CFG_CS1_RO) & \ - defined(CFG_CS1_WS) + defined(CFG_CS1_WIDTH) & defined(CFG_CS1_WS) MCFCSM_CSAR1 = (CFG_CS1_BASE >> 16) & 0xFFFF; @@ -476,8 +474,7 @@ void cpu_init_f(void) #endif #if defined(CFG_CS2_BASE) & defined(CFG_CS2_SIZE) & \ - defined(CFG_CS2_WIDTH) & defined(CFG_CS2_RO) & \ - defined(CFG_CS2_WS) + defined(CFG_CS2_WIDTH) & defined(CFG_CS2_WS) MCFCSM_CSAR2 = (CFG_CS2_BASE >> 16) & 0xFFFF; @@ -505,8 +502,7 @@ void cpu_init_f(void) #endif #if defined(CFG_CS3_BASE) & defined(CFG_CS3_SIZE) & \ - defined(CFG_CS3_WIDTH) & defined(CFG_CS3_RO) & \ - defined(CFG_CS3_WS) + defined(CFG_CS3_WIDTH) & defined(CFG_CS3_WS) MCFCSM_CSAR3 = (CFG_CS3_BASE >> 16) & 0xFFFF; -- 2.39.5