From 3f9c542d3d69b1a10a5e193e779133a0454d1f44 Mon Sep 17 00:00:00 2001
From: Lee Nipper <lee.nipper@freescale.com>
Date: Thu, 10 Apr 2008 09:35:06 -0500
Subject: [PATCH] mpc83xx: Update DIMM data bus width test to support 40-bit
width
32-bit wide ECC memory modules report 40-bit width.
Changed the DIMM data bus width test to 'less than 64' instead of 'equal 32'.
Signed-off-by: Lee Nipper <lee.nipper@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
cpu/mpc83xx/spd_sdram.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index 97ac7bb3d9..70cd410298 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -601,7 +601,7 @@ long int spd_sdram()
debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
/* Check DIMM data bus width */
- if (spd.dataw_lsb == 0x20) {
+ if (spd.dataw_lsb < 64) {
if (spd.mem_type == SPD_MEMTYPE_DDR)
burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
else
@@ -763,7 +763,7 @@ long int spd_sdram()
sdram_cfg |= SDRAM_CFG_RD_EN;
/* The DIMM is 32bit width */
- if (spd.dataw_lsb == 0x20) {
+ if (spd.dataw_lsb < 64) {
if (spd.mem_type == SPD_MEMTYPE_DDR)
sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE;
if (spd.mem_type == SPD_MEMTYPE_DDR2)
--
2.39.5