From 188e94c370621708d13547d58dbc6ed3c5602aa8 Mon Sep 17 00:00:00 2001
From: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
Date: Tue, 8 Apr 2008 16:20:35 +0900
Subject: [PATCH] cpu/mips/cpu.c: Fix flush_cache bug
Cache operations have to take line address (addr), not start_addr.
I noticed this bug when debugging ping failure.
Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
---
cpu/mips/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c
index 8b43d8eb36..e267bba469 100644
--- a/cpu/mips/cpu.c
+++ b/cpu/mips/cpu.c
@@ -56,8 +56,8 @@ void flush_cache(ulong start_addr, ulong size)
unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
while (1) {
- cache_op(Hit_Writeback_Inv_D, start_addr);
- cache_op(Hit_Invalidate_I, start_addr);
+ cache_op(Hit_Writeback_Inv_D, addr);
+ cache_op(Hit_Invalidate_I, addr);
if (addr == aend)
break;
addr += lsize;
--
2.39.5