From 0e0de24b07b8314ea0cc247a89b722c2230e4b0a Mon Sep 17 00:00:00 2001
From: "xypron.glpk@gmx.de" <xypron.glpk@gmx.de>
Date: Sat, 15 Apr 2017 15:23:49 +0200
Subject: [PATCH] ddr: fsl: incorrect logical constraint in
populate_memctl_options
(pdimm[0].data_width >= 32) || (pdimm[0].data_width <= 40)
is always true.
We should use && here.
The problem was indicated by cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
---
drivers/ddr/fsl/options.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c
index d6a8fcb216..cee97fe232 100644
--- a/drivers/ddr/fsl/options.c
+++ b/drivers/ddr/fsl/options.c
@@ -916,7 +916,7 @@ unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
if ((pdimm[0].data_width >= 64) && \
(pdimm[0].data_width <= 72))
popts->data_bus_width = 0;
- else if ((pdimm[0].data_width >= 32) || \
+ else if ((pdimm[0].data_width >= 32) && \
(pdimm[0].data_width <= 40))
popts->data_bus_width = 1;
else {
--
2.39.5