From bd60252811c3c81dd0a32c0871b9116ba160190f Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Sat, 9 Jan 2016 18:34:14 +0100
Subject: [PATCH] MIPS: reserve space for exception vectors
In order to set own exception handlers, a table with the exception
vectors must be built in DRAM and the CPU EBase register must be
set to the base address of this table.
Reserve the space above the stack and use gd->irq_sp as storage
for the exception base address.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
---
arch/mips/lib/Makefile | 1 +
arch/mips/lib/stack.c | 19 +++++++++++++++++++
2 files changed, 20 insertions(+)
create mode 100644 arch/mips/lib/stack.c
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index b7ce5df765..02607f71cc 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -7,6 +7,7 @@
obj-y += cache.o
obj-y += cache_init.o
+obj-y += stack.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
diff --git a/arch/mips/lib/stack.c b/arch/mips/lib/stack.c
new file mode 100644
index 0000000000..c80f5fe146
--- /dev/null
+++ b/arch/mips/lib/stack.c
@@ -0,0 +1,19 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int arch_reserve_stacks(void)
+{
+ /* reserve space for exception vector table */
+ gd->start_addr_sp -= 0x500;
+ gd->start_addr_sp &= ~0xFFF;
+ gd->irq_sp = gd->start_addr_sp;
+ debug("Reserving %d Bytes for exception vector at: %08lx\n",
+ 0x500, gd->start_addr_sp);
+
+ return 0;
+}
--
2.39.5