From ece7844d8fbd67d078e1cb2d6807b913a2025a0c Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 16 Sep 2020 15:17:20 +0800 Subject: [PATCH] imx8mq: fix SSCG_PLL_REFCLK_SEL_x Fix SSCG_PLL_REFCLK_SEL_x, the offset starts from 0, not 16 Reported-by: Coverity 3448860 Signed-off-by: Peng Fan Reviewed-by: Ye Li --- arch/arm/include/asm/arch-imx8m/clock_imx8mq.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h index 7109d334fa..340a61e55b 100644 --- a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h +++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h @@ -358,10 +358,10 @@ enum clk_src_index { #define SSCG_PLL_LOCK_SEL_MASK BIT(3) #define SSCG_PLL_COUNTCLK_SEL_MASK BIT(2) #define SSCG_PLL_REFCLK_SEL_MASK 0x3 -#define SSCG_PLL_REFCLK_SEL_OSC_25M (0 << 16) -#define SSCG_PLL_REFCLK_SEL_OSC_27M BIT(16) -#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16) -#define SSCG_PLL_REFCLK_SEL_CLK_PN (3 << 16) +#define SSCG_PLL_REFCLK_SEL_OSC_25M (0) +#define SSCG_PLL_REFCLK_SEL_OSC_27M (1) +#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2) +#define SSCG_PLL_REFCLK_SEL_CLK_PN (3) #define SSCG_PLL_SSDS_MASK BIT(8) #define SSCG_PLL_SSMD_MASK (0x7 << 5) -- 2.39.5