From a3cc4a4810c3e195ccdb75e148a41e4668cbb36c Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Fri, 2 Aug 2024 15:53:04 +0200 Subject: [PATCH] clk: mediatek: mt7981: fix wrong mux width for pwm2 and pwm1 clock Fix wrong mux width for pwm2 and pwm1. Upstream have width 1 but U-Boot have width set to 2. Change the value to follow upstream implementation. Signed-off-by: Christian Marangi --- drivers/clk/mediatek/clk-mt7981.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7981.c b/drivers/clk/mediatek/clk-mt7981.c index 69d018b817..6e770de99c 100644 --- a/drivers/clk/mediatek/clk-mt7981.c +++ b/drivers/clk/mediatek/clk-mt7981.c @@ -404,9 +404,9 @@ static const struct mtk_composite infra_muxes[] = { INFRA_MUX(CK_INFRA_SPI2_SEL, "infra_spi2_sel", infra_spi0_parents, 0x10, 6, 1), INFRA_MUX(CK_INFRA_PWM1_SEL, "infra_pwm1_sel", infra_pwm1_parents, 0x10, - 9, 2), + 9, 1), INFRA_MUX(CK_INFRA_PWM2_SEL, "infra_pwm2_sel", infra_pwm1_parents, 0x10, - 11, 2), + 11, 1), INFRA_MUX(CK_INFRA_PWM_BSEL, "infra_pwm_bsel", infra_pwm_bsel_parents, 0x10, 13, 2), INFRA_MUX(CK_INFRA_PCIE_SEL, "infra_pcie_sel", infra_pcie_parents, 0x20, -- 2.39.5