Peng Fan [Wed, 3 Jan 2018 00:52:03 +0000 (08:52 +0800)]
imx: mx6ull-14x14-evk: enable DM QSPI driver
To support QSPI DM driver
- Add spi0 alias for qspi node. Which is used for bus number 0.
- Modify the n25q256a@0 compatible property to "spi-flash".
- Modify spi4 (gpio_spi) node to spi5
- Define DM SPI/QSPI related config to enable QSPI
Peng Fan [Wed, 3 Jan 2018 00:52:02 +0000 (08:52 +0800)]
spi: fsl_qspi: support i.MX6UL/6ULLL/7D
The QSPI module on i.MX7D is modified from i.MX6SX. The module used on
i.MX6UL/6ULL is reused from i.MX7D. They share same tx buffer size.
The endianness is not set at qspi driver initialization. So if we don't
boot from QSPI, we will get wrong endianness when accessing from AHB
address directly.
Peng Fan [Tue, 2 Jan 2018 01:32:09 +0000 (09:32 +0800)]
imx: mx6sxsabresd: config wdog pinmux
Because kernel set WDOG_B mux before pad with the common pinctrl
framwork now and wdog reset will be triggered once set WDOG_B mux
with default pad setting, we set pad setting here to workaround this.
Since imx_iomux_v3_setup_pad also set mux before pad setting, we set
as GPIO mux firstly here to workaround it.
Peng Fan [Tue, 2 Jan 2018 01:32:08 +0000 (09:32 +0800)]
imx: mx6sxsabresd: Enable DM driver
Enable I2C/MMC/GPIO/REGUALTOR/PMIC/USB DM drivers.
There are some dependency, such as when DM MMC enabled, USB compile error.
Also the i.MX I2C MMC DM driver does not support legacy GPIO interface.
So enable them all together.
Peng Fan [Tue, 2 Jan 2018 07:51:20 +0000 (15:51 +0800)]
misc: mxc_ocotp: check fuse word before programming on i.MX7ULP
On i.MX7ULP, the fuse words (except bank 0 and 1) only supports to
write once, because they use ECC mode. Multiple writes may damage
the ECC value and cause a wrong fuse value decoded when reading.
This patch adds a checking before the fuse word programming, only
can write when the word value is 0.
Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
CPU: Freescale i.MX6DL rev1.2 996 MHz (running at 792 MHz)
CPU: Commercial temperature grade (0C to 95C) at 40C
Reset cause: POR
I2C: ready
DRAM: 1 GiB
MMC: FSL_SDHC: 0
In: serial
Out: serial
Err: serial
Net: FEC [PRIME]
board/BuR: provide real clock-frequency instead a divider
Actual am335x-fb implementation takes now a real clock frequency instead
a divider. So this component doesn't need to know anymore some base
frequency of the LCDC, we simply provide the pixel-clock frequency.
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Reviewed-by: Anatolij Gustschin <agust@denx.de>
The LCDC IP-core an be feed from several clock sources, one of those is
a dedicated DPLL for generating a dividable base-clock for this IP-core.
The TRM specifies the maximum input frequency for the LCCD with 200 MHz,
so we must not exceed this value with the PLL frequency (which can lock
much higher).
This patch tries every combination of multipliers and divisors of the
PLL and the IP-core itself for getting as near as possible the the
requested panel->pxl_clk.
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Reviewed-by: Anatolij Gustschin <agust@denx.de>
Sumit Garg [Sat, 6 Jan 2018 03:34:24 +0000 (09:04 +0530)]
armv8: ls1088a: SPL size reduction
Using changes in this patch we were able to reduce approx 8k
size of u-boot-spl.bin image. Following is breif description of
changes to reduce SPL size:
1. Changes in board/freescale/ls1088a/Makefile to remove
compilation of eth.c and cpld.c in case of SPL build.
2. Changes in board/freescale/ls1088a/ls1088a.c to keep
board_early_init_f funcations in case of SPL build.
3. Changes in ls1088a_common.h & ls1088ardb.h to remove driver
specific macros due to which static data was being compiled in
case of SPL build.
Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Alison Wang [Thu, 28 Dec 2017 05:00:55 +0000 (13:00 +0800)]
armv8: Implement workaround for Cortex-A53 erratum 855873
855873: An eviction might overtake a cache clean operation
Workaround: The erratum can be avoided by upgrading cache clean by
address operations to cache clean and invalidate operations. For
Cortex-A53 r0p3 and later release, this can be achieved by setting
CPUACTLR.ENDCCASCI to 1.
This patch is to implement the workaround for this erratum.
Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Ahmed Mansour [Fri, 15 Dec 2017 21:01:01 +0000 (16:01 -0500)]
configs: Move SYS_DPAA_QBMAN to Kconfig
The CONFIG_SYS_DPAA_QBMAN define is used by DPAA1 freescale SOCs to
add device tree fixups that allow deep sleep in Linux. The define was
placed in header files included by a number of boards, but was not
explicitly documented in any of the Kconfigs. A description was added
to the drivers/networking menuconfig and default selection for
current SOCs that have this part
Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Ahmed Mansour [Fri, 15 Dec 2017 21:01:00 +0000 (16:01 -0500)]
drivers/misc: Share qbman init between archs
This patch adds changes necessary to move functionality present in
PowerPC folders with ARM architectures that have DPAA1 QBMan hardware
- Create new board/freescale/common/fsl_portals.c to house shared
device tree fixups for DPAA1 devices with ARM and PowerPC cores
- Add new header file to top includes directory to allow files in
both architectures to grab the function prototypes
- Port inhibit_portals() from PowerPC to ARM. This function is used in
setup to disable interrupts on all QMan and BMan portals. It is
needed because the interrupts are enabled by default for all portals
including unused/uninitialised portals. When the kernel attempts to
go to deep sleep the unused portals prevent it from doing so
Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Yuantian Tang [Mon, 11 Dec 2017 05:12:09 +0000 (13:12 +0800)]
armv8: layerscape: sata: refine port register configuration
Sata registers PP2C and PP3C are used to control the configuration
of the PHY control OOB timing for the COMINIT/COMWAKE parameters
respectively. Calculate those parameters from port clock frequency.
Overwrite those registers with calculated values to get better OOB
timing.
Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Tom Rini [Fri, 22 Dec 2017 03:13:22 +0000 (22:13 -0500)]
build: Drop CONFIG_SPL_BUILD guards in some cases
Given gcc-6.1 and later we can now safely have strings discarded when
the functions are unused. This lets us drop certain cases of not
building something so that we don't have the strings brought in when the
code was discarded. Simplify the code now by dropping guards we don't
need now.
Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Chander Kashyap <k.chander@samsung.com> Cc: Thomas Abraham <thomas.ab@samsung.com> Cc: Vipin Kumar <vipin.kumar@st.com> Cc: Wenyou Yang <wenyou.yang@microchip.com> Signed-off-by: Tom Rini <trini@konsulko.com>
fat write: Fixed a problem with the case of file names when writing files
commit 21a24c3bf35b ("fs/fat: fix case for FAT shortnames") made it
possible that get_name() returns file names with some upper cases.
find_directory_entry() must be updated to take this account, and use
case-insensitive functions to compare file names.
Almost all of them were only used for the mach_is_foo() logic in
arch/arm/asm/mach-types.h that were dropped in
commit f9dadaef8b75fa ("arm: Re-sync asm/mach-types.h with
Linux Kernel v4.9")
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Configure AM57xx EVMs for the exact PHY part that is
present on the various boards. This makes U-Boot apply
configurations needed for this PHY like centering the
FLP timing.
For configurations to take effect, DM_ETH needs to be
enabled. Do that too.
Tested on BeagleBoard x15 and AM571x IDK.
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Patrice Chotard [Tue, 12 Dec 2017 09:14:59 +0000 (10:14 +0100)]
ARM: DTS: stm32: add MMC nodes for stm32f746-disco and stm32f769-disco
Add DT nodes to enable ARM_PL180_MMCI IP support for STM32F746
and STM32F769 discovery boards
There is a hardware issue on these boards, it misses a pullup on the GPIO line
used as card detect to allow correct SD card detection.
As workaround, cd-gpios property is not present in DT.
So SD card is always considered present in the slot.
Patrice Chotard [Tue, 12 Dec 2017 08:49:44 +0000 (09:49 +0100)]
board: stm32: add stm32f469-discovery board support
This board offers :
_ STM32F469NIH6 microcontroller featuring 2 Mbytes of Flash memory
and 324 Kbytes of RAM in BGA216 package
_ On-board ST-LINK/V2-1 SWD debugger, supporting USB reenumeration capability:
_ Mbed-enabled (mbed.org)
_ USB functions: USB virtual COM port, mass storage, debug port
_ 4 inches 800x480 pixel TFT color LCD with MIPI DSI interface and capacitive
touch screen
_ SAI Audio DAC, with a stereo headphone output jack
_ 3 MEMS microphones
_ MicroSD card connector
_ I2C extension connector
_ 4Mx32bit SDRAM
_ 128-Mbit Quad-SPI NOR Flash
_ Reset and wake-up buttons
_ 4 color user LEDs
_ USB OTG FS with Micro-AB connector
_ Three power supply options:
_ Expansion connectors and Arduino™ UNO V3 connectors
Patrice Chotard [Tue, 12 Dec 2017 08:49:41 +0000 (09:49 +0100)]
ram: stm32: add memory mapping selection support
This allows to controls the memory internal mapping at
address 0x0000 0000.
We can either map at 0x0000 0000 :
_ main flash memory
_ system flash memory
_ FMC bank1 (NOR/PSRAM 1 and 2)
_ embedded SRAM
_ FMC/SDRAM bank1
Patrice Chotard [Tue, 12 Dec 2017 08:49:39 +0000 (09:49 +0100)]
board: stm32f429-disco: switch to DM STM32 clock driver
Use available DM clk_stm32f.c driver instead of dedicated
mach-stm32/stm32f4/clock.c.
Migrate periph_clock defines from stm32_periph.h directly in
CLK driver. These periph_clock defines will be removed when STMMAC,
TIMER2 and SYSCFG drivers will support DM CLK.
In order to use common clock driver between STM32F4 and
STM32F7, remove clock_get() call
As APB_PSC is always set to 2, only case when
clock_get(CLOCK_AHB) != clock_get(CLOCK_APB1) is kept
STM32F4 SoCs uses the same pinctrl block as found into
STM32F7 and H7 SoCs.
We can add "st,stm32f429-pinctrl" and "st,stm32f469-pinctrl"
compatible string into pinctrl_stm32.c.
Chris Packham [Mon, 8 Jan 2018 03:17:12 +0000 (16:17 +1300)]
ARM: mvebu: correct reference for "ethernet1" on DB-88F6820-AMC
The DB-88F6820-AMC connects ethernet@34000 and ethernet@70000 which are
labeled as eth2 and eth0 in armada-38x.dts. The ethernet@30000 (eth1) is
not used on the AMC board.
This eliminates the following bootup message
Device 'ethernet@70000': seq 0 is in use by 'ethernet@34000'
Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
Eddie Cai [Fri, 15 Dec 2017 00:17:10 +0000 (08:17 +0800)]
usb: rockchip: add the rockusb gadget
this patch implement rockusb protocol on the device side. this is based on
USB download gadget infrastructure. the rockusb function implements the rd,
wl, rid commands. it can work with rkdeveloptool
Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Chen-Yu Tsai [Sat, 30 Dec 2017 12:44:07 +0000 (20:44 +0800)]
musb: sunxi: Use base address from device tree
Now that the musb sunxi glue driver is completely device model / device
tree driven, we should use the base address from the device tree,
instead of hard-coding it in the source code.
Fixes: 3a61b080acee ("musb: sunxi: switch to the device model") Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Tuomas Tynkkynen [Fri, 22 Dec 2017 22:30:56 +0000 (00:30 +0200)]
ARM: sunxi: Remove left-over cd-inverted property from pcDuino3
Commit 8620f384098b ("dm: sunxi: Linksprite_pcDuino3: Correct polarity
of MMC card detect") claims that the Pcduino3 device tree had an
incorrect polarity for the card detect pin and thus changed the polarity
flag of the cd-gpios from GPIO_ACTIVE_HIGH to GPIO_ACTIVE_LOW.
Actually the DT was correct since according to the mmc binding, a
combination of GPIO_ACTIVE_HIGH + cd-inverted results in an active-low
polarity. But because the U-Boot driver lacks the code to look at the
cd-inverted property (unlike the Linux driver) it interpreted the
polarity of active-high. Thus, after that commit the DT is actually
wrong from the binding/Linux point of view.
To make both Linux and U-Boot interpret the DT in the same way, just
drop the left-over cd-inverted property. I've sent a Linux patch to
switch all sunxi DTs over to not using the cd-inverted property, so
eventually all sunxi boards in U-Boot will be consistent in not using
cd-inverted.
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Maxime Ripard [Thu, 21 Dec 2017 12:55:52 +0000 (13:55 +0100)]
sunxi: maintainers: Add myself for the TBS A711
Support for that board got introduced recently without the maintainers
part. Let's fix that.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Chen-Yu Tsai [Thu, 7 Dec 2017 13:00:45 +0000 (21:00 +0800)]
sunxi: Add support for Libre Computer Board ALL-H3-CC H3 ver.
The Libre Computer Board ALL-H3-CC from Libre Technology is a Raspberry
Pi B+ form factor single board computer based on the Allwinner H3 SoC.
The board has 1GB DDR3 SDRAM, provided by 4 2Gb chips. The mounting holes
and connectors are in the exact same position as on the Raspberry Pi B+.
Raspberry Pi B+ like peripherals supported on this board include:
- Power input through micro-USB connector (without USB OTG)
- Native 100 Mbps ethernet using the internal PHY, as opposed to
USB-based on the RPi
- 4x USB 2.0 host ports, directly connected to the SoC, as opposed to
being connected through a USB 2.0 hub on the RPi
- TV and audio output on a 3.5mm TRRS jack
- HDMI output
- Micro-SD card slot
- Standard RPi B+ GPIO header, with the standard peripherals routed to
the same pins.
* 5V, 3.3V power, and ground
* I2C0 on the H3 is routed to I2C1 pins on the RPi header
* I2C1 on the H3 is routed to I2C0 pins on the RPi header
* UART1 on the H3 is routed to UART0 pins on the RPi header
* SPI0 on the H3 is routed to SPI0 pins on the RPi header,
with GPIO pin PA17 replacing the missing Chip Select 1
* I2S1 on the H3 is routed to PCM pins on the RPi header
- Additional peripherals from the H3 are available on different pins.
These include I2S0, JTAG, PWM1, SPDIF, SPI1, and UART3
In addition, there are a number of new features:
- Console UART header
- Consumer IR receiver
- Camera interface (not compatible with RPi)
- Onboard microphone
- eMMC expansion module port
- Heatsink mounting holes
This patch adds defconfig and dts files for this board. The dts file is
the same as the one submitted for inclusion in Linux, with some minor
revisions to match the dtsi file and old EMAC bindings in U-boot.
Since the OTG controller is wired to a USB host port, and the H3 has
proper USB hosts to handle host mode, the MUSB driver is not enabled.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
arm: Exercise v7_arch_cp15_set_acr even without errata fixups
By applying this patch, we are ensuring that the code paths
responsible for applying errata workarounds are also exercised
on CPU revisions, which actually don't need these workarounds.
Only CONFIG_ARM_ERRATA_621766, CONFIG_ARM_ERRATA_454179,
CONFIG_ARM_ERRATA_725233 and CONFIG_ARM_ERRATA_430973 are
covered by this patch (Cortex-A8).
This improves code coverage when testing U-Boot builds
on newer hardware. In particular, the problematic commit 00bbe96ebabb ("arm: omap: Unify get_device_type() function")
would break both BeageBoard and BeagleBoard XM rather than
just older BeagleBoard.
As an additional bonus, we need fewer instructins and the SPL
size is reduced.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Miquel Raynal [Fri, 29 Dec 2017 14:31:56 +0000 (15:31 +0100)]
pinctrl: mvebu: Make drivers depend on the pinctrl framework
Armada pinctrl drivers shall not be compiled without the entire pinctrl
framework and thus lack a "depends on" condition, otherwise the driver
will simply not be probed.
Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com> Signed-off-by: Stefan Roese <sr@denx.de>
Miquel Raynal [Thu, 28 Dec 2017 14:43:09 +0000 (15:43 +0100)]
ARM: mvebu: Allow MVNETA to be selected with Armada 3700 SoCs
Until now, Armada 3700 SoCs could not enable the mvneta driver, and thus
did not benefit from Ethernet support. Add ARMADA_3700 in the
"depends on" list of the MVNETA Kconfig entry.
Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Stefan Roese <sr@denx.de>
Introduce the recovery image download script for usage with
Marvell Armada SoC families (excepting 37xx family).
Since Marvell BootROM uses a sliding window in UART buffer
for detecting escape sequence during the boot, it's easier
to interrupt the normal boot flow by sending a long stream
of chained escape sequences to the serial port instead of
periodically sending a single escape sequence as it is done
by kwboot utility.
Additional benefit of using this script is the ability to
adjust the escape sequence stream length withoiut need for
compilation.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
Masahiro Yamada [Sat, 6 Jan 2018 13:59:25 +0000 (22:59 +0900)]
ARM: uniphier: enable CONFIG_MMC_SDHCI_SDMA for ARMv8 SoCs
I did not enable SDMA when I added sdhci-cadence support because LD20
boards are equipped with a large amount memory beyond 32 bit address
range, but SDMA does not support the 64bit address. U-Boot relocates
itself to the end of effectively available RAM. This would make the
MMC enumeration fail because the buffer for EXT_CSD allocated in the
stack would go too high, then SDMA would fail to transfer data.
Recent SDHCI-compatible controllers support ADMA, but unfortunately
U-Boot does not support ADMA.
In the previous commit, I hided the DRAM area that exceeds the 32 bit
address range. Now, I can enable CONFIG_MMC_SDHCI_SDMA.
Masahiro Yamada [Sat, 6 Jan 2018 13:59:24 +0000 (22:59 +0900)]
ARM: uniphier: do not use RAM that exceeds 32 bit address range
LD20 / PXs3 boards are equipped with a large amount of memory beyond
the 32 bit address range. U-Boot relocates itself to the end of the
available RAM.
This is a problem for DMA engines that only support 32 bit physical
address, like the SDMA of SDHCI controllers.
In fact, U-Boot does not need to run at the very end of RAM. It is
rather troublesome for drivers with DMA engines because U-Boot does
not have API like dma_set_mask(), so DMA silently fails, making the
driver debugging difficult.
Hide the memory region that exceeds the 32 bit address range. It can
be done by simply carving out gd->ram_size. It would also possible to
override get_effective_memsize() or to define CONFIG_MAX_MEM_MAPPED,
but dram_init() is a good enough place to do this job.
Tom Rini [Fri, 22 Dec 2017 17:19:22 +0000 (12:19 -0500)]
arm: socfpga: Guard commands with CONFIG_SPL_BUILD tests
In order for these commands to not be included in SPL we need to guard
compilation with CONFIG_SPL_BUILD checks. Reorganize some sections of
code slightly in order to avoid new warnings and mark the command
functions as static as they should have been before.
Cc: Marek Vasut <marex@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com>
Ran Wang [Wed, 20 Dec 2017 02:34:19 +0000 (10:34 +0800)]
usb: ehci: fsl: Fix some compile warnings.
When enable CONFIG_HAS_FSL_DR_USB, we might encounter below compile
warning, apply this patch can fix it:
drivers/usb/host/ehci-fsl.c:109:4: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
((u32)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
^
drivers/usb/host/ehci-fsl.c:108:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
hcor = (struct ehci_hcor *)
^
drivers/usb/host/ehci-fsl.c:115:8: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
(u32)hccr, (u32)hcor,
^
include/log.h:131:26: note: in definition of macro 'debug_cond'
printf(pr_fmt(fmt), ##args); \
^~~~
drivers/usb/host/ehci-fsl.c:114:2: note: in expansion of macro 'debug'
debug("ehci-fsl: init hccr %x and hcor %x hc_length %d\n",
^~~~~
drivers/usb/host/ehci-fsl.c:115:19: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
(u32)hccr, (u32)hcor,
^
include/log.h:131:26: note: in definition of macro 'debug_cond'
printf(pr_fmt(fmt), ##args); \
^~~~
drivers/usb/host/ehci-fsl.c:114:2: note: in expansion of macro 'debug'
debug("ehci-fsl: init hccr %x and hcor %x hc_length %d\n",
^~~~~
Jagan Teki [Fri, 5 Jan 2018 07:04:21 +0000 (12:34 +0530)]
board: engicam: Fix to remove legacy board/icorem6_rqs
board/icorem6_rqs/ is forgot to remove while moving
common board files together in
(sha1: 52aaddd6f415397bb2eae0d68a8cc1c5c4a98bb3)
"i..MX6: engicam: Add imx6q/imx6ul boards for existing boards"
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Stefan Agner [Fri, 5 Jan 2018 14:08:19 +0000 (15:08 +0100)]
imx: initialize and use generic timer on i.MX 6UL/ULL
The i.MX 6UL/ULL feature a Cortex-A7 CPU which suppor the ARM
generic timer. This change makes use of the ARM generic timer in
U-Boot.
This is crucial to make the ARM generic timers usable in Linux since
timer_init() initalizes the system counter module, which is necessary
to use the generic timers CP15 registers.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Clemens Gruber [Sun, 7 Jan 2018 19:26:29 +0000 (20:26 +0100)]
crypto/fsl: fix BLOB encapsulation and decapsulation
The blob_encap and blob_decap functions were not flushing the dcache
before passing data to CAAM/DMA and not invalidating the dcache when
getting data back.
Therefore, blob encapsulation and decapsulation failed with errors like
the following due to data cache incoherency:
"40000006: DECO: desc idx 0: Invalid KEY command"
To ensure coherency, we require the key_mod, src and dst buffers to be
aligned to the cache line size and flush/invalidate the memory regions.
The same requirements apply to the job descriptor.
Tested on an i.MX6Q board.
Reviewed-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
Andy Shevchenko [Thu, 4 Jan 2018 16:40:13 +0000 (18:40 +0200)]
x86: tangier: Add Bluetooth to ACPI table
As defined on reference board followed by Intel Edison a Bluetooth
device is attached to HSU0, i.e. PCI 0000:04.1.
Describe it in ACPI accordingly.
Note, we use BCM2E95 ID here as one most suitable for such device based
on the description in commit message of commit 89ab37b489d1
("Bluetooth: hci_bcm: Add support for BCM2E95 and BCM2E96")
in the Linux kernel source tree.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Andy Shevchenko [Thu, 4 Jan 2018 16:40:12 +0000 (18:40 +0200)]
x86: tangier: Use actual GPIO hardware numbers
The recent commit 03c4749dd6c7
("gpio / ACPI: Drop unnecessary ACPI GPIO to Linux GPIO translation")
in the Linux kernel reveals the issue we have in ACPI tables here,
i.e. we must use hardware numbers for GPIO resources and,
taking into consideration that GPIO and pin control are *different* IPs
on Intel Tangier, we need to supply numbers properly.
Besides that, it improves user experience since the official documentation
for Intel Edison board is referring to GPIO hardware numbering scheme.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
projects / u-boot.git / log
