Marek Vasut [Sat, 30 Mar 2019 06:22:09 +0000 (07:22 +0100)]
net: sh_eth: Initialize PHY in probe() once
Reset and initialize the PHY once in the probe() function rather than
doing it over and over again is start() function. This requires us to
keep the clock enabled while the driver is in use. This significantly
reduces the time between transfers as the PHY doesn't have to restart
autonegotiation between transfers, which takes forever.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Mon, 4 Mar 2019 21:29:30 +0000 (22:29 +0100)]
pinctrl: renesas: Add TDSEL fixup for H2/E2 ES1.0 SoCs
Linux 5.0, commit 1c163f4c7b3f621efff9b28a47abb36f7378d783,
has a TDSEL fix for R8A7790 H2 and R8A7794 E2 SoCs, implement
similar fix for U-Boot. The difference here is that the SoC
ES matching has to be implemented manually.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Mon, 4 Mar 2019 12:36:13 +0000 (13:36 +0100)]
clk: renesas: Add R8A77965 clock tables
Add clock tables for R8A77965 from Linux 5.0 , except for the
crit, R and Z clock, which are neither used nor supported by
the U-Boot clock framework yet.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Wed, 13 Mar 2019 20:09:49 +0000 (21:09 +0100)]
ARM: rmobile: Enable multi-DTB fit LZO compression
Enable LZO compression of the multi-DTB fitImages, since the U-Boot
with multiple DTs enabled is becoming quite large and the DTs can
be well compressed. The LZO compression saves almost 200 kiB on the
Salvator-X(S) and ULCB targets.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Fri, 8 Mar 2019 15:06:55 +0000 (16:06 +0100)]
lib: fdt: Allow LZO and GZIP DT compression in U-Boot
Add required Kconfig symbols, Makefile bits and macro fixes in a
few places to support LZO and DT compression in U-Boot. This can
save a lot of space with multi-DTB fitImages.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Marek Vasut [Wed, 13 Mar 2019 20:11:22 +0000 (21:11 +0100)]
lib: fdt: Allow enabling both LZO and GZIP DT compression
Allow enabling both LZO and GZIP DT compression in SPL and fix a
bug where if the GZIP decompression failed, the LZO decompression
would not even be attempted.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
Marek Vasut [Thu, 18 Oct 2018 16:38:05 +0000 (18:38 +0200)]
ARM: renesas: Save boot parameters passed in by ATF
The ATF can pass additional information via the first four registers,
x0...x3. The R-Car Gen3 with mainline ATF, register x1 contains pointer
to a device tree with platform information. Save these registers for
future use.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Tue, 5 Mar 2019 03:25:55 +0000 (04:25 +0100)]
lib: fdt: Split fdtdec_setup_memory_banksize()
Split fdtdec_setup_memory_banksize() into fdtdec_setup_memory_banksize_fdt(),
which allows the caller to pass custom blob into the function and the
original fdtdec_setup_memory_banksize(), which uses the gd->fdt_blob. This
is useful when configuring the DRAM properties from a FDT blob fragment
passed in by the firmware.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Tue, 5 Mar 2019 03:25:54 +0000 (04:25 +0100)]
lib: fdt: Split fdtdec_setup_mem_size_base()
Split fdtdec_setup_mem_size_base() into fdtdec_setup_mem_size_base_fdt(),
which allows the caller to pass custom blob into the function and the
original fdtdec_setup_mem_size_base(), which uses the gd->fdt_blob. This
is useful when configuring the DRAM properties from a FDT blob fragment
passed in by the firmware.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Tue, 12 Mar 2019 03:00:09 +0000 (04:00 +0100)]
spl: ymodem: Move GZ handling out of YModem session
In case the gunzip() call fails, it will print an error message.
If that happens within the YModem session, the error message will
not be displayed and would be useless. Move the gunzip() call out
of the YModem session to make those possible error messages visible.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Tom Rini <trini@konsulko.com>
Jagan Teki [Mon, 8 Apr 2019 20:27:54 +0000 (01:57 +0530)]
arm: sunxi: Enable DM_MMC on required SoCs
Enabling DM_MMC is forcing CONFIG_BLK=y so if any board which uses
SCSI must need to enable DM_SCSI otherwise SCSI reads on that particular
target making invalid reading to the disk drive.
Allwinner platform do support SCSI on A10, A20 and R40 SoC's out of
these only A10 have DM_SCSI enabled. So enabling DM_MMC on A20, R40
would eventually end-up with scsi disk read failures like [1]
So, enable DM_MMC in all places of respective SoC's instead of enabling
them globally to Allwinner platform.
Now, DM_MMC is enabled in Allwinner SoC's except A20 and R40.
net: dm: fec: Support phy-reset-post-delay property
As per Linux kernel DT binding doc:
- phy-reset-post-delay : Post reset delay in milliseconds. If present then
a delay of phy-reset-post-delay milliseconds will be observed after the
phy-reset-gpios has been toggled. Can be omitted thus no delay is
observed. Delay is in range of 1ms to 1000ms. Other delays are invalid.
Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@netmodule.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Lukasz Majewski <lukma@denx.de>
Stefan Roese [Wed, 3 Apr 2019 07:12:48 +0000 (09:12 +0200)]
watchdog: Move watchdog_dev to data section (BSS may not be cleared)
This patch moves all instances of static "watchdog_dev" declarations to
the "data" section. This may be needed, as the BSS may not be cleared
in the early U-Boot phase, where watchdog_reset() is already beeing
called. This may result in incorrect pointer access, as the check to
"!watchdog_dev" in watchdog_reset() may not be true and the function
may continue to run.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: "Marek Behún" <marek.behun@nic.cz> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Tested-by: Michal Simek <michal.simek@xilinx.com> (on zcu100) Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Hannes Schmelzer [Fri, 29 Mar 2019 08:54:05 +0000 (09:54 +0100)]
net: phy: implement fallback mechanism for negative phy adresses
Negative phy-addresses can occour if the caller function was not able to
determine a valid phy address (from device-tree for example). In this
case we catch this here and search for ANY phy device on the given mdio-
bus.
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Lukasz Majewski <lukma@denx.de>
Thomas Petazzoni [Sat, 30 Mar 2019 14:29:23 +0000 (15:29 +0100)]
tools/Makefile: build host tools with -std=gnu99
Parts of the code are using C99 constructs (such as variables declared
inside loops), but also GNU extensions (such as typeof), so using
-std=gnu99 is necessary to build with older versions of gcc that don't
default to building with gnu99.
It fixes the following build failure:
./tools/../lib/crc16.c: In function "crc16_ccitt":
./tools/../lib/crc16.c:70:2: error: "for" loop initial declarations are only allowed in C99 mode
for (int i = 0; i < len; i++)
^
./tools/../lib/crc16.c:70:2: note: use option -std=c99 or -std=gnu99 to compile your code
when building the host tools with gcc 4.7.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Neil Armstrong [Wed, 3 Apr 2019 11:46:37 +0000 (13:46 +0200)]
configs: khadas_vim2: Fix defconfig
The Khadas VIM2 defconfig was missing the USB PHY config and
two other misc configs to setup dram banks and call misc_init_r.
Align it on the other Amlogic SoC based boards defconfig.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
The FEC ETH driver switched to PHY GPIO reset performed with data defined
in DTS.
For the HSC|DDC boards the GPIO reset signal is active low and hence the
wrong DTS description must be changed (otherwise the reset for ETH is not
properly setup).
Jagan Teki [Thu, 28 Mar 2019 08:16:11 +0000 (13:46 +0530)]
clk: sunxi: a10: Add CLK_AHB_GMAC
CLK_AHB_GMAC was suppose to be part of previous commit
"clk: sunxi: Implement A10 EMAC clocks" add it so-that
we can get rid of sunxi_set_gate warning on boot message.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Fabio Estevam [Wed, 27 Mar 2019 23:03:39 +0000 (20:03 -0300)]
pico-imx7d: README: Recommend the usage of a USB hub
Since commit 9e3c0174da842 ("pico-imx7d: Add LCD support") we started to
notice some hangs in U-Boot.
There is not an issue on such commit per se, but due to the LCD support
the current drawn is increased and this may cause issues when powering
pico-imx7d-pi from USB.
Some computers may be a bit strict with USB current draw and will
shut down their ports if the draw is too high.
The solution for that is to use an externally powered USB hub between the
board and the host computer.
Jagan Teki [Thu, 21 Mar 2019 08:35:53 +0000 (14:05 +0530)]
configs: icorem6: Use imx6 cratch register for bootcount
SRAM address used for bootcount on exiting code is erasing
previous count value when system reset from Linux. So use
the dedicated imx6 scratch register, GPR2 to preserve the
contents even if the system reset from Linux.
Fixes: 4eb9aa39350e ("configs: imx6qdl_icore_mmc: Enable watchdog and bootcounter") Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Shyam Saini <shyam.saini@amarulasolutions.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
Adam Ford [Sun, 3 Mar 2019 22:22:45 +0000 (16:22 -0600)]
ARM: imx6q_logic: Enable UUID support
With UUID support, the root can now point to UUID. This makes
swiching between mmc 0 and mmc 1 easier by simplying changing
mmcdev between 0 and 1. From there, the scripts handle the rest.
Fabio Estevam [Thu, 21 Mar 2019 13:59:06 +0000 (10:59 -0300)]
pico-imx6ul: Fix eMMC boot after DM_MMC conversion
After the DM_MMC conversion the following eMMC boot error is observed:
U-Boot SPL 2019.04-rc4 (Mar 20 2019 - 18:53:28 +0000)
Trying to boot from MMC1
MMC Device 0 not found
spl: could not find mmc device 0. error: -19
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
This happens because the SPL code does not initialize the SDHC pins
and clock.
Fix it by moving the original eMMC initialization from U-Boot proper
to SPL.
Reported-by: Otavio Salvador <otavio@ossystems.com.br> Signed-off-by: Fabio Estevam <festevam@gmail.com> Tested-by: Fabio Berton <fabio.berton@ossystems.com.br> Reviewed-by: Otavio Salvador <otavio@ossystems.com.br>
Tom Rini [Sun, 31 Mar 2019 11:25:00 +0000 (07:25 -0400)]
Merge tag 'rockchip-fixes-for-2019.04' of git://git.denx.de/u-boot-rockchip
Last-minute fixes for Rockchip for 2019.04:
- reverts the deprecation of the 'download-key' detection
(with a full solution pending for the next release)
- applies a temporary fix for the 32bit pinctrl registers on the RK3288
Marek Vasut [Sat, 30 Mar 2019 06:43:55 +0000 (07:43 +0100)]
ARM: rmobile: rcar-gen2: Activate bootm_size
Commit d245059ff797 ("ARM: rmobile: rcar-gen3: Activate bootm_size")
only fixed the superfluous CONFIG_SYS_BOOTMAPSZ for R-Car Gen3, even
though it listed all affected boards. Apply the same fix to Gen2.
Marek Vasut [Sat, 30 Mar 2019 05:10:49 +0000 (06:10 +0100)]
ARM: rmobile: alt: Remove R8A7794_ETHERNET_B
The R8A7794_ETHERNET_B config option is unused and based on the
description, this is a setting which should be fully done on a
DT level instead. Remove this config option.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Matthias Brugger [Thu, 28 Mar 2019 13:47:39 +0000 (14:47 +0100)]
RPi: Add mbrugger as board maintainer
I took over maintainership from Alex Graf with commit 3157bbfa18 ("rpi: Make Matthias maintainer")
But I forgot to update the board maintainer file.
This patch adds myself to the game.
Signed-off-by: Matthias Brugger <mbrugger@suse.com> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Alexander Graf <agraf@csgraf.de>
Andrew F. Davis [Tue, 26 Mar 2019 15:12:01 +0000 (10:12 -0500)]
configs: ti: Move FIT image load address to avoid overwrite
The FIT image is loaded to 0x8700_0000 followed by extracting from that
several large images also into the 0x8x00_0000 range. Large images
can end up overwriting the FIT image as it is being extracted from.
Move the FIT load address clear out to 0x9000_0000, this will require
a board to have at least 256MB of DRAM, if less then more careful
planning will be required for that platform.
BOUGH CHEN [Tue, 26 Mar 2019 06:24:17 +0000 (06:24 +0000)]
mmc: correct the HS400 initialization process
After the commit b9a2a0e2e9c0 ("mmc: Add support for downgrading
HS200/HS400 to HS mode"), it add a parameter in mmc_set_card_speed()
which indicates that the HS200/HS400 to HS downgrade is happening.
During the HS400 initialization, first select to HS200, and config
the related clock rate, then downgrade to HS mode. So here also need
to config the downgrade value to be true for two reasons. First,
make sure in the function mmc_set_card_speed(), after switch to HS
mode, first config the clock rate, then read the EXT_CSD, avoid
receiving data of EXT_CSD in HS mode at 200MHz. Second, after issue
the MMC_CMD_SWITCH command, it need to wait a bit then switch bus
properties.
Test on i.MX8QM MEK board, some Micron eMMC will stuck in transfer
mode in this case, and USDHC will never get data transfer complete
status, cause the uboot hang.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Acked-by: Marek Vasut <marek.vasut@gmail.com>
Tom Rini [Fri, 29 Mar 2019 13:21:30 +0000 (09:21 -0400)]
Merge tag 'efi-2019-04-rc5-2' of git://git.denx.de/u-boot-efi
Pull request for UEFI system for v2019.04-rc5-2
This patch series contains a bug fix for a double free in a UEFI unit
test. The other patches are documentation only (except for the definition
of two additional constants).
David Wu [Tue, 12 Feb 2019 11:51:51 +0000 (19:51 +0800)]
pinctrl: rockchip: Add 32bit writing function for rk3288 gpio0 pinctrl
There are no higher 16 writing corresponding bits for pmu_gpio0's
iomux/drive/pull at rk3288, need to read the value from register
firstly. Add the flag to distinguish it from normal registers.
Philipp Tomsich [Fri, 29 Mar 2019 08:21:13 +0000 (09:21 +0100)]
Revert "rockchip: Drop call to rockchip_dnl_mode_check() for now"
Due to a final resolution not coming up in time for 2019.04 and
following the consensus on the discussion, we'll keep this around
for 2019.04 after all.
Tom Rini [Fri, 29 Mar 2019 01:44:49 +0000 (21:44 -0400)]
Merge tag 'arc-last-minute-for-2019.04' of git://git.denx.de/u-boot-arc
This is last minute change which fixes problems in runtime on
AXS10x board caused by some changes in NAND framework and
tiny documentation improvement.
Anyways NAND flash storage was never really used on the board for various
reasons and now we decided to drop it for good.
Note this change only touches 1 ARC board so that should be safe for others.
As usual - build tested in TravisCI, see
https://travis-ci.org/abrodkin/u-boot/builds/512041342
Jernej Skrabec [Sun, 24 Mar 2019 18:26:40 +0000 (19:26 +0100)]
sunxi: video: HDMI: Fix clock setup
Currently, HDMI driver doesn't consider minimum and maximum allowed rate
of pll3 (video PLL). It works most of the time, but not always.
Consider monitor with resolution 1920x1200, which has pixel clock rate
of 154 MHz. Current code would determine that pll3 rate has to be set to
154 MHz. However, minimum supported rate is 192 MHz. In this case video
output just won't work.
The reason why the driver is written in the way it is, is that at the
time HDMI PHY and clock configuration wasn't fully understood. But now
we have needed knowledge, so the issue can be fixed.
With this fix, clock configuration routine uses full range (1-16) for
clock divider instead of limited one (1, 2, 4, 11). It also considers
minimum and maximum allowed rate for pll3.
Eugeniy Paltsev [Wed, 27 Mar 2019 13:53:43 +0000 (16:53 +0300)]
ARC: AXS10x: drop NAND support
On AXS10x boards we have non-standard NAND controller
which was never really used a lot as there're other much more
convenient [as they are standard & removable] persistent media
like SD-card and USB mass storage.
Moreover after recent changes we face with some NAND controller
runtime issues. So instead of keeping support of yet another
non-standard peripheral we're dropping its support for good.
Patrick Delaunay [Wed, 27 Feb 2019 14:20:38 +0000 (15:20 +0100)]
Convert CONFIG_ENV_SPI_* to Kconfig
This converts the following to Kconfig:
CONFIG_ENV_SPI_BUS
CONFIG_ENV_SPI_CS
CONFIG_ENV_SPI_MAX_HZ
CONFIG_ENV_SPI_MODE
Most of time these value are not needed, CONFIG_SF_DEFAULT
with same value is used, so I introduced CONFIG_USE_ENV_SPI_*
to force the associated value for the environment.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Define the function board_spi_cs_gpio only when needed,
only called in drivers/spi/mxc_spi.c.
That avoid compilation issue for tqma6s_wru4_mmc_defconfig
when CONFIG_SF_DEFAULT_BUS and CONFIG_SF_DEFAULT_CS are not
defined (CMD_SF not defined) after migration in KConfig.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Wed, 27 Feb 2019 14:20:34 +0000 (15:20 +0100)]
exynos: replace CONFIG_ENV_SPI_BASE by CONFIG_SYS_SPI_BASE
Replace CONFIG_ENV_SPI_BASE by the better CONFIG_SYS_SPI_BASE
(it is not the location for environment but the location for U-Boot)
and, as it is the only platform with use this define, remove
it from whitelist.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Tom Rini [Mon, 25 Mar 2019 21:26:38 +0000 (17:26 -0400)]
Merge branch '2019-03-25-master-imports'
- 3 bugfixes:
- mmc: Align MMC_TRACE with tiny printf
- scripts/Makefile.extrawarn: Silence more DTC warnings
- rsa: check that pointer checksum isn't NULL before using it
Marek Vasut [Mon, 18 Mar 2019 22:43:10 +0000 (23:43 +0100)]
mmc: tmio: Clamp SD_SECCNT to 16bit values on 16bit IP
On 16bit variants of the TMIO SD IP, the SECCNT register can only be
programmed to 16bit values, while on the 32bit and 64bit variants it
can be programmed to 32bit values. The SECCNT register indicates the
maximum number of blocks in a continuous transfer. Hence, limit the
maximum continuous transfer block count to 65535 blocks on 16bit
variants of the TMIO IP and to BIT(32)-1 blocks on 32bit and 64bit
variants.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Marek Vasut [Mon, 18 Mar 2019 04:11:42 +0000 (05:11 +0100)]
clk: renesas: Fix SDH clock divider decoding on Gen2
The gen2_clk_get_sdh_div() function is supposed to look up the
$val value read out of the SDCKCR register in the supplied table
and return the matching divider value. The current implementation
was matching the value from SDCKCR on the divider value in the
table, which is wrong. Fix this and rework the function a bit
to make it more readable.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
projects / u-boot.git / log
