Michal Simek [Thu, 26 Mar 2020 14:01:29 +0000 (15:01 +0100)]
net: macb: Fix incorrect write function name when MACB_ZYNQ is enabled.
When MACB_ZYNQ is enabled there is compilation warnings
drivers/net/macb.c: In function ‘_macb_init’:
drivers/net/macb.h:675:33: error: ‘MACB_DMACFG’ undeclared (first use in this function);
did you mean ‘MACB_MCF’?
writel((value), (port)->regs + MACB_##reg)
^~~~~
It has been caused by changing macros name by commit below.
Fixes: 6c636514d499 ("net: macb: sync header definitions as taken from Linux") Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Rasmus Villemoes [Tue, 11 Feb 2020 15:20:25 +0000 (15:20 +0000)]
mpc8xxx_spi: implement real ->set_speed
Not all boards have the same CSB frequency, nor do every SPI slave
necessarily support running at 16.7 MHz. So implement ->set_speed;
that also allows using a smaller PM (i.e., 0) for slaves that do
support a higher speed.
Based on work by Klaus H. Sørensen.
Cc: Klaus H. Sorensen <khso@prevas.dk> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Rasmus Villemoes [Tue, 11 Feb 2020 15:20:25 +0000 (15:20 +0000)]
mpc8xxx_spi: always use 8-bit characters, don't read or write garbage
There are a few problems with the current driver.
First, it unconditionally reads from dout/writes to din whether or not
those pointers are NULL. So for example a simple "sf probe" ends up
writing four bytes at address 0:
Finally, when the bitlen is 24 mod 32 (e.g. requesting to read 3 or 7
bytes), the last three bytes and up being the wrong ones, since the
driver does a full 32 bit read and then shifts the wrong byte out:
Fix all of that by always using a character size of 8, and reject
transfers that are not a whole number of bytes. While it ends being
more work for the CPU, we're mostly bounded by the speed of the SPI
bus, and we avoid writing to the mode register in every loop.
Based on work by Klaus H. Sørensen.
Cc: Klaus H. Sorensen <khso@prevas.dk> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Rasmus Villemoes [Tue, 11 Feb 2020 15:20:24 +0000 (15:20 +0000)]
mpc8xxx_spi: put max_cs to use
Currently, max_cs is write-only; it's just set in
mpc8xxx_spi_ofdata_to_platdata and not otherwise used.
My mpc8309 was always resetting during an "sf probe 0". It turns out
dm_gpio_set_dir_flags() was being called with garbage, since nothing
had initialized priv->gpios[0] - our device tree used "cs-gpios"
rather than "gpios", so gpio_request_list_by_name() had returned 0.
That would have been a lot easier to figure out if the chip select
index was sanity checked, so rename max_cs to cs_count, and reject a
xfer with a too large cs index.
gpio/mpc83xx_spisel_boot.c: gpio driver for SPISEL_BOOT signal
Some SoCs in the mpc83xx family, e.g. mpc8309, have a dedicated spi
chip select, SPISEL_BOOT, that is used by the boot code to boot from
flash.
This chip select will typically be used to select a SPI boot
flash. The SPISEL_BOOT signal is controlled by a single bit in the
SPI_CS register.
Implement a gpio driver for the spi chip select register. This allows a
spi driver capable of using gpios as chip select, to bind a chip select
to SPISEL_BOOT.
It may be a little odd to do this as a GPIO driver, since the signal
is neither GP or I, but it is quite convenient to present it to the
spi driver that way. The alternative it to teach mpc8xxx_spi to handle
the SPISEL_BOOT signal itself (that is how it's done in the linux
kernel, see commit 69b921acae8a)
Signed-off-by: Klaus H. Sorensen <khso@prevas.dk> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Rasmus Villemoes [Tue, 28 Jan 2020 12:04:34 +0000 (12:04 +0000)]
gpio: mpc8xxx: don't do RMW on gpdat register when setting value
The driver correctly handles reading back the value of an output gpio
by reading from the shadow register for output, and from gpdat for
inputs.
Unfortunately, when setting the value of some gpio, we do a RMW cycle
on the gpdat register without taking the shadow register into account,
thus accidentally setting other output gpios (at least those whose
value cannot be read back) to 0 at the same time.
When changing a gpio from input to output, we still need to make sure
it initially has the requested value. So, the procedure is
- update the shadow register
- compute the new gpdir register
- write the bitwise and of the shadow and new gpdir register to gpdat
- write the new gpdir register
Rasmus Villemoes [Tue, 28 Jan 2020 12:04:33 +0000 (12:04 +0000)]
gpio: mpc8xxx: don't modify gpdat when setting gpio as input
Since some chips don't support reading back the value of output gpios
from the gpdat register, we should not do a RMW cycle (i.e., the
clrbits_be32) on the gpdat register when setting a gpio as input, as
that might accidentally change the value of some other (still
configured as output) gpio.
The extra indirection through mpc8xxx_gpio_set_in() does not help
readability, so just fold the gpdir update into
mpc8xxx_gpio_direction_input().
Kuldeep Singh [Thu, 12 Mar 2020 09:43:00 +0000 (15:13 +0530)]
configs: lx2160a: Access flash memory as per spi-mem
MC_INIT and BOOT command currently access spi-nor flash memory directly.
As per spi-mem framework, flash memory access via absolute addresses is
no more possible. Use flash APIs to access memory instead of directly
using it.
Kuldeep Singh [Mon, 2 Mar 2020 11:09:19 +0000 (16:39 +0530)]
arm: dts: lx2160aqds: Add FSPI node properties
lx2160a-qds has 2 micron "mt35xu512aba" flashes of size 64M each
connected on A0 and B1 i.e on CS0 and CS3. Since flashes are connected
on different buses, only one flash can be probed at a time.
Add fspi node properties aligned with LX2160A-RDB fspi properties.
Biwen Li [Fri, 20 Mar 2020 10:26:14 +0000 (18:26 +0800)]
configs: ls1012afrwy: adjust env kernel_addr_r
Adjust environment kernel_addr_r from 0x96000000 to 0x92000000
to fix a bug that failed to boot kernel for ls1012afrwy with 512MiB RAM,
=> tftpboot $kernel_addr_r Image (Image size is 36 MiB)
TFTP error: trying to overwrite reserved memory...
Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Yangbo Lu [Tue, 3 Mar 2020 02:32:51 +0000 (10:32 +0800)]
configs: disable eMMC HS200 support on layerscape platforms
The eMMC HS200 speed mode on Layerscape platforms has not been
supported properly. The eSDHC clock tuning has not been implemented
by now. So disable it until it is supported properly in case of
any potential issues.
Ran Wang [Fri, 7 Feb 2020 04:42:08 +0000 (12:42 +0800)]
configs: arm: ls1021aiot: enable CONFIG_DM_USB support
Enable CONFIG_DM_USB to remove below compile warning:
===================== WARNING ======================
This board does not use CONFIG_DM_USB. Please update
the board to use CONFIG_DM_USB before the v2019.07 release.
Failure to update by the deadline may result in board removal.
See doc/driver-model/migration.rst for more info.
====================================================
Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Ran Wang [Fri, 7 Feb 2020 04:42:07 +0000 (12:42 +0800)]
configs: arm64: ls1012afrdm Enable CONFIG_BLK
With DM_USB enabled, enable CONFIG_BLK to remove this
compile warning for ls1012afrdm based targets:
===================== WARNING ======================
This board does not use CONFIG_DM_USB. Please update
the board to use CONFIG_DM_USB before the v2019.07 release.
Failure to update by the deadline may result in board removal.
See doc/driver-model/migration.rst for more info.
====================================================
Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Yuantian Tang [Fri, 20 Mar 2020 06:37:07 +0000 (14:37 +0800)]
armv8: ls1028a: clean up the environment variables
Move the environment variables from command head file to
ls1028ardb specific head file so that they will not mess
up with ls1028aqds board.
Also updated some variable slightly.
There is no function change by this patch.
Yangbo Lu [Thu, 19 Mar 2020 07:18:54 +0000 (15:18 +0800)]
board: fsl: lx2160a: fix SDHC1_DAT4 signal routing
The SDHC1_DAT4 signal could be routes to SDHC1_VS or SDHC1
adapter slot for SDHC1 usage. When SDHC1 is selected in RCW,
do not force to route it to SDHC1 adapter slot if find it
has already been configued for SDHC1_VS.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Vladimir Oltean [Fri, 13 Mar 2020 14:53:06 +0000 (16:53 +0200)]
pci-host-ecam-generic: access config space independent of system-wide bus id
The pci-host-ecam-generic code assumes that the ECAM is the first PCI
bus in the system to be probed. Therefore, the system-wide bus number
allocated by U-Boot in sequence for it is going to be zero, which
corresponds to the memory-mapped config spaces found within it.
Reuse the logic from other PCI bus drivers, and assume that U-Boot will
allocate bus numbers in sequence for all buses within the current ECAM.
So the base number of the bus needs to be subtracted when indexing the
correct config space.
Fixes: 3675cb044e68 ("PCI: Add driver for a 'pci-host-ecam-generic' host controller") Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
The correct setting for the RGMII ports on LS1046ARDB is to
enable delay on both Rx and Tx so the interface mode used must
be PHY_INTERFACE_MODE_RGMII_ID. There is a pull-up that turns
on Rx internal delay by default and the u-boot does not
override that (yet) so in u-boot the interface is functional.
In Linux the PHY driver is clearing the Rx delay for the
"rgmii-txid" mode and the reception does not work.
Changing the RGMII mode to internal delay here ensures that
device tree fix-ups for the PHY connection type turn on both
Tx and Rx internal delay in Linux.
The correct setting for the RGMII ports on LS1043ARDB is to
enable delay on both Rx and Tx so the interface mode used must
be PHY_INTERFACE_MODE_RGMII_ID. There is a pull-up that turns
on Rx internal delay by default and the u-boot does not
override that (yet) so in u-boot the interface is functional.
In Linux the PHY driver is clearing the Rx delay for the
"rgmii-txid" mode and the reception does not work.
Changing the RGMII mode to internal delay here ensures that
device tree fix-ups for the PHY connection type turn on both
Tx and Rx internal delay in Linux.
Setting fdt_high and initrd_high to 0xffffffffffffffff leads to
various difficulty to resolve bugs.
Remove them and use bootm_size instead to safely contain a kernel,
device tree and initrd for relocation.
Setting fdt_high and initrd_high to 0xffffffffffffffff leads to
various difficulty to resolve bugs.
Remove them and use bootm_size instead to safely contain a kernel,
device tree and initrd for relocation.
Alison Wang [Mon, 3 Feb 2020 07:25:19 +0000 (15:25 +0800)]
ls1021a: Set CONFIG_SYS_BOOTMAPSZ to the memory for relocation
This patch sets CONFIG_SYS_BOOTMAPSZ to the amount of memory available
to safely contain a kernel, device tree and initrd for relocation. The
way to set fdt_high as 0xffffffff to disable device tree relocation is
removed.
Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Harald Seiler [Thu, 26 Mar 2020 17:07:27 +0000 (18:07 +0100)]
test/py: mmc: Fix 'mmc info' testcase
Commit 41e30dcf8796 ("cmd: mmc: Make Mode: printout consistent") fixed
the layout of `mmc info` output. Reflect this change in the respective
testcase.
Also fix a typo in the documentation.
Fixes: 41e30dcf8796 ("cmd: mmc: Make Mode: printout consistent") Signed-off-by: Harald Seiler <hws@denx.de> Acked-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Miquel Raynal [Wed, 18 Mar 2020 16:22:55 +0000 (17:22 +0100)]
rockchip: mkimage: Use an existing macro instead of a decimal value
Depending on the SoC, a header of four characters is prepended to the
image. There is already a macro defining the number of characters:
RK_SPL_HDR_SIZE, so use it instead of hardcoding "4".
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This happens because the above commit missed to include the
"rockchip-u-boot.dtsi" for rv1108, so include this file
like it done for other Rockchip SoC dtsi's.
Fixes: 79030a486128 ("rockchip: Add Single boot image (with binman, pad_cat)") Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Otavio Salvador [Fri, 13 Mar 2020 17:42:46 +0000 (14:42 -0300)]
elgin-rv1108: Use rk_board_late_init() for GPIO settings
Since commit 8e9a8d0d0c8c ("rockchip: elgin-rv1108: use board_early_init_f
for per-boar init") the function that configure the board GPIOs is no
longer called since CONFIG_BOARD_EARLY_INIT_F=y is not selected.
These GPIOs do not need to be configured in such early stagem, so change it
to rk_board_late_init() and also select CONFIG_BOARD_LATE_INIT=y
to fix the regression.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Signed-off-by: Fabio Berton <fabio.berton@ossystems.com.br> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Peter Robinson [Mon, 2 Mar 2020 07:57:55 +0000 (07:57 +0000)]
rockchip: Change keyboard input from CrOS EC keyboard to a USB keyboard
These boards aren't ChromeOS devices so won't have a cros-ec-keyb
input as it's the keyboard available via the ChromeOS Embedded
Controller. Update them to use a USB keyboard which would actually
be available. Also enable the usb keyboard option for those devices
that don't have it enabled already.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Kristian Amlie [Tue, 25 Feb 2020 17:22:16 +0000 (18:22 +0100)]
vexpress_ca9x4: Enable use of correct DTB file and restore EFI loader.
EFI was disabled in f95b8a4b5f64f because of the missing DTB file,
and indeed, the DTB file is required to load recent versions of GRUB
(2.04) correctly.
Signed-off-by: Kristian Amlie <kristian.amlie@northern.tech>
Tom Rini [Mon, 23 Mar 2020 14:14:31 +0000 (10:14 -0400)]
Merge tag 'efi-2020-04-rc4-5' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2020-04-rc4 (5)
This series contains bug fixes for the UEFI sub-system:
* report correct variable length in GetNextVariable()
* correct copying direction if freestanding memmove()
* remove const for parameter of GetNextVariableName()
* correct function descriptions
Andre Przywara [Thu, 20 Feb 2020 17:51:15 +0000 (17:51 +0000)]
sunxi: Remove no longer needed default options from defconfigs
Now that those common Allwinner config symbols are defined automatically
for all boards in their Kconfig files, we can remove the now redundant
definitions from the boards' _defconfig files.
Some boards had a differing definiton for some of those symbols, it
looks like mostly to "merge races" when the symbol was introduced (new
board *_defconfig file missed the "add symbol to all files" patch).
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # Amarula A64-Relic Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Andre Przywara [Thu, 20 Feb 2020 17:51:14 +0000 (17:51 +0000)]
sunxi: Move common defconfig options to Kconfig
Some config symbols are found in *almost* every _defconfig file for
Allwinner boards, because those options are actually a platform choice,
and not a per-board decision.
Some of these options are older, some have recently been added.
Move those options to be set for all Allwinner boards in their
respective Kconfig files.
The rationales are as follows:
- NR_DRAM_BANKS: All Allwinner SoC map DRAM at one contiguous region of
address space only, starting at 1 GB. So it's always one bank.
- SPL_{DOS,EFI}_PARTITION: The Allwinner SPL does only support raw MMC
accesses, we don't care about filesystems or partitions in there, so
there is no need to define those symbols at all.
- USE_PREBOOT: We start USB early when a keyboard is configured, using the
preboot env variable, so we need to set this variable.
- SYS_RELOC_GD_ENV_ADDR: We don't specify any ENV_ADDR, so need this
symbol to be set (according to 8d8ee47e03e).
- SYS_USB_EVENT_POLL_VIA_INT_QUEUE: According to commit eab9433aa55428,
specifying this reduces the latency of the USB keyboard handling, so
this was formerly enabled in config headers for all Allwinner boards.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # Amarula A64-Relic Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Andre Przywara [Tue, 28 Jan 2020 00:46:43 +0000 (00:46 +0000)]
sunxi: SPL SPI: Add SPI boot support for the Allwinner H6 SoC
The Allwinner H6 SoC uses a quite different memory map, also changes the
clocks quite a bit. This requires some changes to the SPL SPI routine,
which hardcodes these values so far.
Using the just introduced helper functions to determine base address
and SPI controller generation, we can cover some of these differences
easily.
The clock setup is different, so requires some explicit code changes
there (reset and clock gate in one register at a different address).
Also we need to change the pinmux function to use a different set of
pins that the H6 uses for SPI0.
Eventually we can enable the H6 to use SPI booting in Kconfig.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Andre Przywara [Tue, 28 Jan 2020 00:46:42 +0000 (00:46 +0000)]
sunxi: SPL SPI: Add SPI boot support for the Allwinner R40 SoC
Now that we can easily select an SoC specific SPI0 base address, adding
support for the Allwinner R40 is fairly trivial:
We set the base address, add this SoC to the ones that use PC23 and
enable it in Kconfig.
This allows booting from SPI flash on R40 boards.
Tested on a Bananapi M2 Berry with SPI flash connected to the header pins.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Andre Przywara [Tue, 28 Jan 2020 00:46:41 +0000 (00:46 +0000)]
sunxi: SPL SPI: Introduce is_sun6i_gen_spi()
So far we were using the CONFIG_SUNXI_GEN_SUN6I symbol to select between
the two SPI controller generations used on Allwinner SoCs. This is a
convenience symbol to roughly differentiate between "older" and "newer"
generation of SoCs.
The H6 SoCs is the newest SoC so far, but is sufficiently different to
not define this symbol. However it is using a SPI controller compatible
to the "new gen" SoCs.
To prepare for H6 support, we replace the check for this single symbol
with an explicit function, which can later be extended.
For now we just return CONFIG_SUNXI_GEN_SUN6I in there, so this does not
create a functional change.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Andre Przywara [Tue, 28 Jan 2020 00:46:40 +0000 (00:46 +0000)]
sunxi: SPL SPI: Split off SPI0 base address
So far on all supported Allwinner SoCs we find the old generation SPI
controller always at address 0x1c05000, and the new generation one at
0x1c68000. However the Allwinner R40 SoC has a new generation SPI at
the old address, and the H6 uses a completely different address.
So split off the base address from the respective SPI registers, by
changing the #defines to just contain offsets.
The base address is provided by a function, so it can easily be extended
later when support for those SoCs materialises.
This does not change the code size (since the toolchain is clever enough
to optimise this properly), also does not bring any functional change at
this point.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tom Rini [Wed, 18 Mar 2020 11:48:39 +0000 (07:48 -0400)]
Merge tag 'efi-2020-04-rc4-4' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2020-04-rc4 (4)
This series fixes several bugs:
* consider the /reserved-memory node in the device tree
* consider memory reservations created in ft_board_setup()
* correct output of 'efidebug memmap' on the sandbox
* correct the definition of efi_capsule_header()
Furthermore some definitions needed for future patches are added to
header files.
Using memcpy() for some MMIO access is generally frowned upon and might
break things on some platforms. Allwinner H3, which fails to boot, being
an example here.
Moreover, fields being accessed are naturally aligned and warnings
produced by GCC have been quiesced for some time already by:
AKASHI Takahiro [Tue, 17 Mar 2020 02:12:37 +0000 (11:12 +0900)]
efi_loader: correct a definition of struct efi_capsule_header
See UEFI specification, section 8.5.3.
In addition, the structure, efi_capsule_header, should be "packed"
as it is a serialized binary format in a capsule file.
AKASHI Takahiro [Tue, 17 Mar 2020 02:12:36 +0000 (11:12 +0900)]
efi_loader: export a couple of protocol related functions
This is a preparatory patch.
Those functions will be used in an implementation of UEFI firmware
management protocol as part of my capsule update patch.
Atish Patra [Sat, 14 Mar 2020 00:11:30 +0000 (17:11 -0700)]
cmd: bootefi: Parse reserved-memory node from DT
Currently, bootefi only parses memory reservation block to setup
EFI reserved memory mappings. However, it doesn't parse the
reserved-memory[1] device tree node that also can contain the
reserved memory regions.
Add capability to parse reserved-memory node and update the EFI memory
mappings accordingly.
Addresses in the sandbox's device tree are in the sandbox's virtual address
space. If we want to compare memory reservations in the device-tree with
the output of 'efidebug memmap', we need to convert back to this address
space.
Adjust the output of the 'efidebug memmap' command.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
efi_loader: create reservations after ft_board_setup
Some memory reservations are made in ft_board_setup(). Ensure that we
create reserved memory map entries after ft_board_setup().
The downside of this patch is that if bootefi is called multiple times with
an devicetree argument superfluous reservations for the old copies of the
device tree will exist. But that is still better than missing a reservation.
Deleting the superfluous reservations is not possible because reservations
in the memory map are rounded to page size and may be coallesced.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Bin Meng [Tue, 10 Mar 2020 02:35:30 +0000 (19:35 -0700)]
riscv: Introduce a new config for SBI v0.1
We now have SBI v0.2 which is more scalable and extendable to handle
future needs for RISC-V supervisor interfaces.
Introduce a new config and move all SBI v0.1 code under that config.
This allows to implement the new replacement SBI extensions cleanly
and remove v0.1 extensions easily in future. Currently, the config
is enabled by default. Once all M-mode software, with v0.1, is no
longer in use, this config option and all relevant code can be easily
removed.
This commit is inspired from Linux kernel patch:
https://patchwork.kernel.org/patch/11407361/
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
projects / u-boot.git / log
