- Bug fixes and updates on ls2088a,ls1028a, ls1046a, ls1043a, ls1012a
- lx2-watchdog support
- layerscape: pci-endpoint support, spin table relocation fixes and
cleanups
- fsl-crypto: RNG support and bug fixes
Tom Rini [Mon, 27 Jul 2020 15:11:27 +0000 (11:11 -0400)]
travis: Install pyelftools via pip
With the migration to python3 for all of our tests, we need to install
pyelftools via pip now rather than the system tools as they will
otherwise not be present in our virtualenv.
Signed-off-by: Tom Rini <trini@konsulko.com>
---
Changes in v2: Switch to pip
Neil Armstrong [Tue, 21 Jul 2020 11:41:14 +0000 (13:41 +0200)]
serial: meson: handle RX errors
This checks and handles RX errors on the Amlogic UART controller
after experiencing errors on the Khadas VIM3 & VIM3L when UART AO A
lines are not connected.
When the RX line is not connected, the first byte is erroneous and breaks
the U-Boot autoboot, breaking automatic boot.
This checks and drops any erroneous RX byte on pending and getc callbacks
to avoid returning true to pending when an error byte is in the FIFO.
Fixes: bfcef28ae4 ("arm: add initial support for Amlogic Meson and ODROID-C2") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Guillaume La Roque <glaroque@baylibre.com>
Tom Rini [Mon, 27 Jul 2020 13:25:53 +0000 (09:25 -0400)]
Merge branch '2020-07-27-misc-env-improvements'
- Assorted environment fixes.
- Enhance environment in MMC and controlled via OF_CONTROL
- Allow for environment in FAT to use the same device we boot from
rather than be hard-coded.
According to Server Base System Architecture (SBSA) specification,
the SBSA Generic Watchdog has two stage timeouts: the first signal
(WS0) is for alerting the system by interrupt, the second one (WS1) is a
real hardware reset.
More details about the hardware specification of this device:
ARM DEN0029B - Server Base System Architecture (SBSA)
This driver can operate ARM SBSA Generic Watchdog as a single stage
In the single stage mode, when the timeout is reached, your system
will be reset by WS1. The first signal (WS0) is ignored.
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Xiaowei Bao [Thu, 9 Jul 2020 15:31:37 +0000 (23:31 +0800)]
pci_ep: layerscape: Add the workaround for errata A-009460
The VF_BARn_REG register's Prefetchable and Type bit fields
are overwritten by a write to VF's BAR Mask register.
workaround: Before writing to the VF_BARn_MASK_REG register,
write 0b to the PCIE_MISC_CONTROL_1_OFF register.
lx2160a rev2 requires 4KB space for type0 and 4KB
space for type1 iATU window. Increase configuration
size to 8KB to have sufficient space for type0
and type1 window.
Biwen Li [Thu, 2 Jul 2020 03:13:04 +0000 (11:13 +0800)]
freescale: ls1043aqds: drop ifdef CONFIG_SYS_I2C
- Drop ifdef CONFIG_SYS_I2C to initialize
baudrate of i2c
- Drop warning of i2c_early_init_f as follows,
warning: implicit declaration of function 'i2c_early_init_f'; did you
mean 'arch_early_init_r'? [-Wimplicit-function-declaration]
Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Biwen Li [Thu, 2 Jul 2020 03:13:02 +0000 (11:13 +0800)]
freescale: ls1046aqds: drop ifdef CONFIG_SYS_I2C
- Drop ifdef CONFIG_SYS_I2C to initialize
baudrate of i2c
- Drop warning of i2c_early_init_f as follows,
warning: implicit declaration of function 'i2c_early_init_f'; did you
mean 'arch_early_init_r'? [-Wimplicit-function-declaration]
Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Kuldeep Singh [Thu, 25 Jun 2020 07:26:22 +0000 (12:56 +0530)]
configs: ls1012a: Increase CONFIG_SYS_MALLOC_LEN value
Previous attempt to increase CONFIG_SYS_MALLOC_LEN was done in commit c084a8edf4e2 ("configs: ls1012a: Increase CONFIG_SYS_MALLOC_LEN size")
which increased malloc memory to ~1M.
PFE firmware alone requires 3M of dynamic memory allocation and
therefore, increase the config value to a larger value i.e 5M. This size
should be enough as of now to accommodate further memory requirements.
Yangbo Lu [Wed, 17 Jun 2020 10:08:58 +0000 (18:08 +0800)]
Move eSDHC adapter card identification to board files
The eSDHC adapter card identification and multiplexing configuration
through FPGA had been implemented in both common mmc driver and
fsl_esdhc driver. However it is proper to move these code to board
files and do it during board initialization. The FPGA registers are
also board specific.
This patch is to move eSDHC adapter card identification and
multiplexing configuration from mmc driver to specific board files.
And the option CONFIG_FSL_ESDHC_ADAPTER_IDENT is no longer needed.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
[Rebased, Removed T1040QDS change as board does not exist] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
The correct setting for the RGMII ports on LS1012ARDB is to
enable delay on both Rx and Tx so the interface mode used should
be PHY_INTERFACE_MODE_RGMII_ID
The compiler emits a "stur x1, [x0, #12]". x1 is might just be 32 bit
aligned pointer. Remove the unused u64 element from the union to drop
the minimal alignment to 32 bit. Also remove the union, because it is
no more needed.
Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Mon, 1 Jun 2020 19:53:36 +0000 (21:53 +0200)]
armv8: layerscape: rework spin table
There are two issues:
(1) The spin table doesn't convert the endianness of the jump address.
Although there is code for it, the result isn't used at all (x0).
(2) If something goes wrong, the function returns. But that doesn't
make sense at all.
Use the actual converted jump address as destination to fix. If
there is an error, jump to a trap loop. And rearrange the code exception
level switching code to make it smaller and clearer.
This reduces the size of the spin table code section from 696 bytes to
424 bytes. If CONFIG_ARMV8_SWITCH_TO_EL1 the code size reduced from 696
bytes to 632 bytes.
Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Mon, 1 Jun 2020 19:53:35 +0000 (21:53 +0200)]
armv8: layerscape: relocate spin table if EFI_LOADER is enabled
On ARM64, a 64kb region is reserved for the runtime services code.
Unfortunately, this code overlaps with the spin table code, which also
needs to be reserved. Thus now that the code is relocatable, allocate a
new page from EFI, copy the spin table code into it, update any pointers
to the old region and the start the secondary CPUs.
Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Mon, 1 Jun 2020 19:53:34 +0000 (21:53 +0200)]
armv8: layerscape: clean exported symbols in spintable.S
Add a new variable secondary_boot_code_start, which holds a pointer to
the start of the spin table code. This will help to relocate the code
section. While at it, move the size variable from the end to the
beginning so there is a common section for the variables. Remove any
other symbols.
Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Mon, 1 Jun 2020 19:53:28 +0000 (21:53 +0200)]
armv8: layerscape: load function pointer using ADR
Don't use LDR to load a pointer to a function. This will generate a
literal which cannot be relocated. Use ADR which is PC-relative and
therefore can easily be relocated.
Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Mon, 1 Jun 2020 19:53:27 +0000 (21:53 +0200)]
armv8: layerscape: move spin table into own module
Move it out of lowlevel.S into spintable.S. On layerscape, the secondary
CPUs are brought up in main u-boot. This will make it possible to only
compile the spin table code for the main u-boot and omit it in SPL.
This saves about 720 bytes in the SPL.
Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Mon, 1 Jun 2020 19:53:26 +0000 (21:53 +0200)]
armv8: layerscape: properly use CPU_RELEASE_ADDR
The generic armv8 code already has support to bring up the secondary
cores. Thus, don't hardcode the jump in the layerscape lowlevel_init to
the spin table code; instead just return early and let the common armv8
code handle the jump. This way we can actually use the CPU_RELEASE_ADDR
feature.
Signed-off-by: Michael Walle <michael@walle.cc>
[Rebased, Removed kontron_sl28.h change as file does not exist] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Mon, 1 Jun 2020 19:53:24 +0000 (21:53 +0200)]
armv8: layerscape: fix spin-table support
Spin tables are broken with bootefi. This is because - in contrast to
the booti call chain - there is no call to smp_kick_all_cpus(). Due to
this missing call the secondary CPUs are never released from their "wait
for interrupt state", see secondary_boot_func() in lowlevel.S.
Originally, this "wait for interrupt" is there to make sure, the spin
table is cleared before the secondary cores read it for the first time.
But the boot flow for the layerscape architecture is different from
that. The CPUs are release from their BootROM _after_ U-Boot's
spin-table is cleared, see fsl_layerscape_wake_seconday_cores() in mp.c.
Thus, there is no need to wait for this interrupt and no need for
kicking all cores on cpu_release. An atomic 64bit write to the
spin-table and a "sev" is sufficient.
Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Kuldeep Singh [Thu, 28 May 2020 06:12:53 +0000 (11:42 +0530)]
net: pfe_eth: Use spi_flash_read API to access flash memory
Current PFE firmware access spi-nor memory directly. New spi-mem
framework does not support direct memory access. So, let's use
spi_flash_read API to access memory instead of directly using it.
Michael Walle [Sat, 9 May 2020 23:20:11 +0000 (01:20 +0200)]
armv8: ls1028a: move FSL_LAYERSCAPE to kconfig
CONFIG_FSL_LAYERSCAPE is available in kconfig. There is no need to
define it per board; the ls1028a_common.h is really board dependent and
only fits to the NXP eval boards. Instead select CONFIG_FSL_LAYERSCAPE
when ARCH_LS1028A is selected.
Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Vladimir Oltean [Mon, 4 May 2020 08:24:26 +0000 (11:24 +0300)]
fsl_dspi: Introduce DT bindings for CS-SCK and SCK-CS delays
Communication with some SPI slaves just won't cut it if these delays
(before the beginning, and after the end of a transfer) are not added to
the Chip Select signal.
These are a straight copy from Linux:
Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
drivers/spi/spi-fsl-dspi.c
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
[Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Simon Glass [Sat, 25 Jul 2020 21:11:19 +0000 (15:11 -0600)]
binman: Don't change the descriptor in tests
At present testPackX86RomMeNoDesc removes the contents of the
descriptor.bin file and testPackX86RomMeMissingDesc removes the file
completely.
If a test that relies on this file happens to run after it is removed, it
will not work. Since we have no control over the selecting of tests that
run in parallel and series, we must avoid changing the files.
Patrick Delaunay [Mon, 15 Jun 2020 08:38:57 +0000 (10:38 +0200)]
env: mmc: add redundancy support in mmc_offset_try_partition
Manage 2 copy at the end of the partition selected by config
"u-boot,mmc-env-partition" to save the U-Boot environment,
with CONFIG_ENV_SIZE and 2*CONFIG_ENV_SIZE offset.
This patch allows to support redundancy (CONFIG_ENV_OFFSET_REDUND).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Mon, 15 Jun 2020 08:38:55 +0000 (10:38 +0200)]
env: mmc: allow support of mmc_get_env_dev with OF_CONTROL
Use the weak function mmc_get_env_dev in mmc_offset_try_partition
function to allow dynamic selection of mmc device to use
and no more use directly the define CONFIG_SYS_MMC_ENV_DEV.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Fri, 19 Jun 2020 12:03:35 +0000 (14:03 +0200)]
cmd: env: check real location for env info command
Check the current ENV location, dynamically provided by the weak
function env_get_location to be sure that the environment can be
persistent.
The compilation flag ENV_IS_IN_DEVICE is not enough when the board
dynamically select the available storage location (according boot
device for example).
This patch solves issue for stm32mp1 platform, when the boot device
is USB.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
Patrick Delaunay [Fri, 19 Jun 2020 12:03:34 +0000 (14:03 +0200)]
cmd: env: add option for quiet output on env info
The "env info" can be use for test with -d and -p parameter,
in scripting case the output of the command is not needed.
This patch allows to deactivate this output with a new option "-q".
For example, we can save the environment if default
environment is used and persistent storage is managed with:
if env info -p -d -q; then env save; fi
Without the quiet option, I have the unnecessary traces
First boot:
Default environment is used
Environment can be persisted
Saving Environment to EXT4... File System is consistent
Next boot:
Environment was loaded from persistent storage
Environment can be persisted
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
Patrick Delaunay [Wed, 24 Jun 2020 07:27:25 +0000 (09:27 +0200)]
env: correct overflow check of env_has_init size
Correct the overflow check of the bit-field env_has_init with
the max value of env_location= ENVL_COUNT and no more with the
size of env_locations.
This bit-field is indexed by this enumerate and not by the position in
the env_locations (only used in env_get_location) and the
2 values are different, depending of thea ctivated CONFIG_ENV_IS_ options.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Dave Gerlach [Thu, 16 Jul 2020 04:39:59 +0000 (23:39 -0500)]
dm: soc: Introduce soc_ti_k3 driver for TI K3 SoCs
Introduce an soc_ti_k3_driver that allows identification and selection
of SoC specific data based on the JTAG ID register for device
identification, as described for AM65x[0] and J721E[1] devices.
Dave Gerlach [Thu, 16 Jul 2020 04:39:57 +0000 (23:39 -0500)]
dm: soc: Introduce UCLASS_SOC for SOC ID and attribute matching
Introduce UCLASS_SOC to be used for SOC identification and attribute
matching based on the SoC ID info. This allows drivers to be provided
for SoCs to retrieve SoC identifying information and also for matching
device attributes for selecting SoC specific data.
This is useful for other device drivers that may need different
parameters or quirks enabled depending on the specific device variant in
use.
Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Dave Gerlach [Thu, 16 Jul 2020 04:39:56 +0000 (23:39 -0500)]
doc: Add new doc for soc ID driver model
Add a new documentation file for UCLASS_SOC and its usage to describe
the SoC Device ID framework that allows SoC identification and device
data matching.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
projects / u-boot.git / log
