From: Masahisa Kojima <masahisa.kojima@linaro.org>
Date: Tue, 17 May 2022 08:41:38 +0000 (+0900)
Subject: spi: synquacer: DMSTART bit must not be set while transferring
X-Git-Url: http://git.dujemihanovic.xyz/%22/img/sics.gif/%22/static/git-favicon.png?a=commitdiff_plain;h=de9f2c9c2ed8ee4ffadc3909a46c17888fed619f;p=u-boot.git

spi: synquacer: DMSTART bit must not be set while transferring

DMSTART bit must not be set while there is active transfer.
This commit sets the DMSTART bit only when the transfer begins.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com>
Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
---

diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c
index f1422cf893..5e1b3aedc7 100644
--- a/drivers/spi/spi-synquacer.c
+++ b/drivers/spi/spi-synquacer.c
@@ -330,9 +330,11 @@ static int synquacer_spi_xfer(struct udevice *dev, unsigned int bitlen,
 	writel(~0, priv->base + RXC);
 
 	/* Trigger */
-	val = readl(priv->base + DMSTART);
-	val |= BIT(TRIGGER);
-	writel(val, priv->base + DMSTART);
+	if (flags & SPI_XFER_BEGIN) {
+		val = readl(priv->base + DMSTART);
+		val |= BIT(TRIGGER);
+		writel(val, priv->base + DMSTART);
+	}
 
 	while (busy & (BIT(RXBIT) | BIT(TXBIT))) {
 		if (priv->rx_words)