From: Ley Foon Tan <ley.foon.tan@intel.com>
Date: Fri, 10 Jul 2020 12:55:21 +0000 (+0800)
Subject: clk: agilex: Add clock enable support
X-Git-Tag: v2025.01-rc5-pxa1908~2181^2~28
X-Git-Url: http://git.dujemihanovic.xyz/%22/img/sics.gif/%22/static/git-favicon.png?a=commitdiff_plain;h=d3e829b6183a857b9f5b7626ae6af2eaff95c555;p=u-boot.git

clk: agilex: Add clock enable support

Some drivers probing failed if clock enable function is not supported in
clock driver. So, add clock enable function to clock driver to solve it.

Return 0 (success) for *.enable function because all clocks are enabled
by default in clock driver probe.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---

diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c
index d7402999ef..36a224d762 100644
--- a/drivers/clk/altera/clk-agilex.c
+++ b/drivers/clk/altera/clk-agilex.c
@@ -542,6 +542,11 @@ static ulong socfpga_clk_get_rate(struct clk *clk)
 	}
 }
 
+static int socfpga_clk_enable(struct clk *clk)
+{
+	return 0;
+}
+
 static int socfpga_clk_probe(struct udevice *dev)
 {
 	const struct cm_config *cm_default_cfg = cm_get_default_config();
@@ -565,6 +570,7 @@ static int socfpga_clk_ofdata_to_platdata(struct udevice *dev)
 }
 
 static struct clk_ops socfpga_clk_ops = {
+	.enable		= socfpga_clk_enable,
 	.get_rate	= socfpga_clk_get_rate,
 };