From: Patrice Chotard <patrice.chotard@st.com>
Date: Wed, 7 Feb 2018 09:44:49 +0000 (+0100)
Subject: ARM: dts: stm32: Add timer support for STM32F7
X-Git-Url: http://git.dujemihanovic.xyz/%22/img/sics.gif/%22/static/git-favicon.png?a=commitdiff_plain;h=cd389c03f270636e581a16ba157e37b47ae75d93;p=u-boot.git

ARM: dts: stm32: Add timer support for STM32F7

Add missing timer node to enable timer5 for STM32F7 SoCs family

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---

diff --git a/arch/arm/dts/stm32f7-u-boot.dtsi b/arch/arm/dts/stm32f7-u-boot.dtsi
index 9a9e4e5f37..4a677192a2 100644
--- a/arch/arm/dts/stm32f7-u-boot.dtsi
+++ b/arch/arm/dts/stm32f7-u-boot.dtsi
@@ -1,3 +1,11 @@
+/{
+	soc {
+		timer5: timer@40000c00 {
+			u-boot,dm-pre-reloc;
+		};
+	};
+};
+
 &pinctrl {
 	usart1_pins_a: usart1@0	{
 		u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index 46d148eab2..8c6fa133e0 100644
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -323,6 +323,13 @@
 			pinctrl-names = "default", "opendrain";
 			max-frequency = <48000000>;
 		};
+
+		timer5: timer@40000c00 {
+			compatible = "st,stm32-timer";
+			reg = <0x40000c00 0x400>;
+			interrupts = <50>;
+			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
+		};
 	};
 };