From: Marek Vasut Date: Mon, 8 Jul 2024 11:43:23 +0000 (+0200) Subject: ARM: stm32: Fix secure_waitbits() mask check X-Git-Url: http://git.dujemihanovic.xyz/%22/img/sics.gif/%22/static/git-favicon.png?a=commitdiff_plain;h=b0348a97de9e01fe2165520cfc1bc9ed5594f9ab;p=u-boot.git ARM: stm32: Fix secure_waitbits() mask check Do not apply bitwise AND to register value and expected value, only apply bitwise AND to register value and mask, and only then compare the result with expected value that the function polls for. Fixes: b49105320a5b ("stm32mp: psci: Implement PSCI system suspend and DRAM SSR") Signed-off-by: Marek Vasut --- diff --git a/arch/arm/mach-stm32mp/stm32mp1/psci.c b/arch/arm/mach-stm32mp/stm32mp1/psci.c index bfbf420fdb..a02a8988a6 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/psci.c +++ b/arch/arm/mach-stm32mp/stm32mp1/psci.c @@ -393,8 +393,7 @@ static int __secure secure_waitbits(u32 reg, u32 mask, u32 val) asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (start)); for (;;) { tmp = readl(reg); - tmp &= mask; - if ((tmp & val) == val) + if ((tmp & mask) == val) return 0; asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (end)); if ((end - start) > delay)