From: Tom Rini <trini@konsulko.com>
Date: Fri, 24 Jul 2020 12:43:08 +0000 (-0400)
Subject: Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv
X-Git-Tag: v2025.01-rc5-pxa1908~2295
X-Git-Url: http://git.dujemihanovic.xyz/%22/img/sics.gif/%22/static/git-favicon.png?a=commitdiff_plain;h=ada61f1ee2a4eaa1b29d699b5ba940483171df8a;p=u-boot.git

Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv

- Fix SiFive HiFive Unleashed board booting failure problem.
- Enable SiFive fu540 PWM driver.
- Support SiFive fu540: SPI boot.
- Update OpenSBI used for RISC-V CI testing.
- Revert "riscv: Allow use of reset drivers".
- Revert "Revert "riscv: sifive: fu540: Add gpio-restart support"".
- sysreset: syscon:
        - Don't assume default value for offset and mask property.
        - Support value property.
- qemu: Add syscon reboot and poweroff support.
- Fix SIFIVE debug serial dependency.
- Fix linking error when building u-boot-spl with no SMP support.
- AE350 use fdtdec_get_addr_size_auto_noparent to parse smc reg.
- Make memory node available to SPL in hifive-unleashed-a00-u-boot.dtsi
- SiFive fu540 avoid using hardcoded ram base and size.
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ada61f1ee2a4eaa1b29d699b5ba940483171df8a