From: Ley Foon Tan <ley.foon.tan@intel.com>
Date: Fri, 10 Jan 2020 05:48:37 +0000 (+0800)
Subject: reset: socfpga: Poll for reset status after deassert reset
X-Git-Url: http://git.dujemihanovic.xyz/%22/img/sics.gif/%22/static/git-favicon.png?a=commitdiff_plain;h=9e6082198acca5371dded5fcbede7a53ff4a7ec8;p=u-boot.git

reset: socfpga: Poll for reset status after deassert reset

In Cyclone 5 SoC platform, the first USB probing is failed but second
probing is success. DWC2 USB driver read gsnpsid register right after
de-assert reset, but controller is not ready yet and it returns gsnpsid 0.
Polling reset status after de-assert reset to solve the issue.

Retry with this fix more than 10 times without issue.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---

diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
index 93ec9cfdb6..105ce94c71 100644
--- a/drivers/reset/reset-socfpga.c
+++ b/drivers/reset/reset-socfpga.c
@@ -18,6 +18,7 @@
 #include <dm/of_access.h>
 #include <env.h>
 #include <reset-uclass.h>
+#include <wait_bit.h>
 #include <linux/bitops.h>
 #include <linux/io.h>
 #include <linux/sizes.h>
@@ -80,7 +81,10 @@ static int socfpga_reset_deassert(struct reset_ctl *reset_ctl)
 	int offset = id % (reg_width * BITS_PER_BYTE);
 
 	clrbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset));
-	return 0;
+
+	return wait_for_bit_le32(data->modrst_base + (bank * BANK_INCREMENT),
+				 BIT(offset),
+				 false, 500, false);
 }
 
 static int socfpga_reset_request(struct reset_ctl *reset_ctl)