board/t2080rdb: some update for t2080rdb

- update readme.
- add CONFIG_SYS_CORTINA_FW_IN_* for loading Cortina PHY CS4315
  ucode from NOR/NAND/SPI/SD/REMOTE.
- update cpld vbank with SW3[5:7]=000 as default vbank0 instead of
  previous SW3[5:7]=111 as default vbank.
- fix CONFIG_SYS_I2C_EEPROM_ADDR_LEN to 2.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/board/freescale/t208xrdb/README b/board/freescale/t208xrdb/README
index fe26de55c09df47d5d6cc7af3820b6fb6089ca34..24484cd0ffca70334ce50a76a0997a668f0c1e84 100644 (file)
--- a/board/freescale/t208xrdb/README
+++ b/board/freescale/t208xrdb/README
@@ -67,7 +67,7 @@ T2080PCIe-RDB board Overview
      - One PCIe x2 end-point device (C293 Crypto co-processor)
  - IFC/Local Bus
      - NOR:  128MB 16-bit NOR Flash
-     - NAND: 512MB 8-bit NAND flash
+     - NAND: 1GB 8-bit NAND flash
      - CPLD: for system controlling with programable header on-board
  - SATA
      - Two SATA 2.0 onnectors on-board
@@ -156,11 +156,11 @@ Software configurations and board settings
    Switching between default bank and alternate bank on NOR flash
    To change boot source to vbank4:
        via software:   run command 'cpld reset altbank' in u-boot.
-       via DIP-switch: set SW3[5:7] = '011'
+       via DIP-switch: set SW3[5:7] = '100'
 
    To change boot source to vbank0:
        via software:   run command 'cpld reset' in u-boot.
-       via DIP-Switch: set SW3[5:7] = '111'
+       via DIP-Switch: set SW3[5:7] = '000'
 
 2. NAND Boot:
    a. build PBL image for NAND boot

diff --git a/board/freescale/t208xrdb/cpld.h b/board/freescale/t208xrdb/cpld.h
index 4cee4e55cfcbdbce150ebda3054811ddde709a59..3f1533888ddf51acd9a0e3c9e2b40027268fa318 100644 (file)
--- a/board/freescale/t208xrdb/cpld.h
+++ b/board/freescale/t208xrdb/cpld.h
@@ -35,8 +35,8 @@ void cpld_write(unsigned int reg, u8 value);
 #define CPLD_LBMAP_MASK                0x3F
 #define CPLD_BANK_SEL_MASK     0x07
 #define CPLD_BANK_OVERRIDE     0x40
-#define CPLD_LBMAP_ALTBANK     0x43 /* BANK OR | BANK 4 */
-#define CPLD_LBMAP_DFLTBANK    0x47 /* BANK OR | BANK 0 */
+#define CPLD_LBMAP_ALTBANK     0x44 /* BANK OR | BANK 4 */
+#define CPLD_LBMAP_DFLTBANK    0x40 /* BANK OR | BANK 0 */
 #define CPLD_LBMAP_RESET       0xFF
 #define CPLD_LBMAP_SHIFT       0x03
 #define CPLD_BOOT_SEL          0x80

diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c
index f3fec2aa6ebc49c69931dbe0f6c45c9836b1791a..265c1f97ddbb6bb927bc2d24129419100647ab85 100644 (file)
--- a/board/freescale/t208xrdb/t208xrdb.c
+++ b/board/freescale/t208xrdb/t208xrdb.c
@@ -44,7 +44,7 @@ int checkboard(void)
                puts("NAND\n");
        } else {
                reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
-               printf("NOR vBank%d\n", ~reg & 0x7);
+               printf("NOR vBank%d\n", reg);
        }
 #endif
 

diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 4ef1167f9f5e63a7d38a35e32e00bbc117cd05e6..73d82edb80f39c8ace493737051e6f2cf174ed94 100644 (file)
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -208,7 +208,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_SYS_EEPROM_BUS_NUM      0
 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 
 /*
  * DDR Setup
@@ -584,7 +584,8 @@ unsigned long get_board_ddr_clk(void);
  * env, so we got 0x110000.
  */
 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
-#define CONFIG_SYS_FMAN_FW_ADDR        0x110000
+#define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR                0x110000
 #define CONFIG_CORTINA_FW_ADDR         0x120000
 
 #elif defined(CONFIG_SDCARD)
@@ -594,11 +595,13 @@ unsigned long get_board_ddr_clk(void);
  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_CORTINA_FW_IN_MMC
 #define CONFIG_SYS_FMAN_FW_ADDR                (512 * 0x820)
 #define CONFIG_CORTINA_FW_ADDR         (512 * 0x8a0)
 
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_CORTINA_FW_IN_NAND
 #define CONFIG_SYS_FMAN_FW_ADDR                (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #define CONFIG_CORTINA_FW_ADDR         (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
@@ -610,11 +613,13 @@ unsigned long get_board_ddr_clk(void);
  * master LAW->the ucode address in master's memory space.
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
-#define CONFIG_SYS_FMAN_FW_ADDR        0xFFE00000
+#define CONFIG_SYS_CORTINA_FW_IN_REMOTE
+#define CONFIG_SYS_FMAN_FW_ADDR                0xFFE00000
 #define CONFIG_CORTINA_FW_ADDR         0xFFE10000
 #else
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_FMAN_FW_ADDR        0xEFF00000
+#define CONFIG_SYS_CORTINA_FW_IN_NOR
+#define CONFIG_SYS_FMAN_FW_ADDR                0xEFF00000
 #define CONFIG_CORTINA_FW_ADDR         0xEFE00000
 #endif
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH   0x10000