riscv: dts: jh7110: Enable PLL node in SPL

Previously PLL node was missing from SPL dts. This caused BUS_ROOT
to stay on OSC clock (24Mhz). As a result, all peripherals have to
run at a much lower frequency, and loading from sdcard/emmc is slow.
Thus, enabling PLL node in dts to fix this.

Signed-off-by: Bo Gan <ganboing@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi
index 2f560e7296f60e12c9628e01e4343c2743a4e0a1..c09d5c917088c38303a670fae07fa2ce6cfc1c83 100644 (file)
--- a/arch/riscv/dts/jh7110-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-u-boot.dtsi
@@ -93,6 +93,10 @@
        bootph-pre-ram;
 };
 
+&pllclk {
+       bootph-pre-ram;
+};
+
 &S7_0 {
        status = "okay";
 };