spi: synquacer: DMSTART bit must not be set while transferring

DMSTART bit must not be set while there is active transfer.
This commit sets the DMSTART bit only when the transfer begins.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com>
Acked-by: Jassi Brar <jaswinder.singh@linaro.org>

diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c
index f1422cf893e7a6d394510175fc04ee56176da7f3..5e1b3aedc73e77d48e7a5317a245ae471771a321 100644 (file)
--- a/drivers/spi/spi-synquacer.c
+++ b/drivers/spi/spi-synquacer.c
@@ -330,9 +330,11 @@ static int synquacer_spi_xfer(struct udevice *dev, unsigned int bitlen,
        writel(~0, priv->base + RXC);
 
        /* Trigger */
-       val = readl(priv->base + DMSTART);
-       val |= BIT(TRIGGER);
-       writel(val, priv->base + DMSTART);
+       if (flags & SPI_XFER_BEGIN) {
+               val = readl(priv->base + DMSTART);
+               val |= BIT(TRIGGER);
+               writel(val, priv->base + DMSTART);
+       }
 
        while (busy & (BIT(RXBIT) | BIT(TXBIT))) {
                if (priv->rx_words)