imx: imx8m: clock: not configure reserved SRC register

i.MX8M[M,N,P] SRC not has 0x1004 offset register, so drop it.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 31c34b6031f6e37f86138999fbc4ce2026a56800..986870799d367c8eb581c16c6d207dbc0b9cc07c 100644 (file)
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -90,7 +90,6 @@ static int fracpll_configure(enum pll_clocks pll, u32 freq)
        case ANATOP_DRAM_PLL:
                setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7);
                setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5);
-               writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1004);
 
                pll_base = &ana_pll->dram_pll_gnrl_ctl;
                break;