# Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
# Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
-ifeq ($(CONFIG_SPL_BUILD),y)
+ifeq ($(CONFIG_XPL_BUILD),y)
obj-y := mux.o
endif
obj-y += ../common/common.o
/* -- defines for GPIO -- */
#define REPSWITCH (0+20) /* GPIO0_20 */
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
/* TODO: check ram-timing ! */
static const struct ddr_data ddr3_data = {
.datardsratio0 = MT41K256M16HA125E_RD_DQS,
&ddr3_cmd_ctrl_data,
&ddr3_emif_reg_data, 0);
}
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
/* Basic board specific setup. Pinmux has been handled already. */
int board_init(void)
#include <asm/arch/sys_proto.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
# include <asm/arch/mx6-ddr.h>
#endif
#include <asm/arch/clock.h>
#define MUXDESC(pad, ctrl) IOMUX_PADS(pad | MUX_PAD_CTRL(ctrl))
-#if !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_XPL_BUILD)
static iomux_v3_cfg_t const eth_pads[] = {
/*
* Gigabit Ethernet
void reset_cpu(void)
{
}
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
zip -9 -r $@ misc/* >/dev/null $<
ifeq ($(hw-platform-y),brppt2)
-ifneq ($(CONFIG_SPL_BUILD),y)
+ifneq ($(CONFIG_XPL_BUILD),y)
INPUTS-y += $(hw-platform-y)_prog.bin
INPUTS-y += $(hw-platform-y)_prod.zip
endif
# B&R Industrial Automation GmbH - http://www.br-automation.com/
#
-obj-$(CONFIG_SPL_BUILD) += mux.o
+obj-$(CONFIG_XPL_BUILD) += mux.o
obj-y += ../common/br_resetc.o
obj-y += ../common/common.o
obj-y += board.o
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
static const struct ddr_data ddr3_data = {
.datardsratio0 = MT41K256M16HA125E_RD_DQS,
.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
&ddr3_cmd_ctrl_data,
&ddr3_emif_reg_data, 0);
}
-#endif /* CONFIG_SPL_BUILD */
-#if !defined(CONFIG_SPL_BUILD)
+#endif /* CONFIG_XPL_BUILD */
+#if !defined(CONFIG_XPL_BUILD)
/* decision if backlight is switched on or not on powerup */
int board_backlightstate(void)
}
#endif /* CONFIG_BOARD_LATE_INIT */
-#endif /* !CONFIG_SPL_BUILD */
+#endif /* !CONFIG_XPL_BUILD */
# Copyright (C) 2014 Hannes Schmelzer <oe5hpm@oevsv.at> -
# Bernecker & Rainer Industrielektronik GmbH - http://www.br-automation.com/
-obj-$(CONFIG_SPL_BUILD) += mux.o
+obj-$(CONFIG_XPL_BUILD) += mux.o
obj-y += ../common/br_resetc.o
obj-y += ../common/common.o
obj-y += board.o
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
static const struct ddr_data ddr3_data = {
.datardsratio0 = MT41K256M16HA125E_RD_DQS,
.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
&ddr3_cmd_ctrl_data,
&ddr3_emif_reg_data, 0);
}
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
/*
* Basic board specific setup. Pinmux has been handled already.
*/
return 1;
}
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_AM33XX)
+#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_AM33XX)
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/clock.h>
enable_board_pin_mux();
}
-#endif /* CONFIG_SPL_BUILD && CONFIG_AM33XX */
+#endif /* CONFIG_XPL_BUILD && CONFIG_AM33XX */
# SPDX-License-Identifier: GPL-2.0+
# (C) 2022 Pali Rohár <pali@kernel.org>
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += ../../freescale/p1_p2_rdb_pc/spl.o
endif
0, 9, BOOKE_PAGESZ_256K, 1),
#endif
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD)
/* **M** - SDRAM 2G */
SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE,
CFG_SYS_DDR_SDRAM_BASE,
obj-y := turris_omnia.o ../turris_atsha_otp.o ../turris_common.o
obj-$(CONFIG_CMD_EEPROM_LAYOUT) += eeprom.o
-obj-$(CONFIG_SPL_BUILD) += old_ddr3_training.o
+obj-$(CONFIG_XPL_BUILD) += old_ddr3_training.o
if (!eeprom)
return false;
- if (IS_ENABLED(CONFIG_SPL_BUILD))
+ if (IS_ENABLED(CONFIG_XPL_BUILD))
ret = dm_i2c_read(eeprom, 0, (void *)oep, sizeof(*oep));
else
ret = i2c_eeprom_read(eeprom, 0, (void *)oep, sizeof(*oep));
# Copyright (C) 2015 Phil Sutter <phil@nwl.cc>
obj-y += ds414.o
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-y += cmd_syno.o
endif
ifdef CONFIG_TARGET_IMX8MP_RSB3720A1_6G
obj-y += imx8mp_rsb3720a1.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_rsb3720a1_6G.o
endif
ifdef CONFIG_TARGET_IMX8MP_RSB3720A1_4G
obj-y += imx8mp_rsb3720a1.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_rsb3720a1_4G.o
endif
#
obj-y += imx8qm_dmsse20_a1.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_XPL_BUILD) += spl.o
obj-y += imx8qm_rom7720_a1.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
endif
#
obj-y := $(BOARD).o
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-y += ../common/gpio_hog.o
endif
# (C) Copyright 2021
# Svyatoslav Ryhel <clamor95@gmail.com>
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_DM_PMIC_MAX77663) += grouper-spl-max.o
obj-$(CONFIG_DM_PMIC_TPS65910) += grouper-spl-ti.o
endif
# (C) Copyright 2021
# Svyatoslav Ryhel <clamor95@gmail.com>
-obj-$(CONFIG_SPL_BUILD) += transformer-t30-spl.o
+obj-$(CONFIG_XPL_BUILD) += transformer-t30-spl.o
obj-y += transformer-t30.o
}
#endif
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
#include <spl.h>
#include <nand.h>
return 0;
}
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
#include <spl.h>
#include <nand.h>
return 0;
}
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
#include <spl.h>
#include <nand.h>
#endif
/* SPL */
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void spl_board_init(void)
{
}
}
/* SPL */
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
static void board_leds_init(void)
{
}
/* SPL */
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
/* must set PB25 low to enable the CAN transceivers */
static void board_can_stdby_dis(void)
#endif
/* SPL */
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void spl_board_init(void)
{
}
}
/* SPL */
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void spl_board_init(void)
{
#ifdef CONFIG_SD_BOOT
#endif
/* SPL */
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void spl_board_init(void)
{
#if CONFIG_NAND_BOOT
}
/* SPL */
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void spl_board_init(void)
{
#if CONFIG_NAND_BOOT
}
/* SPL */
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void spl_board_init(void)
{
#if CONFIG_NAND_BOOT
# (C) Copyright 2013
# Avionic Design GmbH <www.avionic-design.de>
-obj-$(CONFIG_SPL_BUILD) += tec-ng-spl.o
+obj-$(CONFIG_XPL_BUILD) += tec-ng-spl.o
obj-y += ../common/tamonten-ng.o
obj-y += imx8mm_beacon.o
obj-y += ../../freescale/common/
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
obj-y += lpddr4_timing.o
endif
obj-y += imx8mn_beacon.o
obj-y += ../../freescale/common/
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
ifdef CONFIG_IMX8MN_BEACON_2GB_LPDDR
obj-y += lpddr4_2g_timing.o
obj-y += imx8mp_beacon.o
obj-y += ../../freescale/common/
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
endif
# Remove quotes
hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))
-obj-$(CONFIG_SPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o
+obj-$(CONFIG_XPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o
return 0;
}
-#if IS_ENABLED(CONFIG_SPL_BUILD)
+#if IS_ENABLED(CONFIG_XPL_BUILD)
#include <asm/arch/crm_regs.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
}
}
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
#endif
#if defined(CONFIG_USB_ETHER) && \
- (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER))
+ (!defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_USB_ETHER))
int board_eth_init(struct bd_info *bis)
{
return usb_eth_initialize(bis);
# (C) Copyright 2021 Amarula Solutions B.V.
obj-y := imx6ulz_smm_m2.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_XPL_BUILD) += spl.o
obj-y += imx8mn_smm_s2.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
obj-$(CONFIG_BSH_SMM_S2_DDR3L_256) += ddr3l_timing_256m.o
obj-$(CONFIG_BSH_SMM_S2_DDR3L_512) += ddr3l_timing_512m.o
#
obj-y := mamoj.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_XPL_BUILD) += spl.o
obj-y += imx8mm_phg.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
endif
obj-y := mux.o common.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
else
obj-y += cl-som-imx7.o
PADS_SET_PROT(espi1_pads);
#endif /* CONFIG_SPI */
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
#ifdef CONFIG_FSL_ESDHC_IMX
PADS_SET_PROT(usdhc3_emmc_pads);
#endif /* CONFIG_FSL_ESDHC_IMX */
#endif /* CONFIG_FEC_MXC */
PADS_SET_PROT(usb_otg1_pads);
PADS_SET_PROT(wdog_pads);
-#endif /* !CONFIG_SPL_BUILD */
+#endif /* !CONFIG_XPL_BUILD */
#endif /* CONFIG_SPI */
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
#ifdef CONFIG_FSL_ESDHC_IMX
PADS_SET(wdog_pads)
-#endif /* !CONFIG_SPL_BUILD */
+#endif /* !CONFIG_XPL_BUILD */
# (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
#
# Authors: Nikita Kiryanov <nikita@compulab.co.il>
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y = common.o spl.o
else
obj-y = common.o cm_fx6.o
#
# Copyright (C) 2015 Compulab, Ltd.
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o mux.o
else
obj-y += cm_t43.o mux.o
obj-y += imx8mm-cl-iot-gate.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o eeprom_spl.o
obj-y += ddr/
endif
#include <asm/setup.h>
#include <linux/delay.h>
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#define CFG_SYS_I2C_EEPROM_ADDR_P1 0x51
return 0;
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#include <spl.h>
#define MX6_PHYFLEX_ERR006282 IMX_GPIO_NR(2, 11)
}
/* SPL */
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void spl_board_init(void)
{
}
obj-y += cgtqmx8.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
endif
MINIMAL=
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
ifndef CONFIG_TPL_BUILD
ifdef CONFIG_SPL_INIT_MINIMAL
MINIMAL=y
return 0;
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
static void data_modul_imx_edm_sbc_early_init_f(const iomux_v3_cfg_t wdog_pad)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
# SPDX-License-Identifier: GPL-2.0+
#
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o lpddr4_timing_2G_32.o lpddr4_timing_4G_32.o
else
obj-y += imx8mm_data_modul_edm_sbc.o
# SPDX-License-Identifier: GPL-2.0+
#
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o lpddr4_timing_4G_32.o
else
obj-y += imx8mp_data_modul_edm_sbc.o
#endif
#endif
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
static const struct ns16550_plat serial_pdata = {
.base = DAVINCI_UART2_BASE,
.reg_shift = 2,
#
# Copyright (C) 2017 Marek Vasut <marex@denx.de>
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y := dh_imx6_spl.o
else
obj-y := dh_imx6.o
# SPDX-License-Identifier: GPL-2.0+
#
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o lpddr4_timing_2G_32.o lpddr4_timing_4G_32.o
else
obj-y += imx8mp_dhcom_pdk2.o
void board_vddcore_init(u32 voltage_mv)
{
- if (IS_ENABLED(CONFIG_SPL_BUILD))
+ if (IS_ENABLED(CONFIG_XPL_BUILD))
opp_voltage_mv = voltage_mv;
}
int board_early_init_f(void)
{
- if (IS_ENABLED(CONFIG_SPL_BUILD))
+ if (IS_ENABLED(CONFIG_XPL_BUILD))
stpmic1_init(opp_voltage_mv);
board_get_coding_straps();
}
#endif
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
void spl_perform_fixups(struct spl_image_info *spl_image)
{
dh_stm32_ks8851_fixup(spl_image_fdt_addr(spl_image));
return 0;
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#include <spl.h>
#ifdef CONFIG_SPL_LOAD_FIT
#define CFG_SYS_RTC_SCRATCH0 0x60
#define BOOT_DEVICE_SAVE_REGISTER (RTC_BASE + CFG_SYS_RTC_SCRATCH0)
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
static void save_boot_device(void)
{
*((u32 *)(BOOT_DEVICE_SAVE_REGISTER)) = spl_boot_device();
return 0;
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#include <spl.h>
void board_init_f(ulong dummy)
# SPDX-License-Identifier: GPL-2.0+
# Copyright (C) 2016 Amarula Solutions B.V.
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_IMX6_ENGICAM_COMMON) += spl.o
else
obj-$(CONFIG_IMX6_ENGICAM_COMMON) += board.o
obj-y += icore_mx8mm.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
obj-y += lpddr4_timing.o
endif
obj-y += icore_mx8mp.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
endif
# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
#
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
else
obj-y += stm32mp1.o
#include <asm/global_data.h>
#include <dm/ofnode.h>
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
static int setup_led(void)
{
#ifdef CONFIG_SPL_LED
#include <asm/arch-rockchip/gpio.h>
#include <asm/arch-rockchip/grf_rk3399.h>
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#define PMUGRF_BASE 0xff320000
#define GPIO0_BASE 0xff720000
MINIMAL=
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
ifndef CONFIG_TPL_BUILD
ifdef CONFIG_SPL_INIT_MINIMAL
MINIMAL=y
obj-$(CONFIG_FSL_CADMUS) += cadmus.o
obj-$(CONFIG_FSL_VIA) += cds_via.o
obj-$(CONFIG_FMAN_ENET) += fman.o
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_FSL_NGPIXIS) += ngpixis.o
endif
obj-$(I2C_COMMON) += i2c_common.o
obj-$(CONFIG_FSL_USE_PCA9547_MUX) += i2c_mux.o
obj-$(CONFIG_$(SPL_)VID) += vid.o
obj-$(CONFIG_FSL_QIXIS) += qixis.o
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_ID_EEPROM) += sys_eeprom.o
endif
ifndef CONFIG_RAMBOOT_PBL
return 0;
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static int do_esbc_validate(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
#include <dm/root.h>
#include <asm/fsl_secure_boot.h>
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_FRAMEWORK)
+#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_FRAMEWORK)
#include <spl.h>
#endif
return 0;
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
int fsl_setenv_chain_of_trust(void)
{
/* Check Boot Mode
}
#endif
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr)
{
int res;
image_entry();
}
#endif /* ifdef CONFIG_SPL_FRAMEWORK */
-#endif /* ifdef CONFIG_SPL_BUILD */
+#endif /* ifdef CONFIG_XPL_BUILD */
*/
void fsl_secboot_handle_error(int error)
{
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
const struct fsl_secboot_errcode *e;
for (e = fsl_secboot_errcodes; e->errcode != ERROR_ESBC_CLIENT_MAX;
prop.num_bits = key_len * 8;
prop.exp_len = key_len;
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
ret = device_bind_driver(NULL, "fsl_rsa_mod_exp", "fsl_rsa_mod_exp", NULL);
if (ret) {
printf("Couldn't bind fsl_rsa_mod_exp driver (%d)\n", ret);
}
#endif
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static void qixis_reset(void)
{
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET);
obj-y += imx8mm_evk.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
endif
obj-y += imx8mn_evk.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_ld.o
obj-y += imx8mp_evk.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
endif
obj-y += imx8mq_evk.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o lpddr4_timing_b0.o
endif
#
obj-y += imx8qm_mek.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_XPL_BUILD) += spl.o
#
obj-y += imx8qxp_mek.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_XPL_BUILD) += spl.o
obj-y += imx8ulp_evk.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
ifdef CONFIG_IMX8ULP_ND_MODE
obj-y += lpddr4_timing_264.o
obj-y += imx93_evk.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX93_EVK_LPDDR4X) += lpddr4x_timing.o lpddr4x_timing_1866mts.o
endif
return fdtdec_setup_memory_banksize();
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
return fdtdec_setup_memory_banksize();
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
return fdtdec_setup_memory_banksize();
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
#endif
mmdc_init(&mparam);
-#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
#endif
mmdc_init(&mparam);
gd->ram_size = CFG_SYS_SDRAM_SIZE;
-#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
#endif
#endif
gd->ram_size = CFG_SYS_SDRAM_SIZE;
-#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
#endif
int dram_init(void)
{
-#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
+#if (!defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD))
ddrmc_init();
#endif
return 0;
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void board_init_f(ulong dummy)
{
/* Clear the BSS */
{
phys_size_t dram_size;
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
+#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_SPL)
puts("Initializing DDR....using SPD\n");
dram_size = fsl_ddr_sdram();
#else
dram_size = fsl_ddr_sdram_size();
#endif
-#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_XPL_BUILD)
fsl_dp_resume();
#endif
return 0;
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void board_init_f(ulong dummy)
{
#ifdef CONFIG_NAND_BOOT
static void ddrmc_init(void)
{
-#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
+#if (!defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD))
struct ccsr_ddr *ddr = (struct ccsr_ddr *)CFG_SYS_FSL_DDR_ADDR;
u32 temp_sdram_cfg, tmp;
out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
}
#endif
-#endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
+#endif /* !defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD) */
}
int dram_init(void)
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
-#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_XPL_BUILD)
fsl_dp_resume();
#endif
return 0;
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void board_init_f(ulong dummy)
{
void (*second_uboot)(void);
return 0;
}
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
void spl_board_init(void)
{
ls102xa_smmu_stream_id_init();
int dram_init(void)
{
-#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
+#if (!defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD))
ddrmc_init();
#endif
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
-#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_XPL_BUILD)
fsl_dp_resume();
#endif
return 0;
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void board_init_f(ulong dummy)
{
void (*second_uboot)(void);
return 0;
}
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
void spl_board_init(void)
{
if (IS_ENABLED(CONFIG_FSL_CAAM)) {
}
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) \
- && !defined(CONFIG_SPL_BUILD)
+ && !defined(CONFIG_XPL_BUILD)
static void convert_flash_bank(char bank)
{
struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE);
u8 uart;
#endif
-#if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_XPL_BUILD)
i2c_early_init_f();
#endif
#
obj-y += ddr.o
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-y += eth.o
endif
obj-y += ls1043aqds.o
{
phys_size_t dram_size;
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD)
gd->ram_size = fsl_ddr_sdram_size();
return 0;
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
fsl_initdram();
#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
- defined(CONFIG_SPL_BUILD)
+ defined(CONFIG_XPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
#endif
obj-y += ddr.o
obj-y += ls1043ardb.o
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_NET) += eth.o
obj-y += cpld.o
endif
phys_size_t dram_size;
#ifdef CONFIG_SYS_DDR_RAW_TIMING
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
+#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_SPL)
puts("Initializing DDR....\n");
dram_size = fsl_ddr_sdram();
#else
dram_size = fsl_ddr_sdram_size();
#endif
#else
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
+#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_SPL)
puts("Initialzing DDR using fixed setting\n");
dram_size = fixed_sdram();
#else
return 0;
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
int checkboard(void)
{
#
obj-y += ddr.o
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-y += eth.o
endif
obj-y += ls1046aqds.o
{
phys_size_t dram_size;
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD)
gd->ram_size = fsl_ddr_sdram_size();
return 0;
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
fsl_initdram();
#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
- defined(CONFIG_SPL_BUILD)
+ defined(CONFIG_XPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
#endif
obj-y += ddr.o
obj-y += ls1046ardb.o
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_NET) += eth.o
obj-y += cpld.o
endif
{
phys_size_t dram_size;
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD)
gd->ram_size = fsl_ddr_sdram_size();
return 0;
return 0;
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
int checkboard(void)
{
static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
obj-y += ls1088a.o
obj-y += ddr.o
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_TARGET_LS1088ARDB) += eth_ls1088ardb.o
obj-$(CONFIG_TARGET_LS1088AQDS) += eth_ls1088aqds.o
endif
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
+#if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD))
static void fsl_ddr_setup_0v9_volt(memctl_options_t *popts)
{
int vdd;
popts->addr_hash = 1;
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
-#if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
+#if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD))
fsl_ddr_setup_0v9_volt(popts);
#endif
{
puts("Initializing DDR....using SPD\n");
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD)
gd->ram_size = fsl_ddr_sdram_size();
#else
gd->ram_size = fsl_ddr_sdram();
return 0;
}
-#if !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_XPL_BUILD)
int checkboard(void)
{
#ifdef CONFIG_TFABOOT
}
#endif
-#if !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_XPL_BUILD)
void board_retimer_init(void)
{
u8 reg;
return ret;
}
-#if !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_XPL_BUILD)
int board_init(void)
{
init_final_memctl_regs();
return 0;
}
#endif
-#endif /* defined(CONFIG_SPL_BUILD) */
+#endif /* defined(CONFIG_XPL_BUILD) */
#ifdef CONFIG_TFABOOT
#ifdef CONFIG_MTD_NOR_FLASH
#else
int fsl_initdram(void)
{
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD)
gd->ram_size = fsl_ddr_sdram_size();
#else
puts("Initializing DDR....using SPD\n");
#endif
}
-#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_XPL_BUILD)
void fdt_fixup_board_enet(void *fdt)
{
int offset;
fsl_fdt_fixup_dr_usb(blob, bd);
-#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_XPL_BUILD)
fdt_fixup_board_enet(blob);
fdt_reserve_mc_mem(blob, 0x300);
#endif
#else
int fsl_initdram(void)
{
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD)
gd->ram_size = fsl_ddr_sdram_size();
#else
puts("Initializing DDR....using SPD\n");
int board_eth_init(struct bd_info *bis)
{
-#if defined(CONFIG_PHY_AQUANTIA) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_PHY_AQUANTIA) && !defined(CONFIG_XPL_BUILD)
/*
* Export functions to be used by AQ firmware
* upload application
int board_early_init_f(void)
{
-#if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_XPL_BUILD)
i2c_early_init_f();
#endif
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-y := mx23evk.o
else
obj-y := spl_boot.o
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-y := mx28evk.o
else
obj-y := iomux.o
#
# (C) Copyright 2011 Freescale Semiconductor, Inc.
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y := spl.o
else
obj-y := mx6memcal.o
}
#endif
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#include <asm/arch/mx6-ddr.h>
#include <spl.h>
#include <linux/libfdt.h>
return 0;
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#include <asm/arch/mx6-ddr.h>
#include <spl.h>
#include <linux/libfdt.h>
MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
};
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
static iomux_v3_cfg_t const usdhc1_pads[] = {
/* 8 bit SD */
MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
return 0;
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#include <spl.h>
#include <linux/libfdt.h>
}
#endif
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
gpio_set_value(IMX_GPIO_NR(5, 9), 0);
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#include <linux/libfdt.h>
#include <spl.h>
#include <asm/arch/mx6-ddr.h>
MINIMAL=
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
ifndef CONFIG_TPL_BUILD
ifdef CONFIG_SPL_INIT_MINIMAL
MINIMAL=y
ifdef MINIMAL
obj-y += spl_minimal.o
else
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
endif
obj-y += p1010rdb.o
return 0;
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static int pin_mux_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1M, 1),
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_16M, 1),
MINIMAL=
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
ifndef CONFIG_TPL_BUILD
ifdef CONFIG_SPL_INIT_MINIMAL
MINIMAL=y
ifdef MINIMAL
obj-y += spl_minimal.o
else
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
endif
obj-y += p1_p2_rdb_pc.o
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1M, 1),
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
/* W**G* - Flash/promjet, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
# SPDX-License-Identifier: GPL-2.0+
#
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
else
obj-y += t102xrdb.o
{
phys_size_t dram_size;
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
+#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
#ifndef CONFIG_SYS_DDR_RAW_TIMING
puts("Initializing....using SPD\n");
#endif
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
-#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_XPL_BUILD)
fsl_dp_resume();
#endif
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 11, BOOKE_PAGESZ_256K, 1),
#endif
-#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_XPL_BUILD)
SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 12, BOOKE_PAGESZ_1G, 1),
#
# Copyright 2013 Freescale Semiconductor, Inc.
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
else
obj-y += t104xrdb.o
{
phys_size_t dram_size;
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
+#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
puts("Initializing....using SPD\n");
dram_size = fsl_ddr_sdram();
#else
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
-#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_XPL_BUILD)
fsl_dp_resume();
#endif
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_256K, 1),
-#elif defined(CONFIG_NXP_ESBC) && defined(CONFIG_SPL_BUILD)
+#elif defined(CONFIG_NXP_ESBC) && defined(CONFIG_XPL_BUILD)
/*
* *I*G - L3SRAM. When L3 is used as 256K SRAM, in case of Secure Boot
* the physical address of the SRAM is at 0xbffc0000,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 11, BOOKE_PAGESZ_256K, 1),
#endif
-#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_XPL_BUILD)
SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 12, BOOKE_PAGESZ_1G, 1),
# SPDX-License-Identifier: GPL-2.0+
#
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
else
obj-$(CONFIG_TARGET_T2080QDS) += t208xqds.o eth_t208xqds.o
{
phys_size_t dram_size;
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
+#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
puts("Initializing....using SPD\n");
dram_size = fsl_ddr_sdram();
#else
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
/* *I*G* - PCIe 1, 0x80000000 */
SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 18, BOOKE_PAGESZ_1M, 1),
#endif
-#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_XPL_BUILD)
SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 19, BOOKE_PAGESZ_2G, 1)
# SPDX-License-Identifier: GPL-2.0+
#
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
else
obj-$(CONFIG_TARGET_T2080RDB) += t208xrdb.o eth_t208xrdb.o cpld.o
{
phys_size_t dram_size;
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
+#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
puts("Initializing....using SPD\n");
dram_size = fsl_ddr_sdram();
#else
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
/* *I*G* - PCIe 1, 0x80000000 */
SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
0, 18, BOOKE_PAGESZ_1M, 1),
#endif
-#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_XPL_BUILD)
SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 19, BOOKE_PAGESZ_2G, 1)
# SPDX-License-Identifier: GPL-2.0+
#
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
else
obj-$(CONFIG_TARGET_T4240RDB) += t4240rdb.o
}
#endif
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
int rc = 0;
puts("Initializing....using SPD\n");
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
+#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
dram_size = fsl_ddr_sdram();
#else
/* DDR has been initialised by first stage boot loader */
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
MAS3_SW|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 17, BOOKE_PAGESZ_4K, 1),
#endif
-#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_XPL_BUILD)
SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 18, BOOKE_PAGESZ_2G, 1)
obj-y += board.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
endif
return ret;
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
U_BOOT_CMD(
fd_write, 1, 0, do_fd_write,
"Write test factory-data values to SPI NOR",
#
obj-y := gw_ventana.o eeprom.o common.o
-obj-$(CONFIG_SPL_BUILD) += gw_ventana_spl.o
+obj-$(CONFIG_XPL_BUILD) += gw_ventana_spl.o
{ /* Sentinel */ }
};
-#if defined(CONFIG_CMD_EECONFIG) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_CMD_EECONFIG) && !defined(CONFIG_XPL_BUILD)
static struct ventana_eeprom_config *get_config(const char *name)
{
struct ventana_eeprom_config *cfg = econfig;
obj-y += venice.o eeprom.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
ifdef CONFIG_IMX8MM
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_imx8mm.o
obj-$(CONFIG_TARGET_CONTROLCENTERDC) += controlcenterdc.o hre.o keyprogram.o dt_helpers.o
-ifeq ($(CONFIG_SPL_BUILD),)
+ifeq ($(CONFIG_XPL_BUILD),)
obj-$(CONFIG_TARGET_CONTROLCENTERDC) += hydra.o ihs_phys.o
endif
void spl_board_init(void)
{
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
uint k;
struct gpio_desc gpio = {};
int board_early_init_f(void)
{
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
/* Configure MPP */
writel(0x00111111, MVEBU_MPP_BASE + 0x00);
writel(0x40040000, MVEBU_MPP_BASE + 0x04);
return 0;
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
void init_host_phys(struct mii_dev *bus)
{
uint k;
int board_late_init(void)
{
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
hydra_initialize();
#endif
return 0;
return 0;
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static int last_stage_init(void)
{
struct udevice *tpm;
int ret;
- if (IS_ENABLED(CONFIG_SPL_BUILD))
+ if (IS_ENABLED(CONFIG_XPL_BUILD))
return 0;
ccdc_eth_init();
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
#define B1X5V2_GE_VPD_OFFSET 0x0100000
#define B1X5V2_GE_VPD_SIZE 1022
""
);
-#endif // CONFIG_SPL_BUILD
+#endif // CONFIG_XPL_BUILD
#include <spi_flash.h>
#include <spl.h>
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
#include <asm/arch/mx6-ddr.h>
{
int ret;
- if (IS_ENABLED(CONFIG_SPL_BUILD))
+ if (IS_ENABLED(CONFIG_XPL_BUILD))
return -ENOSYS;
switch (id) {
#include <init.h>
#include <asm/arch-rockchip/clock.h>
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
/* provided to defeat compiler optimisation in board_init_f() */
void gru_dummy_function(int i)
{
}
#endif
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
int board_early_init_r(void)
{
struct udevice *clk;
obj-y += imx8mq_phanbell.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_1g.o
endif
* There is a U-Boot driver for this but it may need to add support for the
* 'voltage-table' property.
*/
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
static int veyron_init(void)
{
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
-#if !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_XPL_BUILD)
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;
return 0;
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void board_boot_order(u32 *spl_boot_list)
{
struct src *psrc = (struct src *)SRC_BASE_ADDR;
# (C) Copyright 2021
# Svyatoslav Ryhel <clamor95@gmail.com>
-obj-$(CONFIG_SPL_BUILD) += endeavoru-spl.o
+obj-$(CONFIG_XPL_BUILD) += endeavoru-spl.o
obj-y += endeavoru.o
jz4780_clk_ungate_mmc();
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static void ci20_mux_eth(void)
{
return 0;
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#if defined(CONFIG_SPL_MMC)
int board_mmc_init(struct bd_info *bd)
#
# Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += mux.o
endif
return revision;
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
/* PN H5TQ4G63AFR is equivalent to MT41K256M16HA125*/
static const struct ddr_data ddr3_igep0034_data = {
.datardsratio0 = MT41K256M16HA125E_RD_DQS,
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y := spl.o common.o
else
obj-y := igep00x0.o common.o
#
# Copyright (C) 2018 Lukasz Majewski <lukma@denx.de>
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y := kp_imx6q_tpc_spl.o
else
obj-y := kp_imx6q_tpc.o
obj-y += pitx_imx8m.o pitx_misc.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o pitx_misc.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_2gb.o lpddr4_timing_4gb.o
endif
# SPDX-License-Identifier: GPL-2.0+
# (C) Copyright 2018 Kontron Electronics GmbH
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y := spl.o
else
obj-y := sl-mx6ul.o
obj-y := sl-mx8mm.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
endif
# SPDX-License-Identifier: GPL-2.0+
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-y += sl28.o cmds.o
endif
obj-$(CONFIG_ARMV8_PSCI) += psci.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
obj-$(CONFIG_SPL_ATF) += spl_atf.o
endif
break;
}
- if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_SPL_BUILD))
+ if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_XPL_BUILD))
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
gd->ram_size = dram_size;
#
# Copyright (C) 2014 Marek Vasut <marex@denx.de>
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y := novena_spl.o
else
obj-y := novena.o
# (C) Copyright 2022
# Open Surface RT
-obj-$(CONFIG_SPL_BUILD) += ideapad-yoga-11-spl.o
+obj-$(CONFIG_XPL_BUILD) += ideapad-yoga-11-spl.o
MUX_SNIPER();
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void get_board_mem_timings(struct board_sdrc_timings *timings)
{
timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
# (C) Copyright 2021
# Svyatoslav Ryhel <clamor95@gmail.com>
-obj-$(CONFIG_SPL_BUILD) += x3-t30-spl.o
+obj-$(CONFIG_XPL_BUILD) += x3-t30-spl.o
obj-y += x3-t30.o
#
# SPDX-License-Identifier: GPL-2.0+
#
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y = spl.o
else
obj-y := display5.o
#
# (C) Copyright 2016-2017
# Lukasz Majewski, DENX Software Engineering, lukma@denx.de
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y := spl.o
else
obj-y := mccmon6.o
obj-y := xea.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl_xea.o
endif
#include <spi.h>
#include <spi_flash.h>
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#include <spl.h>
#endif
mxs_set_sspclk(MXC_SSPCLK3, 96000, 0);
}
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_FRAMEWORK)
+#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_FRAMEWORK)
void board_init_f(ulong arg)
{
init_clocks();
.id = UCLASS_CLK,
.of_match = imx28_clk_ids,
};
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
#define CPGMACSS_SW_RST (1 << 1)
#define PHY_GPIO 30
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
#if defined(CONFIG_SPL_OS_BOOT)
int spl_start_uboot(void)
{
return 0;
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6q-ddr.h>
#include <spl.h>
}
#endif
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
/*
* Routine: get_board_mem_timings
* Description: If we use SPL then there is no x-loader nor config header
/*
* NAND SPL
*/
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void spl_board_init(void)
{
setup_iomux_nand();
obj-y += ../../toradex/verdin-imx8mm/verdin-imx8mm.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += ../../toradex/verdin-imx8mm/spl.o
obj-$(CONFIG_IMX8M_LPDDR4) += ../../toradex/verdin-imx8mm/lpddr4_timing.o
endif
# Common for all Toradex modules
-ifeq ($(CONFIG_SPL_BUILD),y)
+ifeq ($(CONFIG_XPL_BUILD),y)
# Necessary to create built-in.o
obj- := __dummy__.o
else
# (C) Copyright 2021
# Open Surface RT
-obj-$(CONFIG_SPL_BUILD) += surface-rt-spl.o
+obj-$(CONFIG_XPL_BUILD) += surface-rt-spl.o
obj-y += imx8mq_reform2.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
endif
# SPDX-License-Identifier: GPL-2.0
#
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o lpddr4_timing.o
else
obj-y += sm2s_imx8mp.o
# SPDX-License-Identifier: GPL-2.0+
obj-y := mys_6ulx.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_XPL_BUILD) += spl.o
#
# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
-obj-$(CONFIG_SPL_BUILD) += beaver-spl.o
+obj-$(CONFIG_XPL_BUILD) += beaver-spl.o
obj-y = ../cardhu/cardhu.o
# (C) Copyright 2010-2012
# NVIDIA Corporation <www.nvidia.com>
-obj-$(CONFIG_SPL_BUILD) += cardhu-spl.o
+obj-$(CONFIG_XPL_BUILD) += cardhu-spl.o
obj-y += cardhu.o
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-y := mx23_olinuxino.o
else
obj-y := spl_boot.o
hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))
-obj-$(CONFIG_SPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o
+obj-$(CONFIG_XPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o
# Copyright (C) 2023 PHYTEC Messtechnik GmbH
# Author: Teresa Remmet <t.remmet@phytec.de>
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
# necessary to create built-in.o
obj- := __dummy__.o
endif
#
obj-y := pcl063.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_XPL_BUILD) += spl.o
return 0;
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#include <spl.h>
#include <linux/libfdt.h>
#
# Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += mux.o
endif
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
}
#endif
-#if IS_ENABLED(CONFIG_SPL_BUILD)
+#if IS_ENABLED(CONFIG_XPL_BUILD)
void spl_perform_fixups(struct spl_image_info *spl_image)
{
u64 start[CONFIG_NR_DRAM_BANKS];
obj-y += phycore-imx8mm.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
endif
obj-y += phycore-imx8mp.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
endif
obj-y += phycore-imx93.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o lpddr4_timing.o
endif
obj-y += imx8mp_debix_model_a.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
endif
obj-y += librem5.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o lpddr4_timing_b0.o
endif
/* Could be ASPEN, BIRCH or CHESTNUT. assume CHESTNUT */
#define BOARD_REV_UNKNOWN BOARD_REV_CHESTNUT
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
static const iomux_v3_cfg_t configure_pads[] = {
IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(PAD_CTL_DSE6),
IMX8MQ_PAD_GPIO1_IO03__GPIO1_IO3 | MUX_PAD_CTRL(PAD_CTL_DSE6) | MUX_MODE_SION,
gpio_direction_output(AUDIO_EN, 1);
gpio_direction_output(DSI_EN, 1);
}
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
#define USB1_BASE_ADDR 0x38100000
#define USB2_BASE_ADDR 0x38200000
#endif
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && IS_ENABLED(CONFIG_EFI_PARTITION)
static bool board_is_rockpi_4b(void)
{
}
}
#endif /* CONFIG_EFI_HAVE_CAPSULE_SUPPORT && CONFIG_EFI_PARTITION */
-#endif /* !CONFIG_SPL_BUILD */
+#endif /* !CONFIG_XPL_BUILD */
# SPDX-License-Identifier: GPL-2.0
#
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y := alt_spl.o
else
obj-y := alt.o qos.o
# SPDX-License-Identifier: GPL-2.0+
#
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y := ../rcar-common/gen3-spl.o
else
obj-y := ../rcar-common/common.o
# SPDX-License-Identifier: GPL-2.0+
#
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y := ../rcar-common/gen3-spl.o
else
obj-y := draak.o ../rcar-common/common.o
# SPDX-License-Identifier: GPL-2.0+
#
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y := ../rcar-common/gen3-spl.o
else
obj-y := ../rcar-common/v3-common.o ../rcar-common/common.o
# SPDX-License-Identifier: GPL-2.0+
#
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y := ../rcar-common/gen3-spl.o
else
obj-y := ../rcar-common/common.o
# SPDX-License-Identifier: GPL-2.0+
#
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y := ../rcar-common/gen3-spl.o
else
obj-y := falcon.o ../rcar-common/common.o
# SPDX-License-Identifier: GPL-2.0
#
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y := gose_spl.o
else
obj-y := gose.o qos.o
# SPDX-License-Identifier: GPL-2.0
#
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y := koelsch_spl.o
else
obj-y := koelsch.o qos.o
# SPDX-License-Identifier: GPL-2.0
#
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y := lager_spl.o
else
obj-y := lager.o qos.o
# SPDX-License-Identifier: GPL-2.0
#
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y := porter_spl.o
else
obj-y := porter.o qos.o
# SPDX-License-Identifier: GPL-2.0+
#
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y := ../rcar-common/gen3-spl.o
else
obj-y := salvator-x.o ../rcar-common/common.o
# SPDX-License-Identifier: GPL-2.0
#
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y := silk_spl.o
else
obj-y := silk.o qos.o
# SPDX-License-Identifier: GPL-2.0
#
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y := stout_spl.o
else
obj-y := stout.o cpld.o qos.o
# SPDX-License-Identifier: GPL-2.0+
#
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y := ../rcar-common/gen3-spl.o
else
obj-y := ulcb.o cpld.o ../rcar-common/common.o
# SPDX-License-Identifier: GPL-2.0+
#
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y := ../rcar-common/gen3-spl.o
else
obj-y := ../rcar-common/v3-common.o ../rcar-common/common.o
# SPDX-License-Identifier: GPL-2.0+
#
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y := ../rcar-common/gen3-spl.o
else
obj-y := ../rcar-common/v3-common.o ../rcar-common/common.o
# SPDX-License-Identifier: GPL-2.0+
# (C) Copyright 2017 NXP Semiconductors
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
else
obj-y += imx7-cm.o
obj-y += imx8mq_cm.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
endif
obj-$(CONFIG_USB_GADGET_DOWNLOAD) += gadget.o
obj-$(CONFIG_MISC_COMMON) += misc.o
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_BOARD_COMMON) += board.o sromc.o
ifdef CONFIG_EXYNOS5_DT
obj-y += exynos5-dt.o
#
# Copyright (C) 2011 Samsung Electronics
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
# necessary to create built-in.o
obj- := __dummy__.o
#
# Copyright (C) 2011 Samsung Electronics
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
# necessary to create built-in.o
obj- := __dummy__.o
# SPDX-License-Identifier: GPL-2.0+
obj-y := npi_imx6ull.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_XPL_BUILD) += spl.o
# SPDX-License-Identifier: GPL-2.0+
# (C) Copyright 2022 Kontron Electronics GmbH
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y := spl.o
else
obj-y := imx6dl-sielaff.o
obj-y += board.o
obj-y += ../common/eeprom.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
else
obj-y += ../common/factoryset.o
{
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
/* LED's */
static int board_led_init(void)
{
mdelay(1);
return ret;
}
-#endif /* !CONFIG_SPL_BUILD */
+#endif /* !CONFIG_XPL_BUILD */
int checkboard(void)
{
run_command(cmd, 0);
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static int load_parameters_from_factoryset(void)
{
int ret;
"Reset eth phy",
"[print]"
);
-#endif /* ! CONFIG_SPL_BUILD */
+#endif /* ! CONFIG_XPL_BUILD */
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void set_uart_mux_conf(void)
{
enable_uart0_pin_mux();
return;
}
-#endif /* #ifdef CONFIG_SPL_BUILD */
+#endif /* #ifdef CONFIG_XPL_BUILD */
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
/*
* Basic board specific setup. Pinmux has been handled already.
*/
return 0;
}
-#endif /* #ifndef CONFIG_SPL_BUILD */
+#endif /* #ifndef CONFIG_XPL_BUILD */
#define OSC (V_OSCK/1000000)
const struct dpll_params dpll_ddr = {
return &dpll_ddr;
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
#define MAX_NR_LEDS 10
#define MAX_PIN_NUMBER 128
"Set LEDs defined in environment",
"<0|1>"
);
-#endif /* !CONFIG_SPL_BUILD */
+#endif /* !CONFIG_XPL_BUILD */
void draco_init_ddr(void);
int draco_read_eeprom(void);
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
/* Mux for init: uart?, i2c0 to read the main EEPROM */
void enable_uart0_pin_mux(void);
void enable_uart1_pin_mux(void);
/* Main mux function to enable other pinmux required on the board */
void enable_board_pin_mux(void);
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
#endif /* _BOARD_AM335X_H_ */
* (C) Copyright 2013 Siemens Schweiz AG
*/
-#if !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_XPL_BUILD)
#include <env.h>
#include <g_dnl.h>
{
return factory_dat.version;
}
-#endif /* defined(CONFIG_SPL_BUILD) */
+#endif /* defined(CONFIG_XPL_BUILD) */
at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
}
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
#include <spl.h>
#include <nand.h>
# u-boot:/board/ti/am335x/Makefile
# Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y := mux.o
endif
obj-y += board.o
obj-y += ../common/board_am335x.o
obj-y += ../common/eeprom.o
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-y += ../common/factoryset.o
endif
#include "../common/eeprom.h"
#include "../common/factoryset.h"
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
static struct draco_baseboard_id __section(".data") settings;
#if DDR_PLL_FREQ == 303
printf("hw version: \t'%s'\n", settings.chip.shwver);
printf("max freq: \t%d MHz\n", dpll_mpu_opp100.m);
}
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
#define AM335X_NAND_ECC_MASK 0x0f
#define AM335X_NAND_ECC_TYPE_16 0x02
return 0;
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
/*
* Read header information from EEPROM into global structure.
*/
{
return;
}
-#endif /* if def CONFIG_SPL_BUILD */
+#endif /* if def CONFIG_XPL_BUILD */
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
}
#endif
-#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
- (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD))
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_XPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH) && defined(CONFIG_XPL_BUILD))
static void cpsw_control(int enabled)
{
/* VTP can be added here */
""
);
#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
-#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
+#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_XPL_BUILD)) */
# u-boot:/board/ti/am335x/Makefile
# Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y := mux.o
endif
obj-y += board.o
obj-y += ../common/board_am335x.o
obj-y += ../common/eeprom.o
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-y += ../common/factoryset.o
endif
#include "../common/eeprom.h"
#include "../common/factoryset.h"
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void draco_init_ddr(void)
{
struct emif_regs pxm2_ddr3_emif_reg_data = {
return 0;
}
-#endif /* if def CONFIG_SPL_BUILD */
+#endif /* if def CONFIG_XPL_BUILD */
-#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
- (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD))
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_XPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH) && defined(CONFIG_XPL_BUILD))
static void cpsw_control(int enabled)
{
/* VTP can be added here */
.host_port_num = 0,
.version = CPSW_CTRL_VERSION_2,
};
-#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
+#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_XPL_BUILD)) */
#if defined(CONFIG_DRIVER_TI_CPSW) || \
(defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
int board_eth_init(struct bd_info *bis)
{
int n = 0;
-#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
- (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD))
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_XPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH) && defined(CONFIG_XPL_BUILD))
struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
#ifdef CONFIG_FACTORYSET
int rv;
# u-boot:/board/ti/am335x/Makefile
# Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y := mux.o
endif
obj-y += board.o
obj-y += ../common/board_am335x.o
obj-y += ../common/eeprom.o
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-y += ../common/factoryset.o
endif
#include "../common/eeprom.h"
#include "../common/factoryset.h"
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
/*
* Read header information from EEPROM into global structure.
*/
REQUEST_AND_PULSE_RESET(MAXTOUCH_RESET_GPIO);
REQUEST_AND_PULSE_RESET(DISPLAY_RESET_GPIO);
}
-#endif /* if def CONFIG_SPL_BUILD */
+#endif /* if def CONFIG_XPL_BUILD */
#if defined(CONFIG_DRIVER_TI_CPSW)
static void cpsw_control(int enabled)
int n = 0;
int rv;
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
factoryset_env_set();
#endif
return n;
}
#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
-#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
+#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_XPL_BUILD)) */
#if defined(CONFIG_HW_WATCHDOG)
static bool hw_watchdog_init_done;
#endif /* CONFIG_MACB */
#endif
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
#include <spl.h>
#include <nand.h>
#include <spi_flash.h>
at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
}
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
#include <spl.h>
#include <nand.h>
#include <spi_flash.h>
return 0;
}
-#if !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_XPL_BUILD)
#if defined(CONFIG_BOARD_AXM)
/*
* Booting the Fallback Image.
#
# Copyright (c) 2019 Western Digital Corporation or its affiliates.
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
else
obj-y += unleashed.o
obj-$(CONFIG_ID_EEPROM) += hifive-platform-i2c-eeprom.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
else
obj-y += unmatched.o
# SPDX-License-Identifier: GPL-2.0+
#
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y := ../../renesas/rcar-common/gen3-spl.o
else
obj-y := ek874.o ../../renesas/rcar-common/common.o
setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#include <linux/libfdt.h>
#include <spl.h>
#include <asm/arch/mx6-ddr.h>
return 0;
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
int misc_init_r(void)
{
uchar data[128];
spl_boot_list[1] = BOOT_DEVICE_BOARD;
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#include <asm/arch/mx6-ddr.h>
static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
.dram_sdclk_0 = 0x00020030,
* Board: MB<Board> Var<VarCPN>.<VarFG> Rev.<Revision>-<BOM>
*/
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
#include <command.h>
#include <console.h>
#include <misc.h>
int dram_init(void)
{
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
int rv;
struct udevice *dev;
rv = uclass_get_device(UCLASS_RAM, 0, &dev);
return fdtdec_setup_memory_banksize();
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
#
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
else
obj-y += stm32mp1.o
#
obj-y := starfive_visionfive2.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_XPL_BUILD) += spl.o
obj-$(CONFIG_ID_EEPROM) += visionfive2-i2c-eeprom.o
return 0;
}
-#if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_XPL_BUILD)
static void nand_pinmux_setup(void)
{
unsigned int pin;
#endif
#endif /* CONFIG_MMC */
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
static void sunxi_spl_store_dram_size(phys_addr_t dram_size)
{
else
printf("Failed to set core voltage! Can't set CPU frequency\n");
}
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
#ifdef CONFIG_USB_GADGET
int g_dnl_board_usb_cable_connected(void)
}
#endif
-#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
- (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD))
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_XPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH) && defined(CONFIG_XPL_BUILD))
static void cpsw_control(int enabled)
{
/* VTP can be added here */
* when we build an SPL that has neither option but full U-Boot will.
*/
#if ((defined(CONFIG_SPL_ETH) || defined(CONFIG_SPL_USB_ETHER)) \
- && defined(CONFIG_SPL_BUILD)) || \
+ && defined(CONFIG_XPL_BUILD)) || \
((defined(CONFIG_DRIVER_TI_CPSW) || \
defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
- !defined(CONFIG_SPL_BUILD))
+ !defined(CONFIG_XPL_BUILD))
int board_eth_init(struct bd_info *bis)
{
int rv, n = 0;
mac_addr[4] = mac_lo & 0xFF;
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
- (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD))
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_XPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH) && defined(CONFIG_XPL_BUILD))
if (!env_get("ethaddr")) {
printf("<ethaddr> not set. Validating first E-fuse MAC\n");
#endif
#if defined(CONFIG_USB_ETHER) && \
- (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER))
+ (!defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_USB_ETHER))
if (is_valid_ether_addr(mac_addr))
eth_env_set_enetaddr("usbnet_devaddr", mac_addr);
#include <asm/arch/sys_proto.h>
#include <spl.h>
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
#include <asm/arch/mx6-ddr.h>
#define IMX6DQ_DRIVE_STRENGTH 0x30
#include <linux/libfdt.h>
#include <spl.h>
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
#include <fsl_esdhc_imx.h>
#include <spl.h>
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
obj-y += pico-imx8mq.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_1gb.o lpddr4_timing_2gb.o lpddr4_timing_3gb.o lpddr4_timing_4gb.o
endif
#include <init.h>
#include <net.h>
#include <pci.h>
-#if !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_XPL_BUILD)
#include <bootcount.h>
#endif
#include <asm/global_data.h>
}
#endif
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_LATE_INIT)
+#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_BOARD_LATE_INIT)
int board_late_init(void)
{
pci_dev_t bdf;
}
#endif
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_PCI)
+#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_PCI)
static int pcie_get_link_speed_width(pci_dev_t bdf, int *speed, int *width)
{
struct udevice *dev;
#
obj-y += jaguar_rk3588.o
-ifneq ($(CONFIG_SPL_BUILD),y)
+ifneq ($(CONFIG_XPL_BUILD),y)
obj-y += ../common/common.o
endif
#
obj-y += puma-rk3399.o
-ifneq ($(CONFIG_SPL_BUILD),y)
+ifneq ($(CONFIG_XPL_BUILD),y)
obj-y += ../common/common.o
endif
#
obj-y += ringneck-px30.o
-ifneq ($(CONFIG_SPL_BUILD),y)
+ifneq ($(CONFIG_XPL_BUILD),y)
obj-y += ../common/common.o
endif
#
obj-y += tiger_rk3588.o
-ifneq ($(CONFIG_SPL_BUILD),y)
+ifneq ($(CONFIG_XPL_BUILD),y)
obj-y += ../common/common.o
endif
}
#endif
-#if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
- (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD)))
+#if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_XPL_BUILD) || \
+ (defined(CONFIG_SPL_ETH) && defined(CONFIG_XPL_BUILD)))
static void request_and_set_gpio(int gpio, char *name, int val)
{
int ret;
gpmc_init();
#endif
-#if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
- (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD)))
+#if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_XPL_BUILD) || \
+ (defined(CONFIG_SPL_ETH) && defined(CONFIG_XPL_BUILD)))
if (board_is_icev2()) {
int rv;
u32 reg;
int board_late_init(void)
{
struct udevice *dev;
-#if !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_XPL_BUILD)
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;
#endif
env_set("boot_fit", "1");
#endif
-#if !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_XPL_BUILD)
/* try reading mac address from efuse */
mac_lo = readl(&cdev->macid0l);
mac_hi = readl(&cdev->macid0h);
return opp;
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
/* No env to setup for SPL */
static inline void setup_board_eeprom_env(void) { }
#endif
}
-#else /* CONFIG_SPL_BUILD */
+#else /* CONFIG_XPL_BUILD */
/* Override function to read eeprom information: actual i2c read done by SPL*/
void do_board_detect(void)
set_board_info_env(name);
}
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
void vcores_init(void)
{
if (board_is_bbai())
env_set("console", "ttyS0,115200n8");
-#if !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_XPL_BUILD)
board_ti_set_ethaddr(2);
#endif
}
#endif
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
+#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
int spl_start_uboot(void)
{
/* break into full u-boot on 'c' */
return fdtdec_setup_memory_banksize();
}
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
void spl_board_init(void)
{
}
#endif
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
#if CONFIG_IS_ENABLED(USB_STORAGE)
static int fixup_usb_boot(const void *fdt_blob)
{
struct ti_common_eeprom *ep;
ep = TI_EEPROM_DATA;
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
if (ep->header == TI_EEPROM_HEADER_MAGIC)
return 0; /* EEPROM has already been read */
#endif
struct ti_common_eeprom *ep;
ep = TI_EEPROM_DATA;
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
if (ep->header == DRA7_EEPROM_HEADER_MAGIC)
return 0; /* EEPROM has already been read */
#endif
* Always execute EEPROM read by not allowing to bypass it during the
* first invocation of SPL which happens on the R5 core.
*/
-#if !(defined(CONFIG_SPL_BUILD) && defined(CONFIG_CPU_V7R))
+#if !(defined(CONFIG_XPL_BUILD) && defined(CONFIG_CPU_V7R))
if (ep->header == TI_EEPROM_HEADER_MAGIC) {
debug("%s: EEPROM has already been read\n", __func__);
return 0;
return 0;
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void do_board_detect(void)
{
int rc;
snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
"Board: %s REV %s\n", bname, board_ti_get_rev());
}
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
void vcores_init(void)
{
}
#endif
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
+#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
int spl_start_uboot(void)
{
/* break into full u-boot on 'c' */
}
#endif
-#if defined(CONFIG_SPL_BUILD) && (defined(CONFIG_TARGET_J7200_A72_EVM) || defined(CONFIG_TARGET_J7200_R5_EVM) || \
+#if defined(CONFIG_XPL_BUILD) && (defined(CONFIG_TARGET_J7200_A72_EVM) || defined(CONFIG_TARGET_J7200_R5_EVM) || \
defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J721E_R5_EVM))
void spl_perform_fixups(struct spl_image_info *spl_image)
{
printf("Detected: %s rev %s\n", ep.name, ep.version);
daughter_card_detect_flags[i] = true;
- if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
+ if (!IS_ENABLED(CONFIG_XPL_BUILD)) {
int j;
/*
* Populate any MAC addresses from daughtercard into the U-Boot
}
}
- if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
+ if (!IS_ENABLED(CONFIG_XPL_BUILD)) {
char name_overlays[1024] = { 0 };
for (i = 0; i < ARRAY_SIZE(ext_cards); i++) {
printf("Detected: %s rev %s\n", ep.name, ep.version);
daughter_card_detect_flags[i] = true;
- if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
+ if (!IS_ENABLED(CONFIG_XPL_BUILD)) {
int j;
/*
* Populate any MAC addresses from daughtercard into the U-Boot
}
}
- if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
+ if (!IS_ENABLED(CONFIG_XPL_BUILD)) {
char name_overlays[1024] = { 0 };
for (i = 0; i < ARRAY_SIZE(ext_cards); i++) {
return 0;
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void spl_board_init(void)
{
spl_init_keystone_plls();
}
#endif
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void spl_init_keystone_plls(void)
{
init_plls();
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT)
+#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT)
int rc;
rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
}
#endif
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void spl_init_keystone_plls(void)
{
init_plls();
}
#endif
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void spl_init_keystone_plls(void)
{
init_plls();
}
#endif
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void spl_init_keystone_plls(void)
{
init_plls();
}
#endif /* CONFIG_SPL_OS_BOOT */
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
/*
* Routine: get_board_mem_timings
* Description: If we use SPL then there is no x-loader nor config header
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
timings->mr = MICRON_V_MR_165;
}
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
/*
* Routine: misc_init_r
}
#endif
-#if defined(CONFIG_DRIVER_DM9000) & !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_DRIVER_DM9000) & !defined(CONFIG_XPL_BUILD)
/*
* Routine: board_eth_init
* Description: Setting up the Ethernet hardware.
# Remove quotes
hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))
-obj-$(CONFIG_SPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o
+obj-$(CONFIG_XPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o
MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
-#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_XPL_BUILD)
/* Apalis MMC1 */
iomux_v3_cfg_t const usdhc1_pads[] = {
MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
};
-#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
+#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_XPL_BUILD */
int mx6_rgmii_rework(struct phy_device *phydev)
{
}
#endif
-#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_XPL_BUILD)
/* use the following sequence: eMMC, MMC1, SD1 */
struct fsl_esdhc_cfg usdhc_cfg[CFG_SYS_FSL_USDHC_NUM] = {
{USDHC3_BASE_ADDR},
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
}
-#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
+#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_XPL_BUILD */
int board_phy_config(struct phy_device *phydev)
{
}
#endif
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#include <spl.h>
#include <linux/libfdt.h>
#include "asm/arch/mx6q-ddr.h"
{
}
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
static struct mxc_serial_plat mxc_serial_plat = {
.reg = (struct mxc_uart *)UART1_BASE,
* Helpers for i.MX OTP fusing during module production
*/
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
#include <command.h>
#include <console.h>
#include <fuse.h>
"OTP fusing during module update",
"updt_fuse [-n] [-y] - boot cfg fast boot mode fusing"
);
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
return programmed;
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static int pf0100_prog(void)
{
int rc;
"Program the OTP fuses on the PMIC PF0100",
""
);
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
# Copyright (c) 2014 Marcel Ziswiler
# SPDX-License-Identifier: GPL-2.0+
-obj-$(CONFIG_SPL_BUILD) += apalis_t30-spl.o
+obj-$(CONFIG_XPL_BUILD) += apalis_t30-spl.o
obj-y += apalis_t30.o
MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
-#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_XPL_BUILD)
/* Colibri MMC */
iomux_v3_cfg_t const usdhc1_pads[] = {
MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
-#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
+#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_XPL_BUILD */
/* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */
iomux_v3_cfg_t const gpio_pads[] = {
}
#endif
-#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_XPL_BUILD)
/* use the following sequence: eMMC, MMC */
struct fsl_esdhc_cfg usdhc_cfg[CFG_SYS_FSL_USDHC_NUM] = {
{USDHC3_BASE_ADDR},
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
}
-#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
+#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_XPL_BUILD */
int board_phy_config(struct phy_device *phydev)
{
}
#endif
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#include <spl.h>
#include <linux/libfdt.h>
#include "asm/arch/mx6dl-ddr.h"
{
}
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
static struct mxc_serial_plat mxc_serial_plat = {
.reg = (struct mxc_uart *)UART1_BASE,
* Helpers for i.MX OTP fusing during module production
*/
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
#include <command.h>
#include <console.h>
#include <fuse.h>
"OTP fusing during module update",
"updt_fuse [-n] [-y] - boot cfg fast boot mode fusing"
);
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
return programmed;
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static int pf0100_prog(void)
{
int rc;
"Program the OTP fuses on the PMIC PF0100",
""
);
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
# Copyright (c) 2013-2014 Stefan Agner
# SPDX-License-Identifier: GPL-2.0+
-obj-$(CONFIG_SPL_BUILD) += colibri_t30-spl.o
+obj-$(CONFIG_XPL_BUILD) += colibri_t30-spl.o
obj-y += colibri_t30.o
# Copyright (c) 2016 Toradex, Inc.
# Common for all Toradex modules
-ifeq ($(CONFIG_SPL_BUILD),y)
+ifeq ($(CONFIG_XPL_BUILD),y)
# Necessary to create built-in.o
obj- := __dummy__.o
else
obj-y += verdin-imx8mm.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
endif
obj-y += verdin-imx8mp.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
endif
return 0;
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#include <linux/libfdt.h>
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/sys_proto.h>
#include <spl.h>
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
#include <asm/arch/mx6-ddr.h>
/*
void var_eeprom_print_prod_info(struct var_eeprom *ep)
{
- if (IS_ENABLED(CONFIG_SPL_BUILD))
+ if (IS_ENABLED(CONFIG_XPL_BUILD))
return;
flush_dcache_all();
# SPDX-License-Identifier: GPL-2.0+
obj-y := dart_6ul.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_XPL_BUILD) += spl.o
obj-y += imx8mn_var_som.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
obj-y += ddr4_timing.o
endif
return devno;
}
-#if !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_XPL_BUILD)
#if defined(CONFIG_DISPLAY_BOARDINFO)
}
#endif /* CONFIG_OF_BOARD_SETUP */
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
obj-y += imx93_var_som.o
obj-$(CONFIG_TARGET_IMX93_VAR_SOM) += ../common/imx9_eeprom.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
obj-$(CONFIG_TARGET_IMX93_VAR_SOM) += lpddr4x_timing.o
else
return 0;
}
-#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
+#if defined(CONFIG_XPL_BUILD) || defined(CONFIG_NOR_BOOT)
static const struct ddr_data ddr3_baltos_data = {
.datardsratio0 = MT41K256M16HA125E_RD_DQS,
}
#endif
-#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
- (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD))
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_XPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH) && defined(CONFIG_XPL_BUILD))
static void cpsw_control(int enabled)
{
/* VTP can be added here */
#endif
#if ((defined(CONFIG_SPL_ETH) || defined(CONFIG_SPL_USB_ETHER)) \
- && defined(CONFIG_SPL_BUILD)) || \
+ && defined(CONFIG_XPL_BUILD)) || \
((defined(CONFIG_DRIVER_TI_CPSW) || \
defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
- !defined(CONFIG_SPL_BUILD))
+ !defined(CONFIG_XPL_BUILD))
int board_eth_init(struct bd_info *bis)
{
int rv, n = 0;
mac_addr[4] = mac_lo & 0xFF;
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
- (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD))
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_XPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH) && defined(CONFIG_XPL_BUILD))
if (!env_get("ethaddr")) {
printf("<ethaddr> not set. Validating first E-fuse MAC\n");
# (C) Copyright 2013 Freescale Semiconductor, Inc.
obj-y := wandboard.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_XPL_BUILD) += spl.o
# (C) Copyright 2023
# Svyatoslav Ryhel <clamor95@gmail.com>
-obj-$(CONFIG_SPL_BUILD) += qc750-spl.o
+obj-$(CONFIG_XPL_BUILD) += qc750-spl.o
obj-y += qc750.o
# (C) Copyright 2014 DENX Software Engineering GmbH
# Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += work_92105_spl.o
else
obj-y += work_92105.o
ifndef CONFIG_ARCH_ZYNQ
obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o
endif
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_CMD_FRU) += fru.o fru_ops.o
endif
return fdt_blob;
}
- if (!IS_ENABLED(CONFIG_SPL_BUILD) &&
+ if (!IS_ENABLED(CONFIG_XPL_BUILD) &&
!IS_ENABLED(CONFIG_VERSAL_NO_DDR) &&
!IS_ENABLED(CONFIG_ZYNQMP_NO_DDR)) {
fdt_blob = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR;
debug("DTB is not passed via %p\n", fdt_blob);
}
- if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+ if (IS_ENABLED(CONFIG_XPL_BUILD)) {
/*
* FDT is at end of BSS unless it is in a different memory
* region
{
debug("%s: Check %s, default %s\n", __func__, name, board_name);
-#if !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_XPL_BUILD)
if (IS_ENABLED(CONFIG_REGEX)) {
struct slre slre;
int ret;
ulong max_size;
u32 status = 0;
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SYSRESET_MICROBLAZE)
+#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_SYSRESET_MICROBLAZE)
int ret;
ret = device_bind_driver(gd->dm_root, "mb_soft_reset",
ifeq ($(init-objs),)
ifneq ($(wildcard $(srctree)/$(src)/ps7_init_gpl.c),)
init-objs := ps7_init_gpl.o
-$(if $(CONFIG_SPL_BUILD),\
+$(if $(CONFIG_XPL_BUILD),\
$(warning Put custom ps7_init_gpl.c/h to board/xilinx/zynq/custom_hw_platform/))
endif
endif
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_CMD_ZYNQ) += cmds.o
obj-$(CONFIG_CMD_ZYNQ_RSA) += bootimg.o
endif
-obj-$(CONFIG_SPL_BUILD) += $(init-objs)
+obj-$(CONFIG_XPL_BUILD) += $(init-objs)
# Suppress "warning: function declaration isn't a prototype"
CFLAGS_REMOVE_ps7_init_gpl.o := -Wstrict-prototypes
DECLARE_GLOBAL_DATA_PTR;
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DEBUG_UART_BOARD_INIT)
+#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_DEBUG_UART_BOARD_INIT)
void board_debug_uart_init(void)
{
/* Add initialization sequence if UART is not configured */
int board_init(void)
{
- if (IS_ENABLED(CONFIG_SPL_BUILD))
+ if (IS_ENABLED(CONFIG_XPL_BUILD))
printf("Silicon version:\t%d\n", zynq_get_silicon_version());
if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
ifeq ($(init-objs),)
ifneq ($(wildcard $(srctree)/$(src)/psu_init_gpl.c),)
init-objs := psu_init_gpl.o
-$(if $(CONFIG_SPL_BUILD),\
+$(if $(CONFIG_XPL_BUILD),\
$(warning Put custom psu_init_gpl.c/h to board/xilinx/zynqmp/custom_hw_platform/))
endif
endif
obj-$(CONFIG_$(SPL_)ZYNQMP_PSU_INIT_ENABLED) += $(init-objs)
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
ifneq ($(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE),"")
-obj-$(CONFIG_SPL_BUILD) += pm_cfg_obj.o
+obj-$(CONFIG_XPL_BUILD) += pm_cfg_obj.o
$(obj)/pm_cfg_obj.o: $(shell cd $(srctree); readlink -f $(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE)) FORCE
endif
endif
return 0;
}
-#if !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_XPL_BUILD)
# if defined(CONFIG_DEBUG_UART_BOARD_INIT)
void board_debug_uart_init(void)
{
return multiboot;
}
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
static void restore_jtag(void)
{
if (current_el() != 3)
int ret;
#endif
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
/* Check *at build time* if the filename is an non-empty string */
if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
projects / u-boot.git / commitdiff
