clk: renesas: Synchronize R-Car R8A779A0 V3U clock tables with Linux 6.10.9

Synchronize R-Car R8A779A0 V3U clock tables with Linux 6.10.9,
commit 1611860f184a2c9e74ed593948d43657734a7098 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index b44d5603edd5db2ae878b4165e5f9f43eda163cb..7875a990c2f83459d93dc28f3d01d5475eb67bff 100644 (file)
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -55,6 +55,17 @@ enum clk_ids {
        DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL2X_3X, CLK_MAIN, \
                 .offset = _offset)
 
+#define CPG_PLL20CR    0x0834  /* PLL20 Control Register */
+#define CPG_PLL21CR    0x0838  /* PLL21 Control Register */
+#define CPG_PLL30CR    0x083c  /* PLL30 Control Register */
+#define CPG_PLL31CR    0x0840  /* PLL31 Control Register */
+
+#define CPG_SD0CKCR    0x870   /* SD-IF0 Clock Frequency Control Register */
+#define CPG_CANFDCKCR  0x878   /* CAN-FD Clock Frequency Control Register */
+#define CPG_MSOCKCR    0x87c   /* MSIOF Clock Frequency Control Register */
+#define CPG_CSICKCR    0x880   /* CSI Clock Frequency Control Register */
+#define CPG_DSIEXTCKCR 0x884   /* DSI Clock Frequency Control Register */
+
 static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
        /* External Clock Inputs */
        DEF_INPUT("extal",  CLK_EXTAL),
@@ -64,10 +75,10 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
        DEF_BASE(".main", CLK_MAIN,     CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
        DEF_BASE(".pll1", CLK_PLL1,     CLK_TYPE_GEN4_PLL1, CLK_MAIN),
        DEF_BASE(".pll5", CLK_PLL5,     CLK_TYPE_GEN4_PLL5, CLK_MAIN),
-       DEF_PLL(".pll20", CLK_PLL20,    0x0834),
-       DEF_PLL(".pll21", CLK_PLL21,    0x0838),
-       DEF_PLL(".pll30", CLK_PLL30,    0x083c),
-       DEF_PLL(".pll31", CLK_PLL31,    0x0840),
+       DEF_PLL(".pll20", CLK_PLL20,    CPG_PLL20CR),
+       DEF_PLL(".pll21", CLK_PLL21,    CPG_PLL21CR),
+       DEF_PLL(".pll30", CLK_PLL30,    CPG_PLL30CR),
+       DEF_PLL(".pll31", CLK_PLL31,    CPG_PLL31CR),
 
        DEF_FIXED(".pll1_div2",         CLK_PLL1_DIV2,  CLK_PLL1,       2, 1),
        DEF_FIXED(".pll20_div2",        CLK_PLL20_DIV2, CLK_PLL20,      2, 1),
@@ -110,17 +121,17 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
        DEF_FIXED("cp",         R8A779A0_CLK_CP,        CLK_EXTAL,      2, 1),
        DEF_FIXED("cl16mck",    R8A779A0_CLK_CL16MCK,   CLK_PLL1_DIV2,  64, 1),
 
-       DEF_GEN4_SDH("sd0h",    R8A779A0_CLK_SD0H,      CLK_SDSRC,         0x870),
-       DEF_GEN4_SD("sd0",      R8A779A0_CLK_SD0,       R8A779A0_CLK_SD0H, 0x870),
+       DEF_GEN4_SDH("sd0h",    R8A779A0_CLK_SD0H,      CLK_SDSRC,         CPG_SD0CKCR),
+       DEF_GEN4_SD("sd0",      R8A779A0_CLK_SD0,       R8A779A0_CLK_SD0H, CPG_SD0CKCR),
 
        DEF_BASE("rpc",         R8A779A0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
        DEF_BASE("rpcd2",       R8A779A0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2,
                 R8A779A0_CLK_RPC),
 
-       DEF_DIV6P1("mso",       R8A779A0_CLK_MSO,       CLK_PLL5_DIV4,  0x87c),
-       DEF_DIV6P1("canfd",     R8A779A0_CLK_CANFD,     CLK_PLL5_DIV4,  0x878),
-       DEF_DIV6P1("csi0",      R8A779A0_CLK_CSI0,      CLK_PLL5_DIV4,  0x880),
-       DEF_DIV6P1("dsi",       R8A779A0_CLK_DSI,       CLK_PLL5_DIV4,  0x884),
+       DEF_DIV6P1("mso",       R8A779A0_CLK_MSO,       CLK_PLL5_DIV4,  CPG_MSOCKCR),
+       DEF_DIV6P1("canfd",     R8A779A0_CLK_CANFD,     CLK_PLL5_DIV4,  CPG_CANFDCKCR),
+       DEF_DIV6P1("csi0",      R8A779A0_CLK_CSI0,      CLK_PLL5_DIV4,  CPG_CSICKCR),
+       DEF_DIV6P1("dsi",       R8A779A0_CLK_DSI,       CLK_PLL5_DIV4,  CPG_DSIEXTCKCR),
 
        DEF_GEN4_OSC("osc",     R8A779A0_CLK_OSC,       CLK_EXTAL,      8),
        DEF_GEN4_MDSEL("r",     R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),