clk: renesas: Synchronize R-Car R8A779G0 V4H clock tables with Linux 6.9.3

Synchronize R-Car R8A779G0 V4H clock tables with Linux 6.9.3,
commit 1b4861e32e461b6fae14dc49ed0f1c7f20af5146 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index 781806eed5892efc0595485062f36efea1078c79..4df0a69cfe10f90505689e537572b3c493ece11a 100644 (file)
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -17,7 +17,7 @@
 
 enum clk_ids {
        /* Core Clock Outputs exported to DT */
-       LAST_DT_CORE_CLK = R8A779G0_CLK_R,
+       LAST_DT_CORE_CLK = R8A779G0_CLK_CP,
 
        /* External Input Clocks */
        CLK_EXTAL,
@@ -136,6 +136,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
        DEF_FIXED("svd2_vip",   R8A779G0_CLK_SVD2_VIP,  CLK_SV_VIP,     2, 1),
        DEF_FIXED("cbfusa",     R8A779G0_CLK_CBFUSA,    CLK_EXTAL,      2, 1),
        DEF_FIXED("cpex",       R8A779G0_CLK_CPEX,      CLK_EXTAL,      2, 1),
+       DEF_FIXED("cp",         R8A779G0_CLK_CP,        CLK_EXTAL,      2, 1),
        DEF_FIXED("viobus",     R8A779G0_CLK_VIOBUS,    CLK_VIO,        1, 1),
        DEF_FIXED("viobusd2",   R8A779G0_CLK_VIOBUSD2,  CLK_VIO,        2, 1),
        DEF_FIXED("vcbus",      R8A779G0_CLK_VCBUS,     CLK_VC,         1, 1),
@@ -187,6 +188,8 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
        DEF_MOD("msi3",         621,    R8A779G0_CLK_MSO),
        DEF_MOD("msi4",         622,    R8A779G0_CLK_MSO),
        DEF_MOD("msi5",         623,    R8A779G0_CLK_MSO),
+       DEF_MOD("pciec0",       624,    R8A779G0_CLK_S0D2_HSC),
+       DEF_MOD("pciec1",       625,    R8A779G0_CLK_S0D2_HSC),
        DEF_MOD("pwm",          628,    R8A779G0_CLK_SASYNCPERD4),
        DEF_MOD("rpc-if",       629,    R8A779G0_CLK_RPCD2),
        DEF_MOD("scif0",        702,    R8A779G0_CLK_SASYNCPERD4),
@@ -225,11 +228,12 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
        DEF_MOD("cmt1",         911,    R8A779G0_CLK_R),
        DEF_MOD("cmt2",         912,    R8A779G0_CLK_R),
        DEF_MOD("cmt3",         913,    R8A779G0_CLK_R),
-       DEF_MOD("pfc0",         915,    R8A779G0_CLK_CL16M),
-       DEF_MOD("pfc1",         916,    R8A779G0_CLK_CL16M),
-       DEF_MOD("pfc2",         917,    R8A779G0_CLK_CL16M),
-       DEF_MOD("pfc3",         918,    R8A779G0_CLK_CL16M),
+       DEF_MOD("pfc0",         915,    R8A779G0_CLK_CP),
+       DEF_MOD("pfc1",         916,    R8A779G0_CLK_CP),
+       DEF_MOD("pfc2",         917,    R8A779G0_CLK_CP),
+       DEF_MOD("pfc3",         918,    R8A779G0_CLK_CP),
        DEF_MOD("tsc",          919,    R8A779G0_CLK_CL16M),
+       DEF_MOD("tsn",          2723,   R8A779G0_CLK_S0D4_HSC),
        DEF_MOD("ssiu",         2926,   R8A779G0_CLK_S0D6_PER),
        DEF_MOD("ssi",          2927,   R8A779G0_CLK_S0D6_PER),
 };

diff --git a/include/dt-bindings/clock/r8a779g0-cpg-mssr.h b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h
index 754c54a6eb06a46dafeeb030df71dc6b96c16866..7850cdc62e2854939627552c8c34be6ff8625563 100644 (file)
--- a/include/dt-bindings/clock/r8a779g0-cpg-mssr.h
+++ b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h
@@ -86,5 +86,6 @@
 #define R8A779G0_CLK_CPEX              74
 #define R8A779G0_CLK_CBFUSA            75
 #define R8A779G0_CLK_R                 76
+#define R8A779G0_CLK_CP                        77
 
 #endif /* __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ */